CN106876256A - SiC double flute UMOSFET devices and preparation method thereof - Google Patents
SiC double flute UMOSFET devices and preparation method thereof Download PDFInfo
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- 238000005516 engineering process Methods 0.000 claims description 18
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- 238000005566 electron beam evaporation Methods 0.000 claims description 14
- 239000001301 oxygen Substances 0.000 claims description 14
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The present invention relates to a kind of preparation method of SiC double flutes UMOSFET devices, it is characterised in that including：Choose SiC substrate；Drift layer, epitaxial layer and source region layer are grown in the SiC substrate continuous surface；The source region layer, the epitaxial layer and the drift layer are performed etching to form grid groove；Ion implanting is carried out to the grid groove and forms gate medium protection zone；The source region layer, the epitaxial layer and the drift layer are performed etching and to form source slot；Ion implanting is carried out to the source slot and forms source slot turning protection zone；Gate dielectric layer and grid layer are grown in the grid groove to form grid；Passivation Treatment simultaneously prepares electrode to form the SiC double flutes UMOSFET devices.The present invention forms Schottky contacts by the interface of source electrode and drift layer and epitaxial layer, while " the be powered deterioration " problem for ensureing not causing body diode, extra Schottky diode is reduced, the reliability of device is improve and is reduced the complexity and cost of device design.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of SiC double flutes UMOSFET devices and its preparation side
Method.
Background technology
Wide bandgap semiconductor materials SiC has larger energy gap, critical breakdown electric field higher, high heat conductance and height
The desirable physicals such as electronics saturation drift velocity and chemical characteristic, are adapted to make high temperature, high pressure, high-power, Flouride-resistani acid phesphatase semiconductor
Device.In field of power electronics, power MOSFET has been widely used, and it has raster data model simple, and switch time is short etc.
Feature.The UMOSFET of vertical stratification relative to transversary MOSFET, cellular size small advantage small with conducting resistance,
Have broad application prospects.
But in UMOSFET, the electric field concentration of Cao Shan corners easilys lead to oxide layer at this and is punctured in advance, for
This phenomenon is even more serious for SiC material.It is that P+ gate mediums are protected by one layer of P+ type doped region of bottom design of grid groove
Shield area, makes the spike electric field of bottom land that the PN junction that P+ gate mediums protection zone is constituted with N- drift layers is transferred to from gate oxide
On, and then alleviate the integrity problem that oxide field brings.And the UMOSFET of dual-slot structure, by source electrode cutting, being somebody's turn to do
The depth that N- drift layers are goed deep into region is greater than depth of the grid oxygen in N- drift layers, using this point, electric field at oxide layer because
Source slot corner is transferred to for the presence of source slot, further improves the breakdown characteristics of device.MOSFET is in current transformer simultaneously
As power switch, when its body diode flows continuously through forward current as freewheeling path, it may occur that " be powered deterioration " phenomenon,
Increase the forward conduction voltage drop of conducting resistance and diode, and cause integrity problem.
Therefore in actual application, it is typically employed in a device source-drain electrode two ends cut-in voltage in parallel and is less than the pole of body two
The method of the Schottky diode of pipe provides freewheeling path.Obvious this method substantially increases the complexity of circuit design
And cost.
The content of the invention
Therefore, to solve technological deficiency and deficiency that prior art is present, the present invention proposes a kind of SiC double flutes UMOSFET
The preparation method of device.
Specifically, the preparation method of a kind of SiC double flutes UMOSFET devices that one embodiment of the invention is proposed, including：
Step 1, selection SiC substrate；
Step 2, grow drift layer, epitaxial layer and source region layer in the SiC substrate continuous surface；
Step 3, the source region layer, the epitaxial layer and the drift layer are performed etching to form grid groove；
Step 4, ion implanting is carried out to the grid groove form gate medium protection zone；
Step 5, the source region layer, the epitaxial layer and the drift layer are performed etching and to form source slot；
Step 6, the source slot is carried out ion implanting formed source slot turning protection zone；
Step 7, in the grid groove gate dielectric layer and grid layer are grown to form grid；
Step 8, Passivation Treatment simultaneously prepare electrode to form the SiC double flutes UMOSFET devices.
In one embodiment of the invention, step 2 includes：
Step 21, using epitaxial growth technology, in drift layer described in the SiC substrate superficial growth；
Step 22, using epitaxial growth technology, in epitaxial layer described in the drift layer superficial growth；
Step 23, using epitaxial growth technology, in source region layer described in the epi-layer surface epitaxial growth.
In one embodiment of the invention, step 3 includes：
Using ICP etching technics, using the first mask plate, the source region layer surface is performed etching, the source region layer,
The grid groove is formed in the epitaxial layer and the drift layer.
In one embodiment of the invention, step 4 includes：
Using autoregistration injection technology, using the first mask plate, Al ion implantings are carried out in the drift to the grid groove
The gate medium protection zone is formed in layer.
In one embodiment of the invention, step 5 includes：
Using ICP etching technics, using the second mask plate, the source region layer surface is performed etching, the source region layer,
The source slot is formed in the epitaxial layer and the drift layer.
In one embodiment of the invention, step 6 includes：
Using autoregistration injection technology, using the second mask plate, Al ion implantings are carried out to the source slot in the drift
Source slot turning protection zone is formed in layer.
In one embodiment of the invention, Al ion implantings are carried out to the source slot, including：
Using the Implantation Energy of 450keV, 7.97 × 1013cm-2Implantation dosage, the source slot is carried out first time Al from
Son injection；
Using the Implantation Energy of 300keV, 4.69 × 1013cm-2Implantation dosage, the source slot is carried out second Al from
Son injection；
Using the Implantation Energy of 200keV, 3.27 × 1013cm-2Implantation dosage, the source slot is carried out third time Al from
Son injection；
Using the Implantation Energy of 120keV, 2.97 × 1013cm-2Implantation dosage, the source slot is carried out the 4th Al from
Son injection.
In one embodiment of the invention, step 7 includes：
Using dry oxygen technique, SiO is grown in the grid groove2Material is forming the gate dielectric layer；
Using HWLPCVD techniques, polycrystalline Si material is grown in the grid groove to form the grid layer；
In one embodiment of the invention, step 8 includes：
In the substrate top surface growth of passivation layer including the grid；
Using etching technics, the passivation layer to the gate surface performs etching to form electrode contact hole；
Using electron beam evaporation process, metal material formation source electrode is grown in the source slot and the electrode contact hole
And gate electrode；
Using electron beam evaporation process, drain electrode is formed in substrate lower surface growth metal material described to ultimately form
SiC double flute UMOSFET devices.
A kind of SiC double flutes UMOSFET devices that another embodiment of the present invention is proposed, the method provided by above-described embodiment
Prepare and formed.
Above-described embodiment, Schottky contacts are formed by the interface of source electrode and N- drift layers and epitaxial layer, are substituted external
Schottky diode as freewheeling path, while " the be powered deterioration " problem for ensureing not causing body diode, reduce
Extra Schottky diode, improves the reliability of device and reduces the complexity and cost of device design.In addition, this hair
The dual-slot structure that bright utilization double flute UMSFET is carried, by ion self-registered technology, without photoetching, forms P+ gate mediums protection zone
With P+ source slots turning protection zone, the breakdown characteristics of device are further improved, realized preferably with less technique cost
Device performance.
By the detailed description below with reference to accompanying drawing, other side of the invention and feature become obvious.But should know
Road, the accompanying drawing is only the purpose design explained, not as the restriction of the scope of the present invention, because it should refer to
Appended claims.It should also be noted that unless otherwise noted, it is not necessary to scale accompanying drawing, they only try hard to concept
Ground explanation structure described herein and flow.
Brief description of the drawings
Below in conjunction with accompanying drawing, specific embodiment of the invention is described in detail.
Fig. 1 is a kind of structural representation of SiC double flutes UMOSFET devices provided in an embodiment of the present invention；
Fig. 2 is a kind of schematic diagram of SiC double flutes UMOSFET device preparation methods provided in an embodiment of the present invention；
Fig. 3 a- Fig. 3 k are a kind of process schematic representation of SiC double flutes UMOSFET devices provided in an embodiment of the present invention.
Specific embodiment
To enable the above objects, features and advantages of the present invention more obvious understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of structural representation of SiC double flutes UMOSFET devices provided in an embodiment of the present invention.
SiC double flutes UMOSFET devices of the present invention include drain electrode 11, N+ substrates 1, N- drift layers 2, P- epitaxial layers 3, N+ source region layers 4, source electrode
10th, P+ source slots turning protection zone 6, groove gate medium 7, polysilicon 8, P+ gate mediums protection zone 5, gate electrode 9.
Preferably, the depth of source slot more than grid groove depth, and source slot width be equal to P+ source slots turning protection zone 6 width
Degree；The width of grid groove is equal to the width of P+ gate mediums protection zone 5, between the source electrode 10 and N- drift layers 2 and P- epitaxial layers 3
Interface is Schottky contacts, and remaining is Ohmic contact.
Alternatively, source slot depth is 3 μm, and grid groove depth is 2.5 μm, by inductively coupled plasma (inductively
Cowpled plasmas, abbreviation ICP) etching formation.The width of source slot and P+ source slots turning protection zone 6 is respectively 1 μm, grid groove
Width with P+ gate mediums protection zone 5 is respectively 1.5 μm.
Alternatively, N+ substrates 1 are that thickness is 200 μm~500 μm, and Nitrogen ion doping concentration is 5 × 1018cm-3~1 ×
1020cm-3N-type SiC substrate 1.N- drift layers 2 are that thickness is 10 μm~20 μm, and Nitrogen ion doping concentration is 1 × 1015cm-3~6
×1015cm-3N-type SiC epitaxial layer.
Alternatively, the thickness of P+ source slots turning protection zone 6 is 0.5 μm, and Al ion dopings concentration is 3 × 1018cm-3。P+
The thickness of gate medium protection zone 5 is 0.5 μm, and Al ion dopings concentration is 3 × 1018cm-3。
Alternatively, the P- epitaxial layers 3 are that thickness is 1 μm~1.5 μm, and Al ion dopings concentration is 1 × 1017cm-3P
Type SiC epitaxial layer.N+ source region layers 4 are that thickness is 0.5 μm, and Nitrogen ion doping concentration is 5 × 1018cm-3N-type SiC epitaxial layer.
Alternatively, the groove gate medium 7 is the silica that thickness is 100nm, is formed by dry oxygen technique.Polysilicon 8
It is poly Si, its depth is 2.4 μm, and width is 1.3 μm, by depositing the whole grid slot structure of filling.Deposit field oxide or
Si3N4Layer opens electrode hole as passivation layer, corrosion and passivation layer.Gate electrode 9, drain electrode 11 and source electrode 10 and its Schottky contacts pass through
Electron beam evaporation metal is formed.
The embodiment of the present invention, the present invention introduces Schottky diode by source slot, substitutes external Schottky diode
As freewheeling path, while " the be powered deterioration " problem for ensureing not causing body diode, extra Schottky two is reduced
Pole pipe, improves the reliability of device and reduces the complexity and cost of device design.
It should be noted that the grid being related in the present invention, refers to the entirety that gate dielectric layer and gate material layer are constituted
Structure, such as grid are the overall structure that grid oxygen material and polycrystalline silicon material are constituted.Gate electrode of the present invention, refer in order to
Metallization is interconnected and in the metal material of gate surface of the invention deposit, is equally similar to statement such as source electrode and drain electrode.
Embodiment two
Fig. 2 is referred to, Fig. 2 is a kind of signal of SiC double flutes UMOSFET device preparation methods provided in an embodiment of the present invention
Figure.The preparation method may include steps of：
Step 1, selection SiC substrate；
Step 2, grow drift layer, epitaxial layer and source region layer in the SiC substrate continuous surface；
Step 3, the source region layer, the epitaxial layer and the drift layer are performed etching to form grid groove；
Step 4, ion implanting is carried out to the grid groove form gate medium protection zone；
Step 5, the source region layer, the epitaxial layer and the drift layer are performed etching and to form source slot；
Step 6, the source slot is carried out ion implanting formed source slot turning protection zone；
Step 7, in the grid groove gate dielectric layer and grid layer are grown to form grid；
Step 8, Passivation Treatment simultaneously prepare electrode to form the SiC double flutes UMOSFET devices.
Alternatively, for step 2, can include：
Step 21, using epitaxial growth technology, in drift layer described in the SiC substrate superficial growth；
Step 22, using epitaxial growth technology, in epitaxial layer described in the drift layer superficial growth；
Step 23, using epitaxial growth technology, in source region layer described in the epi-layer surface epitaxial growth.
Specifically, for step 21, including：
10 μm~20 μm drift layers of Nitrogen ion doping are grown in N-type SiC substrate, doping concentration is 1 × 1015cm-3~
6×1015cm-3, epitaxial temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure hydrogen
Gas, impurity source is liquid nitrogen；
Specifically, for step 22, including：
Nitrogen ion doping drift layer on grow 1 μm~1.5 μm epitaxial layers of Al ion dopings, doping concentration be 1 ×
1017cm-3~1 × 1018cm-3, epitaxial temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, carrying gas
Body is pure hydrogen, and impurity source is three base first aluminium；
Specifically, for step 23, including：
0.5 μm of source region layer of Nitrogen ion doping is grown on epitaxial layer, doping concentration is 5 × 1018cm-3, epitaxial temperature
It it is 1600 DEG C, pressure is 100mbar, reacting gas is silane and propane, and carrier gas is pure hydrogen, and impurity source is liquid nitrogen
Gas；
Alternatively, for step 3, can include：
Using ICP etching technics, using the first mask plate, the source region layer surface is performed etching, the source region layer,
The grid groove is formed in the epitaxial layer and the drift layer.
Specifically, for step 3, including：
Using ICP techniques, etching forms grid groove, and width is 1.5 μm, and depth is 2.5 μm, wherein, ICP coil powers
850W, source power 100W, reacting gas SF6And O2Respectively 48sccm and 12sccm；
Alternatively, for step 4, can include：
Using autoregistration injection technology, using the first mask plate, Al ion implantings are carried out in the drift to the grid groove
The gate medium protection zone is formed in layer.
Specifically, for step 4, including：
Multiple Al ions autoregistration is carried out in drift layer to inject, form depth for 0.5 μm using the etch mask of grid groove, it is dense
Spend is 3 × 1018cm-3Gate medium protection zone, implantation temperature be 650 DEG C.
Alternatively, for step 5, can include：
Using ICP etching technics, using the second mask plate, the source region layer surface is performed etching, the source region layer,
The source slot is formed in the epitaxial layer and the drift layer.
Specifically, for step 5, including：
Etch to form source slot using ICP techniques, width is 1 μm, depth is 3 μm, ICP coil power 850W, source power
100W, reacting gas SF6And O2Respectively 48sccm and 12sccm；
Alternatively, for step 6, can include：
Using autoregistration injection technology, using the second mask plate, Al ion implantings are carried out to the source slot in the drift
Source slot turning protection zone is formed in layer.
Wherein, Al ion implantings are carried out to the source slot, including：
Using the Implantation Energy of 450keV, 7.97 × 1013cm-2Implantation dosage, the grid groove is carried out first time Al from
Son injection；
Using the Implantation Energy of 300keV, 4.69 × 1013cm-2Implantation dosage, the grid groove is carried out second Al from
Son injection；
Using the Implantation Energy of 200keV, 3.27 × 1013cm-2Implantation dosage, the grid groove is carried out third time Al from
Son injection；
Using the Implantation Energy of 120keV, 2.97 × 1013cm-2Implantation dosage, the grid groove is carried out the 4th Al from
Son injection.
Specifically, for step 6, including：
Multiple Al ions autoregistration is carried out in drift layer to inject, form depth for 0.5 μm using the etch mask of source slot, it is dense
Spend is 3 × 1018cm-3Source slot turning protection zone, implantation temperature be 650 DEG C；
Alternatively, for step 7, can include：
Using dry oxygen technique, SiO is grown in the grid groove2Material is forming the gate dielectric layer；
Using hot wall low pressure chemical vapour deposition (hot wall low pressure chemical vapour
Deposition, abbreviation HWLPCVD) technique, polycrystalline Si material is grown in the grid groove to form the grid layer；
Specifically, step 7 includes：
SiO is prepared at 1150 DEG C using dry oxygen technique2Gate dielectric layer, thickness is 100nm, then at 1050 DEG C, NO atmosphere
Annealed under enclosing, reduced SiO2The roughness of film surface；
Grid groove is filled up using HWLPCVD techniques growth poly Si, deposition temperature is 600~650 DEG C, and deposit pressure is 60
~80Pa, reacting gas is silane and hydrogen phosphide, and carrier gas is helium；
Alternatively, for step 8, can include：
In the substrate top surface growth of passivation layer including grid；
Using etching technics, the passivation layer to the gate surface performs etching to form electrode contact hole；
Using electron beam evaporation process, metal material formation source electrode is grown in the source slot and the electrode contact hole
With gate electrode 9；
Using electron beam evaporation process, drain electrode is formed in substrate lower surface growth metal material described to ultimately form
SiC double flute UMOSFET devices.
Specifically, step 8 includes：
One layer of field oxygen or Si are deposited in device surface3N4Layer, then open electrode contact hole；
Electron beam evaporation Ti/Ni/Au, prepares electrode, finally short annealing 3min in an ar atmosphere, and temperature is 1050 DEG C.
Because drift layer and outer layer doping concentration are relatively low, Schottky contacts are formed in source electrode and drift layer and epitaxial layer interface, other
Interface forms Ohmic contact.
The embodiment of the present invention, the present invention introduces Schottky diode by source slot, substitutes external Schottky diode
As freewheeling path, while " the be powered deterioration " problem for ensureing not causing body diode, extra Schottky two is reduced
Pole pipe, improves the reliability of device and reduces the complexity and cost of device design.In addition, the embodiment of the present invention is using double
The dual-slot structure that groove UMSFET is carried, by ion self-registered technology, without photoetching, forms gate medium protection zone and source slot turning
Protection zone, further improves the breakdown characteristics of device, and more preferable device performance is realized with less technique cost.
Embodiment two
Fig. 3 is referred to, Fig. 3 is to present embodiments provide another SiC double flutes UMOSFET device preparation methods, the preparation
Method comprises the following steps：
Step a, in the Epitaxial growth N- drift layers 2 of N-type SiC substrate 1, as shown in Figure 3 a.
It it is first 200 μm to thickness, Nitrogen ion doping concentration is 5 × 1018cm-3N-type SiC substrate to carry out RCA standards clear
Wash, be then 10 μm in the Epitaxial growth thickness of whole SiC substrate 1, Nitrogen ion doping concentration is 1 × 1015cm-3N- drift
Layer 2.Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure
Hydrogen, impurity source is liquid nitrogen.
Step b, epitaxial growth P- epitaxial layer 3, as shown in Figure 3 b.
It is 1 μm that a layer thickness is grown on N- drift layers 2, and Al ion dopings concentration is 1 × 1017cm-3P- epitaxial layers 3.
Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure hydrogen
Gas, impurity source is three base first aluminium.
Step c, epitaxial growth N+ source region layer 4, as shown in Figure 3 c.
It is 0.5 μm that a layer thickness is grown on P- epitaxial layers 3, and Nitrogen ion doping concentration is 5 × 1018cm-3N+ source region layers
4.Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure hydrogen
Gas, impurity source is liquid nitrogen.
Step d, etching forms grid groove, as shown in Figure 3 d.
One layer of magnetron sputtering firstTi films as ICP etch masks, then gluing photoetching carries out ICP etchings,
It is 1.5 μm to etch the width of groove, and depth is 2.5 μm, is finally removed photoresist, and goes etch mask, cleans into mating plate.Its process conditions
For：ICP coil power 850W, source power 100W, reacting gas SF6And O2Respectively 48sccm and 12sccm.
Step e, carries out multiple Al ions autoregistration and injects, such as Fig. 3 e institutes using the etch mask of grid groove in N- drift layers 2
Show.
Successively using 450keV, 300keV, 200keV and 120keV Implantation Energy, by implantation dosage be 7.97 ×
1013cm-2、4.69×1013cm-2、3.27×1013cm-2With 2.97 × 1013cm-2Al ions, be injected into four times N- drift
The injection region of layer 2, it is 0.5 μm to form depth, and concentration is 3 × 1018cm-3P+ gate mediums protection zone 5, implantation temperature is 650
℃。
Step f, etching forms source slot, as illustrated in figure 3f.
One layer of magnetron sputtering firstTi films as ICP etch masks, then gluing photoetching carries out ICP etchings,
It is 1 μm to etch the width of groove, and depth is 3 μm, is finally removed photoresist, and goes etch mask, cleans into mating plate.Its process conditions is：ICP
Coil power 850W, source power 100W, reacting gas SF6And O2Respectively 48sccm and 12sccm.
Step g, carries out multiple Al ions autoregistration and injects, such as Fig. 3 g institutes using the etch mask of source slot in N- drift layers 2
Show.
First successively using 450keV, 300keV, 200keV and 120keV Implantation Energy, by implantation dosage be 7.97 ×
1013cm-2、4.69×1013cm-2、3.27×1013cm-2With 2.97 × 1013cm-2Al ions, be injected into four times N- drift
The injection region of layer 2, it is 0.5 μm to form depth, and concentration is 3 × 1018cm-3P+ source slots turning protection zone 6, implantation temperature is 650
℃。
Surface of SiC is cleaned using RCA cleanings standard again, the protection of C films is made after drying, then 1700~1750
Ion-activated annealing 10min is carried out in DEG C argon atmosphere.
Step h, preparation vessel gate medium 7, material therefor is SiO2, as illustrated in figure 3h.
SiO is prepared at 1150 DEG C using dry oxygen technique2Gate dielectric layer, thickness is 100nm, then at 1050 DEG C, NO atmosphere
Annealed under enclosing, reduced SiO2The roughness of film surface.
Step i, prepares poly Si grid, as shown in figure 3i.
Grid groove is filled up using low pressure hot wall chemical vapor deposition method growth poly Si, deposition temperature is 600~650 DEG C, is formed sediment
It is by force 60~80Pa to overstock, and reacting gas is silane and hydrogen phosphide, and carrier gas is helium, then gluing photoetching, etches poly
Si layers, polysilicon gate is formed, finally removed photoresist, cleaned.
Step j, prepares passivation layer, as shown in Fig. 3 j.
One layer of field oxygen or Si are deposited in device surface3N4Layer, then gluing photoetching, corrosion and passivation layer opens electrode contact hole,
Finally remove photoresist, clean.
Step k, prepares electrode, as shown in figure 3k.
Grid first are made in front electron beam evaporation Ti/Ni/Au, source electrode, then gluing photoetching, corrosion metal forms grid,
Source electrode, removes photoresist, cleaning.
Overleaf electron beam evaporation Ti/Ni/Au makes drain electrode again, finally short annealing 3min, temperature in an ar atmosphere
It is 1050 DEG C.Because N- drift layers 2 and the doping concentration of P- epitaxial layers 3 are relatively low, in source electrode 10 and and N- drift layers 2 and P- epitaxial layers
3 interfaces form Schottky contacts, and other interfaces form Ohmic contact.
Embodiment three
Fig. 3 is referred to, Fig. 3 is to present embodiments provide another SiC double flutes UMOSFET device preparation methods, the preparation
Method comprises the following steps：
Step a, in the Epitaxial growth N- drift layers 2 of N-type SiC substrate 1, as shown in Figure 3 a.
It it is first 500 μm to thickness, Nitrogen ion doping concentration is 1 × 1020cm-3N-type SiC substrate 1 to carry out RCA standards clear
Wash, be then 20 μm in the Epitaxial growth thickness of whole SiC substrate 1, Nitrogen ion doping concentration is 3 × 1015cm-3N- drift
Layer 2.Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure
Hydrogen, impurity source is liquid nitrogen.
Step b, epitaxial growth P- epitaxial layer 3, as shown in Figure 3 b.
It is 1.5 μm that a layer thickness is grown on N- drift layers 2, and Al ion dopings concentration is 1 × 1017cm-3P- epitaxial layers
3.Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure hydrogen
Gas, impurity source is three base first aluminium.
Step c, epitaxial growth N+ source region layer 4, as shown in Figure 3 c.
It is 0.5 μm that a layer thickness is grown on P- epitaxial layers 3, and Nitrogen ion doping concentration is 5 × 1018cm-3N+ source region layers
4.Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure hydrogen
Gas, impurity source is liquid nitrogen.
Step d, etching forms grid groove, as shown in Figure 3 d.
One layer of magnetron sputtering firstTi films as ICP etch masks, then gluing photoetching carries out ICP etchings,
It is 1.5 μm to etch the width of groove, and depth is 2.5 μm, is finally removed photoresist, and goes etch mask, cleans into mating plate.Its process conditions
For：ICP coil power 850W, source power 100W, reacting gas SF6And O2Respectively 48sccm and 12sccm.
Step e, carries out multiple Al ions autoregistration and injects, such as Fig. 3 e institutes using the etch mask of grid groove in N- drift layers 2
Show.
Successively using 450keV, 300keV, 200keV and 120keV Implantation Energy, by implantation dosage be 7.97 ×
1013cm-2、4.69×1013cm-2、3.27×1013cm-2With 2.97 × 1013cm-2Al ions, be injected into four times N- drift
The injection region of layer 2, it is 0.5 μm to form depth, and concentration is 3 × 1018cm-3P+ gate mediums protection zone 5, implantation temperature is 650
℃。
Step f, etching forms source slot, as illustrated in figure 3f.
One layer of magnetron sputtering firstTi films as ICP etch masks, then gluing photoetching carries out ICP etchings,
It is 1 μm to etch the width of groove, and depth is 3 μm, is finally removed photoresist, and goes etch mask, cleans into mating plate.Its process conditions is：ICP
Coil power 850W, source power 100W, reacting gas SF6And O2Respectively 48sccm and 12sccm.
Step g, carries out multiple Al ions autoregistration and injects, such as Fig. 3 g institutes using the etch mask of source slot in N- drift layers 2
Show.
First successively using 450keV, 300keV, 200keV and 120keV Implantation Energy, by implantation dosage be 7.97 ×
1013cm-2、4.69×1013cm-2、3.27×1013cm-2With 2.97 × 1013cm-2Al ions, be injected into four times N- drift
The injection region of layer 2, it is 0.5 μm to form depth, and concentration is 3 × 1018cm-3P+ source slots turning protection zone 6, implantation temperature is 650
℃。
Surface of SiC is cleaned using RCA cleanings standard again, the protection of C films is made after drying, then 1700~1750
Ion-activated annealing 10min is carried out in DEG C argon atmosphere.
Step h, preparation vessel gate medium 7, material therefor is SiO2, as illustrated in figure 3h.
SiO is prepared at 1150 DEG C using dry oxygen technique2Gate dielectric layer, thickness is 100nm, then at 1050 DEG C, NO atmosphere
Annealed under enclosing, reduced SiO2The roughness of film surface.
Step i, prepares poly Si grid, as shown in figure 3i.
Grid groove is filled up using low pressure hot wall chemical vapor deposition method growth poly Si, deposition temperature is 600~650 DEG C, is formed sediment
It is by force 60~80Pa to overstock, and reacting gas is silane and hydrogen phosphide, and carrier gas is helium, then gluing photoetching, etches poly
Si layers, polysilicon gate is formed, finally removed photoresist, cleaned.
Step j, prepares passivation layer, as shown in Fig. 3 j.
One layer of field oxygen or Si are deposited in device surface3N4Layer, then gluing photoetching, corrosion and passivation layer opens electrode contact hole,
Finally remove photoresist, clean.
Step k, prepares electrode, as shown in figure 3k.
Grid first are made in front electron beam evaporation Ti/Ni/Au, source electrode, then gluing photoetching, corrosion metal forms grid,
Source electrode, removes photoresist, cleaning.
Overleaf electron beam evaporation Ti/Ni/Au makes drain electrode again, finally short annealing 3min, temperature in an ar atmosphere
It is 1050 DEG C.Because N- drift layers 2 and the doping concentration of P- epitaxial layers 3 are relatively low, in source electrode 10 and and N- drift layers 2 and P- epitaxial layers
3 interfaces form Schottky contacts, and other interfaces form Ohmic contact.
Example IV
Fig. 3 is referred to, Fig. 3 is to present embodiments provide another SiC double flutes UMOSFET device preparation methods, the preparation
Method comprises the following steps：
Step a, in the Epitaxial growth N- drift layers 2 of N-type Si substrates 1, as shown in Figure 3 a.
It it is first 300 μm to thickness, Nitrogen ion doping concentration is 1 × 1019cm-3N-type SiC substrate to carry out RCA standards clear
Wash, be then 15 μm in the Epitaxial growth thickness of whole SiC substrate 1, Nitrogen ion doping concentration is 6 × 1015cm-3N- drift
Layer 2.Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure
Hydrogen, impurity source is liquid nitrogen.
Step b, epitaxial growth P- epitaxial layer 3, as shown in Figure 3 b.
It is 1.3 μm that a layer thickness is grown on N- drift layers 2, and Al ion dopings concentration is 1 × 1017cm-3P- epitaxial layers
3.Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure hydrogen
Gas, impurity source is three base first aluminium.
Step c, epitaxial growth N+ source region layer 4, as shown in Figure 3 c.
It is 0.5 μm that a layer thickness is grown on P- epitaxial layers 3, and Nitrogen ion doping concentration is 5 × 1018cm-3N+ source region layers
4。
Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, carrier gas
It is pure hydrogen, impurity source is liquid nitrogen.
Step d, etching forms grid groove, as shown in Figure 3 d.
One layer of magnetron sputtering firstTi films as ICP etch masks, then gluing photoetching carries out ICP etchings,
It is 1.5 μm to etch the width of groove, and depth is 2.5 μm, is finally removed photoresist, and goes etch mask, cleans into mating plate.Its process conditions
For：ICP coil power 850W, source power 100W, reacting gas SF6And O2Respectively 48sccm and 12sccm.
Step e, carries out multiple Al ions autoregistration and injects, such as Fig. 3 e institutes using the etch mask of grid groove in N- drift layers 2
Show.
Successively using 450keV, 300keV, 200keV and 120keV Implantation Energy, by implantation dosage be 7.97 ×
1013cm-2、4.69×1013cm-2、3.27×1013cm-2With 2.97 × 1013cm-2Al ions, be injected into four times N- drift
The injection region of layer 2, it is 0.5 μm to form depth, and concentration is 3 × 1018cm-3P+ gate mediums protection zone 5, implantation temperature is 650
℃。
Step f, etching forms source slot, as illustrated in figure 3f.
One layer of magnetron sputtering firstTi films as ICP etch masks, then gluing photoetching carries out ICP etchings,
It is 1 μm to etch the width of groove, and depth is 3 μm, is finally removed photoresist, and goes etch mask, cleans into mating plate.Its process conditions is：ICP
Coil power 850W, source power 100W, reacting gas SF6And O2Respectively 48sccm and 12sccm.
Step g, carries out multiple Al ions autoregistration and injects, such as Fig. 3 g institutes using the etch mask of source slot in N- drift layers 2
Show.
First successively using 450keV, 300keV, 200keV and 120keV Implantation Energy, by implantation dosage be 7.97 ×
1013cm-2、4.69×1013cm-2、3.27×1013cm-2With 2.97 × 1013cm-2Al ions, be injected into four times N- drift
The injection region of layer 2, it is 0.5 μm to form depth, and concentration is 3 × 1018cm-3P+ source slots turning protection zone 6, implantation temperature is 650
℃。
Surface of SiC is cleaned using RCA cleanings standard again, the protection of C films is made after drying, then 1700~1750
Ion-activated annealing 10min is carried out in DEG C argon atmosphere.
Step h, preparation vessel gate medium 7, material therefor is SiO2, as illustrated in figure 3h.
SiO is prepared at 1150 DEG C using dry oxygen technique2Gate dielectric layer, thickness is 100nm, then at 1050 DEG C, NO atmosphere
Annealed under enclosing, reduced SiO2The roughness of film surface.
Step i, prepares poly Si grid, as shown in figure 3i.
Grid groove is filled up using low pressure hot wall chemical vapor deposition method growth poly Si, deposition temperature is 600~650 DEG C, is formed sediment
It is by force 60~80Pa to overstock, and reacting gas is silane and hydrogen phosphide, and carrier gas is helium, then gluing photoetching, etches poly
Si layers, polysilicon gate is formed, finally removed photoresist, cleaned.
Step j, prepares passivation layer, as shown in Fig. 3 j.
One layer of field oxygen or Si are deposited in device surface3N4Layer, then gluing photoetching, corrosion and passivation layer opens electrode contact hole,
Finally remove photoresist, clean.
Step k, prepares electrode, as shown in figure 3k.
Grid first are made in front electron beam evaporation Ti/Ni/Au, source electrode, then gluing photoetching, corrosion metal forms grid,
Source electrode, removes photoresist, cleaning.
Overleaf electron beam evaporation Ti/Ni/Au makes drain electrode again, finally short annealing 3min, temperature in an ar atmosphere
It is 1050 DEG C.Because N- drift layers 2 and the doping concentration of P- epitaxial layers 3 are relatively low, in source electrode 10 and and N- drift layers 2 and P- epitaxial layers
3 interfaces form Schottky contacts, and other interfaces form Ohmic contact.
In sum, a kind of SiC double flutes that specific case used herein is provided invention embodiment
The implementation method of UMOSFET devices and preparation method thereof is set forth, and the explanation of above example is only intended to help and understands
The method of the present invention and its core concept；Simultaneously for those of ordinary skill in the art, according to thought of the invention, in tool
Be will change in body implementation method and range of application, in sum, this specification content should not be construed as to the present invention
Limitation, protection scope of the present invention should be defined by appended claim.
Claims (10)
1. a kind of preparation method of SiC double flutes UMOSFET devices, it is characterised in that including：
Step 1, selection SiC substrate；
Step 2, grow drift layer, epitaxial layer and source region layer in the SiC substrate continuous surface；
Step 3, the source region layer, the epitaxial layer and the drift layer are performed etching to form grid groove；
Step 4, ion implanting is carried out to the grid groove form gate medium protection zone；
Step 5, the source region layer, the epitaxial layer and the drift layer are performed etching and to form source slot；
Step 6, the source slot is carried out ion implanting formed source slot turning protection zone；
Step 7, in the grid groove gate dielectric layer and grid layer are grown to form grid；
Step 8, Passivation Treatment simultaneously prepare electrode to form the SiC double flutes UMOSFET devices.
2. method according to claim 1, it is characterised in that step 2 includes：
Step 21, using epitaxial growth technology, in drift layer described in the SiC substrate superficial growth；
Step 22, using epitaxial growth technology, in epitaxial layer described in the drift layer superficial growth；
Step 23, using epitaxial growth technology, in source region layer described in the epi-layer surface epitaxial growth.
3. method according to claim 1, it is characterised in that step 3 includes：
Using ICP etching technics, using the first mask plate, the source region layer surface is performed etching, in the source region layer, described
The grid groove is formed in epitaxial layer and the drift layer.
4. method according to claim 1, it is characterised in that step 4 includes：
Using autoregistration injection technology, using the first mask plate, Al ion implantings are carried out to the grid groove in the drift layer
Form the gate medium protection zone.
5. method according to claim 1, it is characterised in that step 5 includes：
Using ICP etching technics, using the second mask plate, the source region layer surface is performed etching, in the source region layer, described
The source slot is formed in epitaxial layer and the drift layer.
6. method according to claim 1, it is characterised in that step 6 includes：
Using autoregistration injection technology, using the second mask plate, Al ion implantings are carried out to the source slot in the drift layer
Form source slot turning protection zone.
7. method according to claim 6, it is characterised in that Al ion implantings are carried out to the source slot, including：
Using the Implantation Energy of 450keV, 7.97 × 1013cm-2Implantation dosage, the source slot is carried out first time Al ion note
Enter；
Using the Implantation Energy of 300keV, 4.69 × 1013cm-2Implantation dosage, second Al ion note is carried out to the source slot
Enter；
Using the Implantation Energy of 200keV, 3.27 × 1013cm-2Implantation dosage, the source slot is carried out third time Al ions note
Enter；
Using the Implantation Energy of 120keV, 2.97 × 1013cm-2Implantation dosage, the 4th Al ion note is carried out to the source slot
Enter.
8. method according to claim 1, it is characterised in that step 7 includes：
Using dry oxygen technique, SiO is grown in the grid groove2Material is forming the gate dielectric layer；
Using HWLPCVD techniques, polycrystalline Si material is grown in the grid groove to form the grid layer.
9. method according to claim 1, it is characterised in that step 8 includes：
In the substrate top surface growth of passivation layer including the grid；
Using etching technics, the passivation layer to the gate surface performs etching to form electrode contact hole；
Using electron beam evaporation process, metal material formation source electrode and grid are grown in the source slot and the electrode contact hole
Electrode；
Using electron beam evaporation process, drain electrode is formed in substrate lower surface growth metal material double to ultimately form the SiC
Groove UMOSFET devices.
10. a kind of SiC double flutes UMOSFET devices, it is characterised in that the SiC double flutes UMOSFET devices are by claim 1~9
Method described in any one prepares to be formed.
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