CN114927559A - Novel silicon carbide-based super-junction trench MOSFET and preparation method thereof - Google Patents

Novel silicon carbide-based super-junction trench MOSFET and preparation method thereof Download PDF

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CN114927559A
CN114927559A CN202210555055.3A CN202210555055A CN114927559A CN 114927559 A CN114927559 A CN 114927559A CN 202210555055 A CN202210555055 A CN 202210555055A CN 114927559 A CN114927559 A CN 114927559A
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CN114927559B (en
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张峰
王小杰
张国良
付钊
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Xiamen University
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Abstract

A novel silicon carbide-based super-junction trench MOSFET and a preparation method thereof relate to a semiconductor SiC material. The MOSFETs add 3 p + column regions and 2 n + column regions under the trench p-type shielding layer and the p body region, thereby forming a semi-super junction structure. When the device is conducted in the forward direction, current flows from top to bottom along the n column region, and the concentration of current carriers in a current path is increased due to the n column region, so that the device has better forward conduction characteristics; when reverse blocking is carried out, the super junction structure can achieve basic charge balance to form an intrinsic semiconductor with higher withstand voltage, and in addition, in a local area, a triangular electric field is converted into a trapezoidal electric field. The breakdown voltage is higher than that of the conventional structure under the same avalanche electric field. This structure thus mitigates the effect of electric field crowding at the corners of the p-type shield layer, while increasing on-state current and reducing on-state resistance.

Description

Novel silicon carbide-based super-junction trench MOSFET and preparation method thereof
Technical Field
The invention relates to a semiconductor SiC material, in particular to a novel silicon carbide-based super-junction trench MOSFET and a preparation method thereof.
Background
Compared with the traditional Si material, the SiC material has excellent performance, particularly in the aspects of electrical and physical characteristics, such as high breakdown electric field, good thermal stability, high saturated electron drift velocity and the like, can realize low on-resistance compared with the traditional Si device, and is suitable for the field of high-temperature and high-voltage power electronics. And is therefore popular in power supplies, automobiles, industrial equipment, and consumer electronics for home use. The vertical MOSFET structure includes a vertical dual-injection planar gate type structure (DMOSFET) and a trench gate type structure (UMOSFET), and the trench type structure can theoretically have a lower on-resistance and a higher channel current density than the vertical dual-injection structure due to advantages of high mobility of a non-polar surface, effective reduction of a cell size, and the like, and thus is widely applied to MOS devices. Although the trench structure has many advantages, there are many potential problems, such as easy damage of the trench surface sidewall, reliability of the gate oxide layer, unstable threshold voltage, etc. One of the key issues is to reduce the electric field crowding effect (Eox-max) in the gate oxide at the bottom corners of the trench, improving the gate oxide reliability. However, lowering the gate oxide electric field comes at the cost of increasing the device on-resistance.
The super junction structure is a significant development of high voltage MOSFET technology and has significant advantages in that on-resistance, gate charge and gate capacitance values, and die size can be reduced simultaneously. In addition, the MOSFET is applied to some power electronic fields, such as motor driving, inversion, DC-DC conversion, etc., which take into account the corresponding loss, switching loss, conduction loss, etc. of the device in power electronic applications. The smaller grid charge and capacitance enables the device to have faster turn-on speed and turn-off speed in the switch application, and can effectively reduce the loss of the device in the switch application.
Disclosure of Invention
The invention aims to provide a novel silicon carbide-based super-junction trench MOSFET. When the semiconductor device is conducted in the forward direction, the carrier concentration is increased due to the n + column region below the channel, and the semiconductor device has better forward conduction characteristics; when reverse blocking is carried out, the super-junction structure can effectively relieve an electric field at the corner of the p-type shielding layer, and in addition, the prepared SiC-based super-junction trench MOSFET has higher blocking capability due to the intrinsic semiconductor structure formed by mutual depletion of the super-junction structure.
The invention also aims to provide a preparation method of the novel silicon carbide-based super-junction trench MOSFET.
A novel silicon carbide-based super junction trench MOSFET comprises:
a SiC n + + type substrate, at least one epitaxial layer grown on the SiC n + + type substrate, the epitaxial layer comprising: an n-drift layer and an n + column region; the n + column region is grown on the n-drift layer;
etching the n + column region and then performing multi-epitaxial growth to obtain a p + column region;
the active region is injected and epitaxially grows above the n + column region and the p + column region and comprises a p-type channel layer, a p + + type source region layer, an n + + type source region conducting layer, a groove, a p-type shielding layer, a source electrode, a drain electrode and a metal bonding pad; the upper surface of the p-type shielding layer is arranged close to the lower surface of the groove; the surface of the p + + type source region conducting layer is simultaneously clung to the p type channel layer, the left side surface of the n + + type source region conducting layer and the upper surface of the p + column region; the lower surface of the n + + type source region conducting layer is tightly attached to the upper surface of the p type channel layer, and the lower surface of the n + + type source region conducting layer is tightly attached to the upper surface of the p type channel layer;
the source electrode is arranged on the surfaces of the n + + type source region conducting layer and the p + + type source region layer, and the drain electrode is arranged on the back surface of the SiC n + + type substrate; the contact material of the source electrode and the drain electrode can adopt AlTi, Ni, TiW or AlTi and is used for forming ohmic contact with an external component;
the metal pad completely covers the groove, the groove adjacent mesa and the internal insulating material, and is isolated from the gate electrode by the internal insulating material.
The lower surfaces of the n + column region and the p + column region are tightly attached to the upper surface of the n-drift layer; the upper surface of the n + column region is tightly attached to the corner of the p-type shielding layer, the gate oxide layer on the surface of the side wall and the lower surface of the p-type channel layer, and the n + column region is arranged between the two p + column regions; the upper surfaces of the p + column regions at the two sides are tightly attached to the lower surface of the p-type channel layer, and the upper surface of the p + column region in the middle is tightly attached to the lower surface of the p-type shielding layer. The upper surface of the p-type shielding layer is tightly attached to the lower surface of the groove, and the lower surface of the p-type shielding layer is tightly attached to the upper surfaces of the n + column area and the p + column area.
The distance between the upper surface of the n + column region and the upper surface of the n-drift layer can be 1.5-3.5 μm, the right side of the n + column region can extend to the lower part of the trench by 0.5-1.5 μm, and the doping concentration can be 1e 16-6 e16cm -3 (ii) a The distance between the upper surfaces of the two side p + column regions and the upper surface of the n-drift layer is the same as that of the corresponding n + column region, and the doping concentration can be 2e 16-2 e17cm -3 (ii) a The distance between the upper surface of the p-type shielding layer and the upper surfaces of the n + column region and the p + column region below the groove can be 0.1-1 mu m.
The invention is also provided with a gate electrode, the gate electrode is tightly attached to the surface of the gate oxide layer, the lower part of the gate electrode is tightly attached to the upper surface of the gate oxide layer, the top end of the gate electrode is higher than the upper surface of the P-type channel layer, the gate electrode is made of highly doped polysilicon, and when the top end of the gate electrode is flush with the upper surface of the conducting layer of the n + + type source region, the gate electrode is arranged between the gate oxide layers on the two side walls in the groove.
A preparation method of a novel silicon carbide-based super junction trench MOSFET comprises the following steps:
step 1: epitaxially growing an n-drift layer on a SiC n + + type substrate;
step 2: depositing a layer of p + column region above the n-drift layer;
and step 3: etching the p + column region, and growing an n + column region on the n-drift layer in an epitaxial mode;
and 4, step 4: forming a p-type channel layer, a p + + type source region layer and an n + + type source region layer in sequence by injection or epitaxy;
and 5: forming a groove in the active area by using plasma etching, and forming a p-type shielding layer by ion implantation;
and 6: manufacturing a gate oxide layer and filling the groove with polycrystalline silicon;
and 7: manufacturing a source electrode and a drain electrode;
and 8: and manufacturing a passivation layer and a source region metal pad and insulating the passivation layer and the source region metal pad from the gate electrode.
In step 3, the etching adopts HF etching.
In step 7, the source electrode 12 and the drain electrode 13 are in ohmic contact.
Compared with the prior art, the super junction structure is introduced below the MOSFET channel and the p-type shielding layer, and has the following advantages:
1. the device structure based on the silicon carbide-based super-junction trench MOSFET and the preparation method have high cellular integration level, increase the electron concentration of a current carrier when the device is conducted in an n + column region below a channel, improve the mobility of the current carrier, reduce the conduction resistance of the device and enable the on-state characteristic of the device to be good;
2. in the reverse blocking state, the free charges in the p + column and n + column regions in the super junction structure are completely depleted, making it behave as an intrinsic semiconductor, and thus have a considerable lateral electric field, which can be broken down only when an applied voltage is greater than this lateral electric field. The high voltage reliability of the device is improved.
3. Compared with the traditional silicon carbide-based groove UMOSFET device, the silicon carbide-based super-junction groove type MOSFET has lower gate charge and faster switching speed, and reduces the dynamic switching loss of the device.
Drawings
Fig. 1 is a schematic structural diagram of a silicon carbide-based superjunction trench MOSFET provided by the present invention.
Fig. 2 is a flowchart of a method for manufacturing a silicon carbide-based superjunction trench MOSFET provided by the present invention.
Fig. 3 is a schematic structural diagram of the SiC epitaxial layer produced in step S1 in the production method.
Fig. 4 is a schematic structural diagram of the step S2 of manufacturing an n + pillar region and a p + pillar region in the epitaxial layer in the manufacturing method.
Fig. 5 is a schematic diagram of the step S3 of manufacturing the active region in the manufacturing method.
Fig. 6 is a schematic diagram of the step S4 of manufacturing a trench structure in the active region in the manufacturing method.
Fig. 7 is a schematic diagram of the step S5 of ion implantation at the bottom of the trench to form a p-type shielding layer structure in the preparation method.
Fig. 8 is a schematic diagram of the step S7 of manufacturing the gate oxide structure.
Fig. 9 is a schematic diagram of the gate electrode contact structure manufactured in step S8.
Fig. 10 shows the step S9 of the manufacturing method for making the source electrode metal contact.
Fig. 11 shows that step S10 of the preparation method makes a drain electrode metal contact.
Fig. 12 is a schematic diagram of step S12 for fabricating a passivation layer and a source region metal pad.
FIG. 13 is a schematic diagram comparing the electrical characteristics of two structures. Wherein (a) is the current density comparison (V) of the two structures in forward conduction GS 15V and V DS 20V); (b) the breakdown characteristics of both structures.
Each of the labels in the figure is: 10. a SiC n + + type substrate; 20. an n-drift layer; 30. an n + column region; 40. a p + column region; 50. a p-type channel layer; 60. an n + + type source region conducting layer, 61, a p + + type source region conducting layer; 900. a p-type shield layer; 9. a gate oxide layer; 72. a gate electrode; 12. a source electrode; 13. a drain electrode; 70. a trench; 81. and a metal pad.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the accompanying drawings in combination with the embodiments.
In one embodiment of the invention, a novel silicon carbide-based super junction trench MOSFET structure is provided. As shown in fig. 1, the structure includes: a SiC n + + type substrate 10, an n-drift layer 20, an n + column region 30, a p + column region 40, and an active region; specifically, the method comprises the following steps:
a SiC n + + type substrate 10;
an n-drift layer 20 grown over the SiC n + + type substrate 10;
an n + column region 30 grown over the n-drift layer;
a p + column region 40, an n + column region is etched, and epitaxial growth is carried out;
the active region is grown on the n + pillar region 30 and the p + pillar region 40, and includes a p-type channel layer 50, a p + + type source region layer 61, an n + + type source region conductive layer 60, a trench 70, a p-type shielding layer 900, a source electrode 12, and a drain electrode 13. The upper surface of the p-type shielding layer 900 is closely attached to the lower surface of the trench 70; the surface of the p + + type source region conducting layer 61 is tightly attached to the left side surfaces of the p type channel layer 50 and the n + + type source region conducting layer 60 and the upper surface of the p + column region 40; the lower surface of the n + + type base region conducting layer 60 is closely attached to the upper surface of the p type channel layer 50, and the upper surface of the n + + type base region conducting layer 60 is closely attached to the surface of the p type channel layer 50;
the main groove includes: a trench 70; and a gate oxide layer 9, a polysilicon gate electrode 72 and a drain electrode 13 which are formed on the upper surface of the p-type shielding layer and the surfaces of the two side walls in the trench 70, are arranged in the gate oxide layer 9, are arranged on the lower surface of the SiC n + + type substrate 10, and are provided with a source electrode 12 on the upper surfaces of the p + + type source region layer 61 and the n + + type source region conducting layer 60, wherein the two contact materials are AlTi, Ni, TiW or AlTi and are used for forming ohmic contact with an external component.
Fig. 2 shows a manufacturing process according to an embodiment of the invention, comprising the following steps:
s1, epitaxially growing epitaxial layers with different doping on the substrate;
s2, etching the second epitaxial layer to form an n + column region, and performing multi-epitaxial growth to form a p + column region;
s3, epitaxially growing an epitaxial layer p body layer, and forming an n + + source region and a p + + source region through Al and B ion implantation;
s4, manufacturing a groove;
s5, etching the groove to the bottom of the p base region, and injecting ions to form a p + shielding layer;
s6, annealing after ion implantation;
s7, manufacturing a gate oxide layer;
s8, filling doped polysilicon in the groove, and flattening to form a gate electrode;
s9, photoetching and manufacturing a source metal contact;
s10, photoetching and manufacturing a drain metal contact;
s11, quickly annealing to make ohmic contact;
and S12, passivating and connecting metals.
In step S1, the epitaxially grown material forms a differently doped epitaxial layer, n-drift region 20 and n + column regions 30. According to an embodiment of the invention, a chemical vapor deposition or other method of epitaxially growing material is used to epitaxially grow a substrate of SiC n + + type on a substrate as shown in FIG. 3Growing a plurality of SiC epitaxial layers with different doping types to form a sandwich structure, wherein the sandwich structure sequentially comprises an n-drift region and an n + column region from bottom to top. The thickness of the n + + type substrate is 350-1000 μm or a series of processes such as thinning, grinding, polishing, cleaning and the like are carried out on the n + + type substrate by a mechanical processing and chemical reaction method, so that the surface of the sample reaches the required thickness and flatness. Epitaxially forming an n-drift layer 20 on the SiC n + + type substrate 10, wherein the source of epitaxial growth is silane or trichlorosilane, ethylene or propane, etc., the thickness of the n-drift layer 20 is 13 μm, and the doping of the n-drift layer 20 is 1.0 × 10 15 cm -3 ～5.0×10 15 cm -3 The doping source is ammonia gas and other gas sources, wherein the epitaxial growth temperature is 1500-1700 ℃. An n + column region 30 is epitaxially formed on the n-type drift layer 20, the source of epitaxial growth is silane or trichlorosilane, ethylene or propane and the like, the doping source is ammonia and other gas sources, the epitaxial growth temperature is 1500-1800 ℃, the thickness and doping of the n + column region 30 need to be designed according to certain design to meet different blocking voltages, and the doping of the n + column region 30 in the embodiment is 1 × 10 16 cm -3 ～5×10 16 cm -3 The n + column region 30 has a thickness of 2 to 5 μm and a width of 0.1 to 3 μm.
In step S2, the n + pillar region 30 is etched to form a p + pillar region 40, and the etching depth is 2 to 4 μm by using HF or the like. Forming a p + column region 40 on the n-drift layer 20 by epitaxial growth, wherein the doping source is a gas source such as trimethylaluminum, the epitaxial growth temperature is 1500-1700 ℃, the doping concentration of the p + column region 40 is determined according to the doping of the n + column region 30, and the doping concentration of the p + column region 40 in the embodiment is 2.0 × 10 16 cm -3 ～5×10 16 cm -3 The width of the p + pillar region 40 is determined by the doping of the n + pillar region 30 and the p + pillar region 40, and the p + pillar region 40 has a width of 1 to 4 μm and a thickness corresponding to the corresponding n pillar region as shown in fig. 4.
In step S3, according to an embodiment of the present invention, as shown in fig. 5, a p-type channel layer 50 is epitaxially formed on the n + pillar region 30 and the p + pillar region, the doping source for epitaxial growth is a source gas such as trimethylaluminum, and the thickness of the p-type channel layer 50 is 0.1-0.5 μm as an embodimentIs doped to 0.5 x 10 17 cm -3 To 4.5X 10 17 cm -3 Wherein the epitaxial growth temperature is 1500-1700 ℃. An n + + source region layer 60 is epitaxially grown on the p-type channel layer 50, the source of the epitaxial growth is silane, trichlorosilane, ethylene, propane, or the like, the doping source is ammonia gas or other gas source, the thickness of the n + + source region layer 60 is 0.1 to 0.4 μm in the embodiment, and the doping of the n + + source region layer 60 is 1.0 × 10 19 cm -3 ～5.0×10 19 cm -3 Wherein the epitaxial growth temperature is 1500-1700 ℃. Making a p + + source region layer, forming an implantation mask layer by photoetching pattern transfer, respectively implanting with an implantation energy of 28keV and an implantation dose of 2.36 × 10 13 cm -2 And a sum implantation energy of 60keV and an implantation dose of 4.6X 10 12 cm -2 And an implantation energy of 100keV and an implantation dose of 6.3 × 10 14 cm -2 Three times of Al atom implantation to form a doping of about 1.0X 10 19 cm -3 The depth of the p + + source region layer 61 is 0.2 to 0.5 μm, and the implanted atoms may be B atoms.
In step S4, a trench is formed. According to the embodiment of the present invention, the trench 70 is sequentially formed by using processes such as thin film deposition, photolithography, dry and wet etching, ion implantation, etc., wherein the sidewalls of the trench 70 need to be {11-20} plane system, two trench corners of the trench 70 have a rounded structure, the bottom of the trench is planarized, and the p-type shielding layer 900 is formed at the bottom of the trench 70.
In step S5, trench 70 etch terminates at the bottom of p-type base layer 50 and ion implantation forms p-type shield layer 900. According to the embodiment of the invention, as shown in FIG. 6, a barrier layer is formed by depositing silicon dioxide or polysilicon or metal medium with a certain thickness by physical and chemical vapor deposition or other thin film deposition methods, photoetching and patterning are carried out, the barrier layer is etched by a dry method to form an etching mask layer, the etching mask layer can be 2-5 μm as silicon dioxide, the silicon dioxide mask layer is required to be above 1000 ℃, and O is higher than O 2 The etching mask layer can be Al, Ni and the like as metal, and the thickness is about 1 mu m. The dry etching gas may be C 4 F 8 ，CHF 3 ，Cl 2 And the like. Etching the SiC substrate to form a trench 70 by using the etching mask layer by physical and chemical etching means such as Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP), wherein the etching gas may be SF 6 /O 2 、NF 3 /Ar、CF 4 、CHF 3 /O 2 、C 4 F 8 /O 2 Etc., by way of illustration, using SF 6 /O 2 The ICP power is 600-1000W, the bias power is 100-300W, the temperature is 20 ℃, and the trench 70 needs to penetrate through the bottom of the p-type channel layer 50 and enter the n + column region 30 and the p + column region 40. As shown in fig. 7, removing the etching mask layer, depositing a certain thickness of silicon dioxide or polysilicon or metal medium by physical and chemical vapor deposition or other thin film deposition methods to form a barrier layer, performing photolithography patterning, dry etching the barrier layer to form implantation, performing ion implantation to form a p-type shielding layer, wherein the implantation impurity can be B or Al, and the implantation dosage can be 1.0 × 10 18 cm -2 To 1.0X 10 20 cm -2 The implantation energy may be 20keV to 700 keV. The finally formed p-type shield layer 900, as an example, gives a doping concentration of 1.0 × 10 of the p-type shield layer 900 18 cm -3 ～1.0×10 20 cm -3 。
In step S6, post-ion implantation annealing. According to the embodiment of the invention, the implantation mask is removed, the surface is cleaned, carbon film and AlN film are used for covering, the method such as silane inhibition and the like is adopted for annealing for about 0.5h at 1600 ℃ and under the pressure of 600-700 Torr, the ion implantation doping in the steps is activated, the carbon film, AlN film and the like covered on the surface after the annealing is finished are removed, and the surface is cleaned.
In step S7, a gate oxide layer is fabricated. According to the embodiment of the invention, as shown in fig. 8, a gate oxide layer 9 is finally obtained by standard cleaning (RCA) of the SiC substrate by physical or chemical vapor deposition, high temperature thermal oxidation and post oxidation annealing, Atomic Layer Deposition (ALD), and the like. Ultrasonic cleaning with acetone and ethanol in sequence, and washing with deionized water; boiling the SiC substrate subjected to organic ultrasound in concentrated sulfuric acid and hydrogen peroxide solution for at least 10 min; will be cookedThe method comprises the following steps of sequentially boiling a SiC substrate of concentrated sulfuric acid in a first liquid and a second liquid for more than 10min, washing the SiC substrate with deionized water, and then blowing the SiC substrate with nitrogen for later use, wherein the first liquid is a mixed liquid of ammonia water, hydrogen peroxide and deionized water, and the second liquid is a mixed liquid of hydrochloric acid, hydrogen peroxide and deionized water, and the washed SiC substrate is placed in hydrofluoric acid to be soaked for at least 1min to remove a surface oxide layer. The SiC substrate after standard cleaning (RCA) is oxidized for about 0.5h in a wet oxygen environment at about 1100 ℃ to form a sacrificial oxide layer, and the sacrificial oxide layer is removed by diluted HF ultrasonic rinsing. Dry oxygen oxidation is carried out for about 0.5h at 1100-1400 ℃, and annealing is carried out for 1-3 h at 1200-1400 ℃ under the condition of NO atmosphere, wherein the annealing atmosphere is not only NO, but also POCl 3 ，H 2 ，N 2 O，P 2 O 5 ，Sb + NO, etc., and the gate oxide layer 9 finally obtained may be formed by a method such as Atomic Layer Deposition (ALD) as a method of forming the selective gate oxide layer 9.
In step S8, the trench is filled with doped polysilicon and planarized to form a gate electrode. According to an embodiment of the present invention, as shown in fig. 9, the trench 70 where the gate oxide layer 9 has been formed is filled by an isotropic deposition technique, the filler may be doped polysilicon or silicide with high conductivity, a gate electrode 72 is formed, the deposited gate electrode 72 is etched back by dry etching, wet etching, and the like, and deposited and etched back again until the gate electrode 72 in the trench 70 is planarized and only remains.
In step S9, a source metal contact is made by photolithography. According to the embodiment of the present invention, as shown in fig. 10, patterning is performed by photolithography, oxide layers on the p + + source region layer 61 and the n + + source region layer 60 are removed by diluted HF, multiple layers of metals of 60 to 100nm Ni, 20 to 40nm Ti, and 60 to 100nm Al are sequentially deposited by using a thin film deposition method such as electron beam evaporation or sputtering, and the source electrode 12 is formed by lift-off, the source electrode 12 needs to cover the surfaces of the base p + + source region layer 61 and the n + + source region layer 60 at the same time, and the source electrode 12 may be a combination of other metals such as AlTi, Ni, TiW, and the like.
In step S10, a drain metal contact is made. According to the embodiment of the invention, as shown in fig. 11, the front surface source electrode 12 is protected by gluing, the oxide layer on the back surface of the n + + type substrate 1 is removed by diluted HF, a 10-30 nm thick AlTi layer and a 300-500 nm Ni metal layer are deposited on the back surface by using a film deposition method such as electron beam evaporation or sputtering, and the drain electrode 13 can be made of other metal combinations such as AlTi, Ni, TiW, AlTi and the like.
In step S11, rapid thermal annealing produces ohmic contacts. According to the embodiment of the invention, as shown in fig. 10 and 11, the source electrode 12 and the drain electrode 13 are annealed at 800-1200 ℃ for 1-3 min under the environment of N2, and the annealing atmosphere may be Ar or H 2+ N 2 。
In step S12, a passivation layer and a source region metal pad 81 are fabricated. According to the embodiment of the invention, as shown in FIG. 12, SiO with a thickness of about 1 μm is deposited on the gate electrode 72 and the source electrode 12 by other deposition methods such as physical vapor deposition or chemical vapor deposition 2 /Si 3 N 4 The passivation dielectric layer is subjected to photoetching patterning, and an etching gas is selected to etch the passivation dielectric layer by a dry method to form a passivation layer 14; and depositing a thick metal layer with the thickness of 1-3 mu m on the passivation layer by using a film deposition method such as electron beam evaporation or sputtering, photoetching and patterning, and interconnecting to form a metal pad area to finish the preparation of the device.
Fig. 13 shows a schematic diagram comparing the electrical characteristics of the two structures. Wherein (a) is the current density comparison (V) of the two structures in forward conduction GS 15V and V DS 20V); (b) the breakdown characteristics of both structures. As can be seen from fig. 3, the present invention is improved over the on-resistance breakdown voltage.
The invention provides a novel silicon carbide-based super-junction trench MOSFET and a preparation method thereof. The MOSFETs add 3 p + pillar regions 40 and 2 n + pillar regions 30 under the trench p-type shield layer 900 and p-channel layer 50 to form a semi-superjunction structure. When the device is conducted in the forward direction, current flows from top to bottom along the n column region 30, and the concentration of carriers in a current path is increased due to the n column region, so that the device has better forward conduction characteristics; when reverse blocking is carried out, the super junction structure can achieve basic charge balance to form an intrinsic semiconductor with higher withstand voltage, and in addition, in a local area, a triangular electric field is converted into a trapezoidal electric field. The breakdown voltage is higher compared with the traditional structure under the same avalanche electric field. This structure thus mitigates the effect of electric field crowding at the corners of the p-type shield layer, while increasing on-state current and reducing on-state resistance.
The above embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above embodiments are only examples of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A novel silicon carbide-based super-junction trench MOSFET is characterized by comprising:
a SiC n + + type substrate, at least one epitaxial layer grown on the SiC n + + type substrate, the epitaxial layer comprising: an n-drift layer and an n + column region; the n + column region is grown on the n-drift layer;
etching the n + column region and then carrying out multi-epitaxial growth to obtain the p + column region;
the active region is injected and epitaxially grows above the n + column region and the p + column region and comprises a p-type channel layer, a p + + type source region layer, an n + + type source region conducting layer, a groove, a p-type shielding layer, a source electrode, a drain electrode and a metal bonding pad; the upper surface of the p-type shielding layer is arranged close to the lower surface of the groove; the surface of the p + + type source region conducting layer is simultaneously clung to the p type channel layer, the left side surface of the n + + type source region conducting layer and the upper surface of the p + column region; the lower surface of the n + + type source region conducting layer is tightly attached to the upper surface of the p type channel layer, and the lower surface of the n + + type source region conducting layer is tightly attached to the upper surface of the p type channel layer.
2. The novel silicon carbide-based superjunction trench MOSFET of claim 1, wherein the source electrode is disposed on the surface of the n + + type source region conductive layer and the p + + type source region layer, and the drain electrode is disposed on the back surface of the SiC n + + type substrate.
3. The novel silicon carbide-based super-junction trench MOSFET as claimed in claim 1, wherein the contact material of the source electrode and the drain electrode is AlTi, Ni, TiW or AlTi for forming ohmic contact with external components.
4. A novel silicon carbide based superjunction trench MOSFET as claimed in claim 1 wherein said metal pad completely covers the trench, the trench adjacent mesa and the internal insulating material and is isolated from the gate electrode contact by the internal insulating material.
5. The novel silicon carbide-based superjunction trench MOSFET of claim 1 wherein the lower surfaces of the n + column region and the p + column region abut the upper surface of the n-drift layer; the upper surface of the n + column region is tightly attached to the corner of the p-type shielding layer, the gate oxide layer on the surface of the side wall and the lower surface of the p-type channel layer, and the n + column region is arranged between the two p + column regions; the upper surfaces of the p + column regions at two sides are tightly attached to the lower surface of the p-type channel layer, and the upper surface of the p + column region in the middle is tightly attached to the lower surface of the p-type shielding layer; the upper surface of the p-type shielding layer is tightly attached to the lower surface of the groove, and the lower surface of the p-type shielding layer is tightly attached to the upper surfaces of the n + column area and the p + column area.
6. The novel silicon carbide-based super-junction trench MOSFET as claimed in claim 1, wherein the distance between the upper surface of the n + column region and the upper surface of the n-drift layer is 1.5-3.5 μm, the right side of the n + column region extends 0.5-1.5 μm below the trench, and the doping concentration is 1e 16-6 e16cm -3 (ii) a The distance between the upper surfaces of the p + column regions at two sides and the upper surface of the n-drift layer is the same as that of the corresponding n + column region, and the doping concentration can be 2e 16-2 e17cm -3 (ii) a The distance between the upper surface of the p-type shielding layer and the upper surfaces of the n + column region and the p + column region below the groove can be 0.1-1 mu m.
7. A novel silicon carbide based super junction trench MOSFET as claimed in claim 1 further comprising a gate electrode closely attached to the surface of the gate oxide layer, wherein the lower portion of the gate electrode closely attached to the upper surface of the gate oxide layer, the top end of the gate electrode is higher than the upper surface of the P-type channel layer, the gate electrode is made of highly doped polysilicon, and when the top end of the gate electrode is flush with the upper surface of the conductive layer of the n + + type source region, the gate electrode is disposed between the gate oxide layers at the two sidewalls in the trench.
8. The method for preparing a novel silicon carbide-based super junction trench MOSFET as claimed in claim 1, comprising the steps of:
step 1: epitaxially growing an n-drift layer on a SiC n + + type substrate;
step 2: depositing a layer of p + column region above the n-drift layer;
and step 3: etching the p + column region, and growing an n + column region on the n-drift layer in an epitaxial manner;
and 4, step 4: forming a p-type channel layer, a p + + type source region layer and an n + + type source region layer in sequence by injection or epitaxy;
and 5: forming a groove in the active area by using plasma etching, and forming a p-type shielding layer by ion implantation;
step 6: manufacturing a gate oxide layer and filling the groove with polycrystalline silicon;
and 7: manufacturing a source electrode and a drain electrode;
and 8: and manufacturing a passivation layer and a source region metal pad and insulating the passivation layer and the source region metal pad from the gate electrode.
9. The method for manufacturing a novel silicon carbide-based super junction trench MOSFET as claimed in claim 8, wherein in step 3, the etching is HF etching.
10. The method for manufacturing a novel silicon carbide-based super junction trench MOSFET as claimed in claim 8 wherein in step 7, the source electrode and the drain electrode are in ohmic contact.
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