CN209963064U

CN209963064U - SiC-based DMOSFET device

Info

Publication number: CN209963064U
Application number: CN201920122905.4U
Authority: CN
Inventors: 张瑜洁; 李昀佶; 陈彤
Original assignee: Global Power Technology Co Ltd
Current assignee: Global Power Technology Co Ltd
Priority date: 2019-01-24
Filing date: 2019-01-24
Publication date: 2020-01-17
Anticipated expiration: 2029-01-24

Abstract

The utility model relates to a semiconductor field provides a SiC base DMOSFET device, including the SiC epitaxial material substrate, active doping area, JFET slot oxide, the gate electrode contact, source electrode contact and drain electrode contact, the SiC epitaxial material substrate includes n + + type substrate, n + type buffer layer and n-type drift layer, active doping area includes p well district, n + + type source region and p + + type base region, first slot has been seted up in JFET doping area, JFET slot oxide covers in first slot, JFET doping area and p well district, the gate electrode contact is located the upper surface of JFET slot oxide, insulating substance layer is located the upper surface of gate electrode contact and fills the space, source electrode contact is located the upper surface on insulating substance layer, the drain electrode contact is located the lower surface of n + + type substrate. The utility model has the advantages of be used for reducing the JFET resistance and the Miller charge of SiC base DMOSFET device to improve the high frequency optimal value of this SiC base DMOSFET device.

Description

SiC-based DMOSFET device

Technical Field

The utility model relates to a semiconductor field specifically relates to a SiC base DMOSFET device.

Background

The physical and electrical properties of silicon carbide (SiC) materials have significant advantages over conventional Si materials. The SiC has the characteristics of wide forbidden band, high thermal conductivity, high breakdown field strength, high saturated electron drift rate and the like, and simultaneously has excellent physical and chemical stability, extremely strong irradiation resistance, mechanical strength and the like. Therefore, the electronic device based on the wide bandgap SiC material can be used in the power electronic fields of high temperature, high power, high frequency, high radiation and the like, and can fully play the important advantages and outstanding characteristics of the SiC-based device in the aspects of energy conservation and emission reduction.

SiC metal-oxide-semiconductor field effect transistor (MOSFET) power devices have matured over the course of commercialization, especially MOSFETs with planar gate structures, i.e., DMOSFETs, are the mainstream. Nevertheless, SiC-based DMOSFET devices have met with greater challenges in terms of reliability of the gate dielectric layer, among others, due to the fact that the SiO2 layer formed by thermally oxidizing the SiC substrate has more interface states with the SiC substrate, and these interface states trap or emit electrons at high temperature and high field, which is not favorable for the electrical stability of the device.

On one hand, in order to improve the reliability of a gate oxide layer of the SiC-based DMOSFET device, a designer can adopt a method of reducing the distance between adjacent p wells to improve the shielding effect of the device, but the JFET resistance is increased, and the reduction of the on-resistance of the device is not facilitated. On the other hand, when the SiC-based DMOSFET device is used in the high frequency domain, the miller charge determines the switching loss, and therefore how to reduce the miller charge of the device is to be solved.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model lies in providing a SiC base DMOSFET device for reduce JFET resistance and the miller electric charge of SiC base DMOSFET device, thereby improve the high frequency optimal value of this SiC base DMOSFET device.

The utility model discloses a realize like this:

a SiC-based DMOSFET device comprises a SiC epitaxial material substrate, an active doped region, a JFET doped region, JFET trench oxide, a gate electrode contact, a source electrode contact and a drain electrode contact, wherein the SiC epitaxial material substrate comprises an n + + type substrate, an n + type buffer layer and an n + type drift layer, the n + type buffer layer is positioned on the upper surface of the n + + type substrate, the n-type drift layer is positioned on the upper surface of the n + + type buffer layer, the active doped region comprises a p well region, an n + + type source region and a p + + type base region, the n + + type source region is arranged in the p well region, and the p + + type base region is arranged in the n + + type source region and is connected with the p well region;

it is plural p well district periodic arrangement in the upper surface on n-drift layer, JFET doped area is located adjacently between the p well district, first slot has been seted up in JFET doped area, JFET slot oxide cover in first slot the JFET doped area and the p well district, the gate electrode contact is located the upper surface of JFET slot oxide, and is adjacent the gate electrode contact is equipped with the space, insulating substance layer is located the upper surface of gate electrode contact just fills the space, source electrode contact be located the upper surface on insulating substance layer, and downwardly penetrate with n + + type source region and p + + type base region connects, drain electrode contact is located the lower surface of n + + type substrate.

Furthermore, a second groove is formed in the gate electrode in a contact mode, the second groove is located in the first groove, and the insulating substance layer fills the second groove.

Further, the gate electrode contact is a polysilicon gate electrode contact, the source electrode contact is a metal source electrode contact, and the drain electrode contact is a metal drain electrode contact.

The utility model has the advantages of as follows: (1) due to the adoption of a JFET groove etching technology, the design of a JFET doping region of the SiC-based DMOSFET device tends to be more flexible; (2) the resistance of a JFET (junction field effect transistor) doped region of the SiC-based DMOSFET device is converted into accumulated resistance, and the on-state resistance of the device is reduced under the condition that the JFET region is highly doped; (3) when the reverse blocking is carried out, the electric field of the device gate dielectric is greatly reduced by the self-consistent shielding effect of the contact of the adjacent P well area and the gate electrode, and the electric field reliability of the device is improved; (4) the bottom of the JFET groove is filled with thick oxide, so that the overlapping area of the gate electrode contact and the drain electrode metal contact is reduced, the device has smaller Miller charges, and further, the overlapping area of the gate electrode contact and the drain electrode metal contact is further reduced through the separation structure of the gate electrode contact, and the dynamic conversion performance of the device is greatly improved. (5) Compared with the traditional DMOSFET device, the SiC-based DMOSFET device has higher bar Li plus optimal value and higher high-frequency switch optimal value.

Drawings

The invention will be further described with reference to the following examples with reference to the accompanying drawings.

Fig. 1 is a flow chart of the preparation of the SiC-based DMOSFET device of the present invention.

Fig. 2 is a schematic structural diagram of a SiC epitaxial material substrate according to the present invention.

Fig. 3 is a schematic structural view of the p well area of the present invention.

Fig. 4 is a schematic structural diagram of the n + + type source region manufactured in the present invention.

Fig. 5 is a schematic structural diagram of the p + + type base region manufactured in the present invention.

Fig. 6 is a schematic structural diagram of a JFET doped region made in the present invention.

Fig. 7 is a schematic structural diagram of the side wall mask manufactured in the present invention.

Fig. 8 is a schematic structural diagram of the first groove of the present invention.

Fig. 9 is a schematic structural diagram of the bottom oxide formed in the present invention.

Fig. 10 is a schematic diagram of the structure of the gate oxide made in the present invention.

Fig. 11 is a schematic structural diagram of a gate electrode contact according to a first embodiment of the present invention.

Fig. 12 is a schematic structural diagram of an insulating material layer according to a first embodiment of the present invention.

Fig. 13 is a schematic structural diagram of a source electrode contact and a drain electrode contact according to a first embodiment of the present invention.

Fig. 14 is a schematic structural diagram of a gate electrode contact according to a second embodiment of the present invention.

Fig. 15 is a schematic structural view of an insulating material layer according to a second embodiment of the present invention.

Fig. 16 is a schematic structural view of a source electrode contact and a drain electrode contact according to a second embodiment of the present invention.

The labels in the figures indicate: 10. the semiconductor device comprises an n + + type substrate, 20, an n + type buffer layer, 30, an n-type drift layer, 40, a first mask layer, 50, a p well region, 60, a first side wall mask, 70, an n + + type source region, 71, a p + + type base region, 80, a second mask layer, 90, a JFET doping region, 100, a second side wall mask, 110, a first groove, 120, bottom oxide, 121, gate oxide, 130, a first gate electrode contact, 131, a second gate electrode contact, 132, a second groove, 140, an insulating material layer, 150, a source electrode contact, 160 and a drain electrode contact.

Detailed Description

Referring to fig. 1 to 13, a first embodiment of the present invention is shown.

A SiC-based DMOSFET device, comprising a SiC epitaxial material substrate, an active doped region, a JFET doped region 90, a JFET trench oxide, a gate electrode contact, a source electrode contact 150 and a drain electrode contact 160, wherein the SiC epitaxial material substrate comprises an n + + type substrate 10, an n + type buffer layer 20 and an n-type drift layer 30, the n + type buffer layer 20 is located on the upper surface of the n + + type substrate 10, the n-type drift layer 30 is located on the upper surface of the n + type buffer layer 20, the active doped region comprises a pwell region 50, an n + + type source region 70 and a p + + type base region 71, the n + + type source region 70 is disposed in the pwell region 50, and the p + + type base region 71 is disposed in the n + + type source region 70 and is connected to the pwell region 50;

a plurality of p-well regions 50 are periodically arranged on the upper surface of the n-drift layer, the JFET doped region 90 is located between adjacent p-well regions 50, the JFET doped region 90 has a first trench 110, the JFET trench oxide covers the first trench 110, the JFET doped region 90 and the p-well regions 50, the gate electrode contact is located on the upper surface of the JFET trench oxide, the adjacent gate electrode contact has a gap, the insulating material layer 140 is located on the upper surface of the gate electrode contact and fills the gap, the source electrode contact 150 is located on the upper surface of the insulating material layer 140 and penetrates downwards to connect with the n + + type source region 70 and the p + + type base region 71, and the drain electrode contact 160 is located on the lower surface of the n + + type substrate 10.

The gate electrode contact is a polysilicon gate electrode contact, the source electrode contact 150 is a metal source electrode contact, and the drain electrode contact 160 is a metal drain electrode contact. The gate electrode contact of embodiment one is the first gate electrode contact 130.

The periodic arrangement is that a certain distance is reserved between adjacent active doping regions, and each active doping region is arranged in a certain direction according to the distance. The JFET trench oxide includes a bottom oxide 120 and a gate oxide 121, the bottom oxide 120 is located at the bottom of the first trench 110, and the gate oxide 121 is located at both sides of the first trench 110 and covers the JFET doped region 90 and the pwell region 50. JFET doped region 90 is an n + doped region. N + + type > n-type, arranged in terms of doping concentration.

The technical scheme of the utility model is from aspects comprehensive consideration such as SiC base MOS grid dielectric electric field, MOSFET device on-resistance, miller charge, the SiC base DMOSFET device of design has T type bars structure, utilizes the self consistent shielding effect of T type bars, reduces gate oxide 121 electric field and can effectively keep JFET doping area 90's low resistance. Meanwhile, through the shielding effect between the T-shaped gate and the adjacent Pwell region 50, the Miller charge of the device is reduced, so that the switching conversion capacity of the SiC-based DMOSFET device is improved.

The JFET doping area 90 of the SiC-based DMOSFET device of the utility model is provided with a high doping layer and an etching groove, and the gate electrode contact has a T-shaped structure; when the transistor is in forward conduction, electrons enter the high-doping layer along the surface of the p well region 50 and enter the drift layer along the side wall of the first groove 110, so that the resistance of the JFET is effectively reduced; when reverse blocking is carried out, the gate oxide 121 is effectively protected by the self-consistent shielding effect of the contact of the adjacent P well and the gate electrode, so that the electric field of the gate dielectric of the device is greatly reduced, and avalanche occurs at the PN junction of the body area of the device. The utility model discloses a SiC base DMOSFET device has lower forward on resistance and higher reverse blocking ability, and the static state of this device, dynamic operational reliability obtain improving.

The preparation method of the SiC-based DMOSFET device comprises the following steps:

step S1, cleaning the SiC epitaxial material substrate;

the SiC epitaxial material substrate in step S1 includes an n + + type substrate 10, an n + type buffer layer 20, and an n-type drift layer 30, where the n + type buffer layer 20 is formed on the upper surface of the n + + type substrate 10, and the n-type drift layer 30 is formed on the upper surface of the n + type buffer layer 20;

the SiC epitaxial material substrate is cleaned, and the specific operations are as follows:

a. ultrasonic cleaning with acetone and ethanol sequentially for three times, and washing with deionized water.

b. And (3) putting the SiC epitaxial material substrate subjected to organic ultrasonic treatment into concentrated sulfuric acid and hydrogen peroxide solution to be boiled for at least 10 min.

c. And (3) boiling the SiC epitaxial material substrate which is boiled with concentrated sulfuric acid for 15min by using the first liquid and the second liquid in sequence, washing the SiC epitaxial material substrate by using deionized water, and drying the SiC epitaxial material substrate by using nitrogen for later use. The first liquid is a mixed liquid of ammonia water, hydrogen peroxide and deionized water, and the volume ratio of the ammonia water to the hydrogen peroxide to the deionized water is 1 to 2 to 5; the second solution is a mixed solution of hydrochloric acid, hydrogen peroxide and deionized water, and the volume ratio of the hydrochloric acid to the hydrogen peroxide to the deionized water is 1 to 2 to 5.

d. And (3) soaking the washed SiC epitaxial material substrate in diluted hydrofluoric acid for 1min, wherein the volume ratio of hydrogen fluoride to deionized water is 1:3, removing the oxide on the surface, cleaning with the deionized water, and drying.

Step S2, implanting a plurality of active doping regions arranged periodically on the upper surface of the n-type drift layer 30 in a self-aligned manner; the active doping region comprises a p well region 50, an n + + type source region 70 and a p + + type base region 71;

referring to fig. 3, a plurality of p well regions 50 arranged in a periodic manner are implanted in a self-aligned manner on the upper surface of the SiC epitaxial material substrate; specifically, a mask layer, which may be SiO, is deposited on the n-type drift layer 30 by CVD or PVD₂Or Si₃N₄Or polysilicon or metal material, is patterned by photolithography using photolithography mask A to form an injection first mask layer 40; forming a p-well region 50 in the n-type drift layer 30 by doping methods such as ion implantation, wherein the top doping concentration of the p-well region 50 is lower than the bottom doping concentration, and the top doping concentration is 1 × 10¹⁶cm^-3～5×10¹⁷cm^-3Bottom doping concentration of 5 × 10¹⁷cm^-3～1×10¹⁹cm^-3。

Referring to fig. 4, the n + + type source region 70 is formed in the P well region 50; in particular, a secondary mask, which may be SiO, is deposited using chemical vapor deposition or physical vapor deposition₂Or Si₃N₄Or polysilicon type, the secondary mask is etched to form a first sidewall mask 60. The first sidewall mask 60 can also be obtained by other polysilicon oxidation methods and other conventional techniques. According to the first sidewall mask 60, an n + + type source region 70 is formed in the p well region 50 by doping methods such as ion implantation, and the doping concentration of the n + + type source region 70 is 1 × 10¹⁸cm^-3～1×10²⁰cm^-3。

Referring to fig. 5, forming the P + + type base region 71 in the n + + type source region 70, where the P + + type base region 71 is further connected to the P well region 50; specifically, a mask layer is formed by photoetching and patterning, a p + + type base region 71 is formed in the n + + type source region 70 by using a doping method such as ion implantation, and the doping concentration of the p + + type base region 7171 is 1 × 10¹⁹cm^-3～1×10²¹cm^-3. Thus completing the active dopingPreparation of the regions.

Step S3, injecting JFET doped regions 90 between the adjacent active doped regions in a self-aligned mode;

the self-aligned implantation operation in this step S3 and the self-aligned implantation operation in the above step S2 use the same reticle a, namely: the required mask is obtained by reversing the graph of the same photoetching plate.

Referring to fig. 6, a mask layer, which may be SiO, is deposited on the n-type drift layer 30 by cvd or pvd₂Or Si₃N₄Or polysilicon or metal material, forming the second mask layer 80 by photolithography A, and forming the JFET doped region 90 by doping methods such as ion implantation; the doping concentration of the JFET doped region 90 is 2 x 10¹⁶cm^-3～2×10¹⁸cm^-3。

Step S4, self-aligned etching a first trench 110 in the JFET doped region 90;

this step is achieved by self-aligned etching without an additional photolithography mask on the basis of the self-aligned implantation of the JFET doping region 90 in step S3.

Referring to FIG. 7, a secondary mask, which may be SiO, is deposited using chemical vapor deposition or physical vapor deposition₂Or Si₃N₄Or polysilicon type, the secondary mask is etched to form the second sidewall mask 100. The second sidewall mask 100 can also be obtained by other polysilicon oxidation methods and other prior art methods.

Referring to FIG. 8, the SiC substrate is dry etched by physical, chemical, etc. etching means, such as Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP), etc., and the etching gas used may be SF₆/O₂、NF₃/Ar、CF₄、HBr、CHF₃/O₂、C₄F₈/O₂The etching conditions of the gas or combination of (1) are as follows: forming a first groove 110 in the JFET doping area 90 at the ICP power of 600W-1000W, the bias power of 100W-300W and the temperature of 17-70 ℃, wherein the first groove 110 is positioned between the adjacent p well areas 50; wherein the first trench 110 anda JFET doped region 90 with a certain width is reserved between the p well regions 50; the depth of the first trench 110 is less than or equal to the thickness of the pwell region 50.

Step S5, forming JFET trench oxide on the upper surfaces of the first trench 110, the JFET doped region 90 and the pwell region 50; thin film deposition techniques and etching techniques are used.

Referring to fig. 9, the mask layer in step S4 is removed, the SiC surface is standard cleaned, and then the pwell region 50, the n + + type source region 70, the p + + type base region 71, and the JFET doping region 90 in the previous steps are activated, wherein the activation method includes covering with carbon film, AlN film, SiH, and JFET doping region 90₄Inhibition, etc. and annealing at 1400-1800 deg.c and 600-700Torr for 10-30 min.

Then, sacrificial oxygen treatment is performed, the SiC surface is cleaned in a standard manner, the first trench 110 is filled by using thin film deposition technologies such as physical vapor deposition, chemical vapor deposition, atomic layer deposition and the like, the filling material can be silicon dioxide, silicon nitride and other media, the filling material completely covers the inside of the first trench 110 and the upper portion of the SiC substrate, and the filling material has a planarized surface.

Dry etching the above-mentioned filling material by physical, chemical or other etching means, such as Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP), to finally form a bottom oxide 120 with a certain thickness at the bottom of the first trench 110, wherein the thickness of the bottom oxide 120 is 300nm to 800nm, and the etching gas used may be SF₆/O₂、NF₃/Ar、CF₄、CHF₃/O₂、C₄F₈/O₂And the like.

Referring to FIG. 10, the SiC substrate is cleaned by organic and inorganic methods, and is then oxidized and annealed by dry oxidation at 1100-1300 deg.C for about half an hour, and then annealed at 1200-1300 deg.C for 1-3 hours in NO atmosphere, wherein the annealing atmosphere is not only NO but also POCl₃，H₂，N₂O，P₂O₅Sb + NO, etc., to finally obtain a gate oxide 121, which gate oxide 121 may also pass through a physical or chemical vapor phaseDeposition or atomic layer deposition.

The JFET trench oxide includes a bottom oxide 120 and a gate oxide 121.

Step S6, forming a gate electrode contact on the upper surface of the JFET groove oxide;

referring to fig. 11, the surface of the formed JFET trench oxide is filled with highly doped polysilicon by using thin film deposition techniques such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, and the like. And then, the deposited high-doped polysilicon is dry-etched by utilizing a photoetching mask and etching means such as physical and chemical etching means, such as Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP), and finally, a gate electrode contact is formed on the surfaces of the bottom oxide 120 and the gate oxide 121.

Step S7, forming an insulating material layer 140 on the upper surface of the gate electrode contact, wherein the insulating material layer 140 is provided with a contact via, forming a source electrode contact 150 on the upper surface of the insulating material layer 140, and the source electrode contact 150 is connected to the active doped region through the contact via;

referring to fig. 12, a layer of insulating material 140 is deposited on the SiC substrate where the gate electrode contact has been formed using a thin film deposition technique such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., the layer of insulating material 140 having a planarized surface.

Referring to fig. 13, the contact via is formed by dry etching the insulating material layer 140 by physical, chemical or other etching means, such as Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP), using photolithography patterning, wherein the etching gas for the dry etching may be SF₆/O₂、NF₃/Ar、CF₄、CHF₃/O₂、C₄F₈/O₂Combinations of gases, etc.; and sequentially depositing multiple layers of Ni, Ti and Al by using a film deposition method such as electron beam evaporation or sputtering, and stripping to form the source electrode contact 150.

Step S8 is to form a drain contact 160 on the lower surface of the n + + type substrate 10.

Referring to fig. 13, the front surface of the formed SiC substrate is coated with photoresist for protection, the oxide layer on the back surface of the n + + type substrate 10 is removed by diluted HF, a metal layer, which may be a metal such as AlTi, Ni, TiW, AlTi or a combination thereof, is deposited on the back surface by a thin film deposition method such as electron beam evaporation or sputtering, to form a drain electrode contact 160, and the front photoresist is removed.

Annealing the source electrode contact 150 and the drain electrode contact 160 at 900-1100 deg.C under nitrogen or argon to form ohmic contacts. And depositing a thicker metal layer on the front surface of the SiC substrate by using a film deposition method such as electron beam evaporation or sputtering, and the like to form contact interconnection.

Referring to fig. 14 to 16, a second embodiment of the present invention is shown.

In the present invention, the gate electrode contacts the DMOSFET device, and a second trench 132 is formed in the gate electrode, the second trench 132 is located in the first trench 110, and the insulating material layer 140 fills the second trench 132. The gate electrode contact in embodiment two is the second gate electrode contact 131.

In the method for manufacturing the SiC-based DMOSFET device of the present embodiment, please refer to the first embodiment of the present invention from step S1 to step S5 and other portions not described above.

step S6-1, etching the gate electrode contact at the position of the first trench 110 to form a second trench 132, wherein the depth of the second trench 132 extends downward to the JFET trench oxide;

referring to fig. 14, the surface of the JFET trench oxide formed is filled with highly doped polysilicon by using thin film deposition techniques such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. And then, dry etching the deposited highly doped polysilicon by using a photolithography mask and physical and chemical etching means, such as Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP), to form a second trench 132, and finally forming a gate electrode contact on the surface of the gate oxide 121, wherein the gate electrode contact is not formed on the surface of the bottom oxide 120 and in the second trench 132.

in step S7-1, the insulating material layer 140 further fills the second trench 132.

Referring to fig. 15, a layer of insulating material 140 is deposited on the SiC substrate having the gate electrode contact formed thereon by using a thin film deposition technique such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., wherein the layer of insulating material 140 simultaneously fills the second trench 132 and has a planarized surface.

Referring to fig. 16, the contact via is formed by dry etching the insulator layer by physical, chemical or other etching means, such as Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP), using photolithography patterning, wherein the etching gas for the dry etching may be SF₆/O₂、NF₃/Ar、CF₄、CHF₃/O₂、C₄F₈/O₂Combinations of gases, etc.; patterning by photolithography, evaporating or sputtering the film by electron beamAnd the deposition method comprises the steps of sequentially depositing multiple layers of Ni, Ti and Al, and stripping to form the source electrode contact 150.

Referring to fig. 16, the front surface of the SiC substrate is coated with photoresist for protection, the oxide layer on the back surface of the n + + type substrate 10 is removed by diluted HF, a metal layer is deposited on the back surface by a thin film deposition method such as electron beam evaporation or sputtering, the metal layer may be a metal such as AlTi, Ni, TiW, AlTi, or a combination thereof to form a drain electrode contact 160, and then the front photoresist is removed.

The substrate material used in the above embodiments is not limited to SiC material, but may include power electronic semiconductor material such as silicon, gallium nitride, gallium oxide, and diamond. When other semiconductor materials are used as the substrate, the resulting DMOSFET device with low on-resistance and miller charge and the manufacturing method thereof are all included in the protection scope of the present disclosure.

The gate oxide 121 material used in the above-described embodiments is not limited to SiO2, but may be other oxide materials such as Al₂O₃、Si_xN_y(x, y are element ratios) and AlN, AlON, HfO₂High k dielectric materials and combinations thereof.

It should be noted that directional terms, such as "upper", "lower", etc., mentioned in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure.

The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above-mentioned embodiments are only specific embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A SiC-based DMOSFET device is characterized in that: the SiC epitaxial material substrate comprises an n + + type substrate, an n + type buffer layer and an n-type drift layer, wherein the n + type buffer layer is positioned on the upper surface of the n + + type substrate, the n-type drift layer is positioned on the upper surface of the n + + type buffer layer, the active doping region comprises a p well region, an n + + type source region and a p + + type base region, the n + + type source region is arranged in the p well region, and the p + + type base region is arranged in the n + + type source region and is connected with the p well region;

it is plural p well district periodic arrangement in the upper surface on n-drift layer, JFET doped area is located adjacently between the p well district, first slot has been seted up in JFET doped area, JFET slot oxide cover in first slot the JFET doped area and the p well district, the gate electrode contact is located the upper surface of JFET slot oxide, and is adjacent the gate electrode contact is equipped with the space, and insulating substance layer is located the upper surface of gate electrode contact just fills the space, source electrode contact be located the upper surface of insulating substance layer, and downward penetration with n + + type source region and p + + type base region connection, drain electrode contact is located the lower surface of n + + type substrate.

2. The SiC-based DMOSFET device of claim 1, wherein: and a second groove is formed in the gate electrode in a contact manner, the second groove is positioned in the first groove, and the insulating substance layer fills the second groove.

3. The SiC-based DMOSFET device of claim 1, wherein: the gate electrode contact is a polysilicon gate electrode contact, the source electrode contact is a metal source electrode contact, and the drain electrode contact is a metal drain electrode contact.