CN109801959A - A kind of SiC base DMOSFET device and preparation method thereof - Google Patents
A kind of SiC base DMOSFET device and preparation method thereof Download PDFInfo
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Abstract
The present invention relates to semiconductor fields, a kind of SiC base DMOSFET device and preparation method thereof is provided, including SiC epitaxial material substrate, there is source dopant region, JFET doped region, JFET trench oxide, gate electrode contact, source electrode contact is contacted with drain electrode, SiC epitaxial material substrate includes n++ type substrate base, n+ type buffer layer and n-type drift layer, having source dopant region includes the area p well, n++ type source region and p++ type base area, JFET doped region offers first groove, JFET trench oxide is covered in first groove, JFET doped region and the area p well, gate electrode contact is located at the upper surface of JFET trench oxide, insulating material layer is located at the upper surface of gate electrode contact and filling gap, source electrode contact is located at insulating material layer Upper surface, drain electrode contact be located at n++ type substrate base lower surface.The advantage of the invention is that for reducing the JFET resistance and Miller charge of SiC base DMOSFET device, to improve the high-frequency figure of merit of the SiC base DMOSFET device.
Description
Technical field
The present invention relates to semiconductor fields, more particularly to a kind of SiC base DMOSFET device and preparation method thereof.
Background technique
The physically and electrically characteristic of silicon carbide (SiC) material has apparent advantage compared to traditional Si material.SiC tool
There is the features such as forbidden band is wide, thermal conductivity is high, disruptive field intensity is high, saturated electrons drift speed is high, while also with fabulous physics
And chemical stability, extremely strong Radiation hardness and mechanical strength etc..Therefore, the electronic device based on broad stopband SiC material can
For field of power electronics such as high temperature, high-power, high frequency, high radiation, and SiC base device can be given full play in energy-saving and emission-reduction side
Considerable advantage occupied by face and outstanding feature.
SiC metal-oxide semiconductor fieldeffect transistor (MOSFET) power device in commercialization process very
Maturation, especially using the MOSFET of planar gate structure as mainstream, i.e. DMOSFET.However, SiC base DMOSFET device is situated between in grid
The reliability etc. of matter layer encounters larger challenge, wherein main reasons is that thermal oxide SiC substrate and the SiO2 layer that is formed
There is more interfacial state between SiC substrate, these interfacial states are captured under high temperature High-Field or launching electronics, are unfavorable for device
Electrical stability.
On the one hand, in order to improve the reliability of the gate oxide of SiC base DMOSFET device, designer can be using reducing adjacent p
The method of distance improves its shielding action between trap, however thus leads to the raising of JFET resistance, is unfavorable for break-over of device electricity
The reduction of resistance.On the other hand, when SiC base DMOSFET device is used for high frequency field, Miller charge determines the height of its switching loss
It is low, therefore to solve how to reduce the Miller charge of the device.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of SiC base DMOSFET device and preparation method thereof, is used for
The JFET resistance and Miller charge for reducing SiC base DMOSFET device, so that the high frequency for improving the SiC base DMOSFET device is excellent
Value.
The present invention is implemented as follows:
A kind of SiC base DMOSFET device, including SiC epitaxial material substrate, have source dopant region, JFET doped region, JFET ditch
Slot oxide, gate electrode contact, source electrode contact are contacted with drain electrode, and the SiC epitaxial material substrate includes n++ type substrate base
Piece, n+ type buffer layer and n-type drift layer, the n+ type buffer layer are located at the upper surface of the n++ type substrate base, the n-
Type drift layer is located at the upper surface of the n+ type buffer layer, and described to have source dopant region include the area p well, n++ type source region and p++
Type base area, the n++ type source region are built in the area the p well, p++ type base area be built in the n++ type source region and with institute
State the connection of the area p well；
A plurality of p well area's periodic arrangements are located at phase in the upper surface of the n- drift layer, the JFET doped region
Between the adjacent area the p well, the JFET doped region offers first groove, and the JFET trench oxide is covered in institute
First groove, the JFET doped region and the area the p well are stated, the gate electrode contact is located at the JFET groove and aoxidizes
The upper surface of object, adjacent gate electrode contact are equipped with gap, and the insulating material layer is located at the upper of gate electrode contact
Surface and the filling gap, the source electrode contact are located at the upper surface of the insulating material layer and penetrate and the n downwards
++ type source region and the connection of p++ type base area, the drain electrode contact are located at the lower surface of the n++ type substrate base.
Further, the gate electrode contact offers second groove, and the second groove is located at the first groove, institute
It states insulating material layer and fills the second groove.
Further, the gate electrode contact is that polygate electrodes contact, and the source electrode contact is metal source
Contact, the drain electrode contact are that metal leakage pole contacts.
A kind of preparation method of SiC base DMOSFET device, comprising:
Step S1, SiC epitaxial material substrate is cleaned；
Step S2, it is injected in the upper surface autoregistration of the SiC epitaxial material substrate a plurality of in the active of periodic arrangement
Doped region；
Step S3, autoregistration between source dopant region described in adjacent injects JFET doped region；
Step S4, the Self-aligned etching first groove in the JFET doped region；
Step S5, JFET is formed in the upper surface of the first groove, the JFET doped region and the area the p well
Trench oxide；
Step S6, gate electrode contact is formed in the upper surface of the JFET trench oxide；
Step S7, insulating material layer is formed in the upper surface of gate electrode contact, the insulating material layer, which offers, to be connect
Through-hole is touched, forms source electrode contact in the upper surface of the insulating material layer, the source electrode contact passes through contact through hole and institute
Source dopant region connection is stated；
Step S8, drain electrode contact is formed in the lower surface of the SiC epitaxial material substrate.
Further, the SiC epitaxial material substrate in the step S1 includes n++ type substrate base, n+ type buffer layer, n-
Type drift layer, the n+ type buffer layer are initially formed in the upper surface of the n++ type substrate base, and the n-type drift layer re-forms
In the upper surface of the n+ type buffer layer；
The step S2 specifically: injecting a plurality of in the upper surface autoregistration of the n-type drift layer is in periodic arrangement
There is source dopant region；
The step S8 specifically: form drain electrode contact in the lower surface of the n++ type substrate base.
Further, the source dopant region that has in the step S2 includes the area p well, n++ type source region and p++ type base area, institute
It is further to state step S2 are as follows: first injecting a plurality of in the upper surface autoregistration of the SiC epitaxial material substrate is in periodic arrangement
The area the p well forms the n++ type source region in the area the P well, forms the p in the n++ type source region
++ type base area, P++ type base area are also connect with the area the p well.
Further, the autoregistration implant operation in the step S3 is with the autoregistration implant operation in the step S2
Using identical reticle.
Further, the depth of the first groove is less than or equal to the thickness in the area p well.
Further, JFET trench oxide is formed in the step S5 is using film deposition techniques and lithographic technique.
Further, further include step S6-1 after the step S6, further include step S7-1 after the step S7:
Step S6-1, in the position of the first groove, gate electrode contact is performed etching, second groove is formed,
The depth of the second groove extends substantially downward to the JFET trench oxide；
Step S7-1, the described insulating material layer also fills up the second groove.
The present invention has the advantage that (1) due to using JFET etching groove technology, so that SiC base DMOSFET device
The design of JFET doped region more tends to flexibility；(2) resistance of the JFET doped region of SiC base DMOSFET device is converted into accumulation
Resistance, in the case where guaranteeing that the region JFET is highly doped, so that device on state resistance reduces；(3) when reverse blocking, adjacent P
The shielding action of being in harmony certainly of the area well and gate electrode contact substantially reduces the electric field of device gate dielectric, improves the electric field of device
Reliability；(4) JFET channel bottom is filled by thick-oxide, reduces the faying surface of gate electrode contact and drain metal contact
Product, therefore device has lesser Miller charge, further, the separated structure contacted by gate electrode, so that gate electrode connects
The overlapping area of touching and drain metal contact further decreases, and greatly improves the dynamic conversion performance of device.(5) described in
SiC base DMOSFET device has the higher Ba Lijia figure of merit and bigger HF switch compared to traditional DMOSFET device
The figure of merit.
Detailed description of the invention
The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is the preparation flow figure of SiC base DMOSFET device of the invention.
Fig. 2 is the structural schematic diagram of SiC epitaxial material substrate in the present invention.
Fig. 3 is the structural schematic diagram that the area p well is made in the present invention.
Fig. 4 is the structural schematic diagram that n++ type source region is made in the present invention.
Fig. 5 is the structural schematic diagram that p++ type base area is made in the present invention.
Fig. 6 is the structural schematic diagram that JFET doped region is made in the present invention.
Fig. 7 is the structural schematic diagram that side wall exposure mask is made in the present invention.
Fig. 8 is the structural schematic diagram that first groove is made in the present invention.
Fig. 9 is the structural schematic diagram that bottom oxide is made in the present invention.
Figure 10 is the structural schematic diagram that gate oxide is made in the present invention.
Figure 11 is the structural schematic diagram that gate electrode contact is made in the embodiment of the present invention one.
Figure 12 is the structural schematic diagram that insulating material layer is made in the embodiment of the present invention one.
Figure 13 is that source electrode is made in the embodiment of the present invention one to contact the structural schematic diagram contacted with drain electrode.
Figure 14 is the structural schematic diagram that gate electrode contact is made in the embodiment of the present invention two.
Figure 15 is the structural schematic diagram that insulating material layer is made in the embodiment of the present invention two.
Figure 16 is that source electrode is made in the embodiment of the present invention two to contact the structural schematic diagram contacted with drain electrode.
Marking in figure indicates: 10, n++ type substrate base, 20, n+ type buffer layer, 30, n-type drift layer, the 40, first exposure mask
Layer, 50, the area p well, the 60, first side wall exposure mask, 70, n++ type source region, 71, p++ type base area, the 80, second mask layer, 90,
JFET doped region, the 100, second side wall exposure mask, 110, first groove, 120, bottom oxide, 121, gate oxide, 130, first
Gate electrode contact, the contact of the 131, second gate electrode, 132, second groove, 140, insulating material layer, 150, source electrode contact, 160,
Drain electrode contact.
Specific embodiment
Please refer to Fig. 1 to Figure 13, the embodiment of the present invention one.
A kind of SiC base DMOSFET device, including SiC epitaxial material substrate, have source dopant region, JFET doped region 90, JFET
Trench oxide, gate electrode contact, source electrode contact 150 contact 160 with drain electrode, and the SiC epitaxial material substrate includes n++
Type substrate base 10, n+ type buffer layer 20 and n-type drift layer 30, the n+ type buffer layer 20 are located at the n++ type substrate base
10 upper surface, the n-type drift layer 30 are located at the upper surface of the n+ type buffer layer 20, and described to have source dopant region include p
The area well 50, n++ type source region 70 and p++ type base area 71, the n++ type source region 70 are built in the area the p well 50, the p++
Type base area 71 is built in the n++ type source region 70 and connect with the area the p well 50；
A plurality of 50 periodic arrangements of the area the p well are in the upper surface of the n- drift layer, the JFET doped region 90
Between the adjacent area the p well 50, the JFET doped region 90 offers first groove 110, the JFET groove oxidation
Object is covered in the first groove 110, the JFET doped region 90 and the area the p well 50, and the gate electrode contact is located at
The upper surface of the JFET trench oxide, adjacent gate electrode contact are equipped with gap, and the insulating material layer 140 is located at
The upper surface and the filling gap of the gate electrode contact, the source electrode contact 150 are located at the insulating material layer 140
It upper surface and penetrates and connect with the n++ type source region 70 and p++ type base area 71 downwards, described drain electrode contact 160
In the lower surface of the n++ type substrate base 10.
The gate electrode contact is that polygate electrodes contact, and the source electrode contact 150 contacts for metal source, institute
Drain electrode contact 160 is stated to contact for metal leakage pole.The gate electrode contact of embodiment one is first gate electrode contact 130.
Wherein, periodic arrangement is that adjacent active mix has certain spacing between area, each has source dopant region by this spacing
It is arranged toward certain direction.JFET trench oxide includes bottom oxide 120 and gate oxide 121, and bottom oxide 120
In the bottom of first groove 110, gate oxide 121 is located at the two sides of first groove 110 and is covered in JFET doped region 90 and p
The upper surface in the area well 50.JFET doped region 90 is n+ type doped region.It is arranged according to doping concentration, n++ type > n+ type > n-type.
The technical scheme is that from SiC base mos gate medium electric field, MOSFET element conducting resistance, Miller charge etc.
Aspect comprehensively considers, and the SiC base DMOSFET device of design has T-type grid structure, is in harmony shielding action certainly using T-type grid, reduces
121 electric field of gate oxide and the low resistance that can effectively keep JFET doped region 90.Meanwhile passing through T-type grid and the area adjacent P well
Shielding action between 50 reduces the Miller charge of device, to improve the switch conversion ability of SiC base DMOSFET device.
The JFET doped region 90 of SiC base DMOSFET device of the invention has heavily doped layer and etching groove, and gate electrode connects
Touching has T-type structure；When forward conduction, electronics enters heavily doped layer along 50 surface of the area p well, and along first groove 110
Side wall enters drift layer, and JFET resistance is effectively reduced；When reverse blocking, the shielding of being in harmony certainly of adjacent P well and gate electrode contact is made
With effective protection gate oxide 121, so that device gate dielectric electric field substantially reduces, snowslide occurs at the PN junction in device body area.
SiC base DMOSFET device of the invention has lower forward conduction resistance and higher reverse blocking capability, and the device
Static, dynamic duty reliability is improved.
The preparation method of SiC base DMOSFET device of the invention, comprising:
Step S1, SiC epitaxial material substrate is cleaned；
SiC epitaxial material substrate in the step S1 includes n++ type substrate base 10, n+ type buffer layer 20, n-type drift
Layer 30 is moved, the n+ type buffer layer 20 is initially formed in the upper surface of the n++ type substrate base 10, and the n-type drift layer 30 is again
It is formed in the upper surface of the n+ type buffer layer 20；
The SiC epitaxial material substrate is cleaned, concrete operations are as follows:
A. it is successively cleaned three times with acetone and EtOH Sonicate, then is rinsed with deionized water.
B. the SiC epitaxial material substrate after organic ultrasonic will be put into be placed in the concentrated sulfuric acid and hydrogen peroxide solution and is at least boiled
10min。
C. the SiC epitaxial material substrate for boiling the concentrated sulfuric acid is successively boiled into 15min with No.1 liquid and No. two liquid, then uses deionization
Water is stand-by with being dried with nitrogen after rinsing well.No.1 liquid is the mixed liquor of ammonium hydroxide, hydrogen peroxide and deionized water, by volume ammonia
Shui ︰ Guo Yangization Qing ︰ deionized water=1 ︰, 2 ︰ 5；No. two liquid are the mixed liquor of hydrochloric acid, hydrogen peroxide and deionized water, by volume
Yan Suan ︰ Guo Yangization Qing ︰ deionized water=1 ︰, 2 ︰ 5.
D. the SiC epitaxial material substrate after flushing is put into diluted hydrofluoric acid and impregnates 1min, hydrofluoric acid is by volume
Fluorine hydrogen ︰ deionized water=1:3, removes the oxide on surface, and cleaned with deionized water, then dry.
Step S2, injecting in the upper surface autoregistration of the n-type drift layer 30 a plurality of has source doping in periodic arrangement
Area；Having source dopant region includes the area p well 50, n++ type source region 70 and p++ type base area 71；
Referring to Fig. 3, first injecting a plurality of in the upper surface autoregistration of the SiC epitaxial material substrate is in periodic arrangement
The area the p well 50；Specifically, it using chemical vapor deposition or physical vapour deposition (PVD), is covered in deposit on n-type drift layer 30
Film layer, this mask layer can be SiO2Or Si3N4Or polysilicon or metal substance, it is that reticle A is utilized to carry out litho pattern
Change, forms the first mask layer 40 of injection；The doping methods such as ion implanting are recycled, the area p well is made in n-type drift layer 30
50, the top doping concentration in the area p well 50 is lower than bottom doping concentration, wherein top doping concentration is 1 × 1016cm-3~
5×1017cm-3, bottom doping concentration is 5 × 1017cm-3~1 × 1019cm-3。
Referring to Fig. 4, forming the n++ type source region 70 in the area the P well 50；Specifically, chemical gaseous phase is utilized
Deposition or physical vapour deposition (PVD), deposit secondary exposure mask, which can be SiO2Or Si3N4Or polysilicon substance, it carves
The secondary exposure mask is lost, the first side wall exposure mask 60 is formed.The first side wall exposure mask 60 can also pass through other polysilicon oxidation modes
Etc. the prior arts obtain.It is made in the area p well 50 according to the first side wall exposure mask 60 using doping methods such as ion implantings
N++ type source region 70, the doping concentration of n++ type source region 70 are 1 × 1018cm-3~1 × 1020cm-3。
Referring to Fig. 5, forming p++ type base area 71 in the n++ type source region 70, P++ type base area 71 is also
It is connect with the area the p well 50；Specifically, photolithography patterning forms mask layer, using doping methods such as ion implantings, in n++
P++ type base area 71 is made in type source region 70, the doping concentration of p++ type base area 7171 is 1 × 1019cm-3~1 × 1021cm-3.So far
Complete the preparation for having source dopant region.
Step S3, autoregistration between source dopant region described in adjacent injects JFET doped region 90；
Autoregistration implant operation in this step S3 and the autoregistration implant operation in above-mentioned steps S2 are using identical
Reticle A, it may be assumed that required mask plate is the acquisition of same reticle reversal pattern.
Referring to Fig. 6, using chemical vapor deposition or physical vapour deposition (PVD), in depositing exposure mask on n-type drift layer 30
Layer, the mask layer can be SiO2Or Si3N4Or polysilicon or metal substance form the second exposure mask of injection using reticle A
Layer 80, and using doping methods such as ion implantings, JFET doped region 90 is made；The doping concentration of JFET doped region 90 be 2 ×
1016cm-3~2 × 1018cm-3。
Step S4, the Self-aligned etching first groove 110 in the JFET doped region 90；
This step is to need not move through additional photo etched mask on the basis of JFET doped region 90 is injected in step S3 autoregistration
Version, is obtained by Self-aligned etching.
Secondary exposure mask, the secondary exposure mask are deposited using chemical vapor deposition or physical vapour deposition (PVD) refering to Fig. 7
It can be SiO2Or Si3N4Or polysilicon substance, the secondary exposure mask is etched, the second side wall exposure mask 100 is formed.Second side wall
Exposure mask 100 can also be obtained by prior arts such as other polysilicon oxidation modes.
Refering to Fig. 8, by the etching means such as physics, chemistry, such as reactive ion etching (RIE) either inductively coupled plasma
The methods of (ICP), dry etching SiC substrate, used etching gas can be SF6/O2、NF3/Ar、CF4、HBr、CHF3/
O2、C4F8/O2Gas or combination, etching condition are as follows: ICP power 600W~1000W, substrate bias power 100W~300W, temperature
17 DEG C~70 DEG C, first groove 110 is formed in JFET doped region 90, this first groove 110 is located at the adjacent area p well 50
Between；Wherein, the JFET doped region 90 of one fixed width is retained between first groove 110 and the area p well 50；First groove 110
Depth is less than or equal to the thickness in the area p well 50.
Step S5, in the upper surface shape of the first groove 110, the JFET doped region 90 and the area the p well 50
At JFET trench oxide；Use film deposition techniques and lithographic technique.
Refering to Fig. 9, the mask layer in step S4 is removed, then standard cleaning surface of SiC activates the p in abovementioned steps
The area well 50, n++ type source region 70, p++ type base area 71, JFET doped region 90, the Activiation method include being covered using carbon film, AlN film
Lid, SiH4The methods of inhibit, and in 1400 DEG C~1800 DEG C of high temperature, under conditions of pressure is 600-700Torr, anneal 10-
30 minutes.
It does again and sacrifices oxygen processing, and standard cleaning surface of SiC, utilize physical vapour deposition (PVD), chemical vapor deposition, atomic layer
The film deposition techniques such as deposition fill first groove 110, and filling substance used can be the media such as silica, silicon nitride,
The inside and SiC substrate top of first groove 110 is completely covered in the filler, and has planarization surface.
By the etching means such as physics, chemistry, such as reactive ion etching (RIE) either inductively coupled plasma (ICP),
The above-mentioned filler of dry etching finally forms certain thickness bottom oxide 120 in the bottom of first groove 110, should
Bottom oxide 120 with a thickness of 300nm~800nm, used etching gas can be SF6/O2、NF3/Ar、CF4、CHF3/
O2、C4F8/O2Deng gas or combination.
Referring again to Figure 10, organic and inorganic cleaning SiC substrate, using thermal oxidation and the method for post-oxidation anneal,
Or so dry-oxygen oxidation half an hour under conditions of 1100 DEG C~1300 DEG C, and in 1200 DEG C~1300 DEG C of temperature and NO atmospheric condition
Lower annealing 1~3 hour, this annealing atmosphere is not only NO, is also possible to POCl3, H2, N2O, P2O5, Sb+NO etc., final acquisition
Gate oxide 121, the gate oxide 121 can also be by being physically or chemically vapor-deposited or the methods of atomic layer deposition obtains.
JFET trench oxide includes bottom oxide 120 and gate oxide 121.
Step S6, gate electrode contact is formed in the upper surface of the JFET trench oxide；
Refering to fig. 11, using film deposition techniques such as physical vapour deposition (PVD), chemical vapor deposition, atomic layer depositions,
Highly doped polysilicon is filled on the surface of the JFET trench oxide of formation.Recycle the erosion such as photo etched mask and physics, chemistry
Quarter means, such as reactive ion etching (RIE) either inductively coupled plasma (ICP), dry etching deposited highly doped
Finally gate electrode contact is made in bottom oxide 120 and 121 surface of gate oxide in polysilicon.
Step S7, insulating material layer 140 is formed in the upper surface of gate electrode contact, the insulating material layer 140 is opened
Equipped with contact through hole, source electrode contact 150 is formed in the upper surface of the insulating material layer 140, the source electrode contact 150 is logical
Crossing contact through hole has source dopant region connection with described；
Refering to fig. 12, using film deposition techniques such as physical vapour deposition (PVD), chemical vapor deposition, atomic layer depositions,
It is formed and deposits insulating material layer 140 on the SiC substrate of gate electrode contact, which has hardware and software platform surface.
Refering to fig. 13, using photolithography patterning, by the etching means such as physics, chemistry, dry etching insulating material layer 140,
Such as reactive ion etching (RIE) either inductively coupled plasma (ICP), forms contact through hole, the quarter of the dry etching
Erosion gas can be SF6/O2、NF3/Ar、CF4、CHF3/O2、C4F8/O2Deng combination of gases；Utilize electron beam evaporation or sputtering etc.
Membrane deposition method, successively deposits the multiple layer metal of Ni, Ti, Al, and removing forms source electrode contact 150.
Step S8, drain electrode contact 160 is formed in the lower surface of the n++ type substrate base 10.
It referring again to Figure 13, protects in established SiC substrate front resist coating, and is served as a contrast with diluted HF removal n++ type
The oxide layer at 10 back side of bottom substrate utilizes the membrane deposition methods such as electron beam evaporation or sputtering overleaf deposited metal, the gold
Belonging to layer can be metals such as AlTi, Ni, TiW, AlTi or combinations thereof, drain electrode contact 160 be made, then remove front photoresist.
In 900 DEG C~1100 DEG C of temperature range, nitrogen or argon gas condition annealing source electrode contact 150, drain electrode are connect
Touching 160, forms it into Ohmic contact.The membrane deposition methods such as deposited by electron beam evaporation or sputtering deposit thicker in SiC substrate front
Metal layer forms contact interconnection.
The present invention has the advantage that (1) due to using JFET etching groove technology, so that SiC base DMOSFET device
The design of JFET doped region more tends to flexibility；(2) resistance of the JFET doped region of SiC base DMOSFET device is converted into accumulation
Resistance, in the case where guaranteeing that the region JFET is highly doped, so that device on state resistance reduces；(3) when reverse blocking, adjacent P
The shielding action of being in harmony certainly of the area well and gate electrode contact substantially reduces the electric field of device gate dielectric, improves the electric field of device
Reliability；(4) JFET channel bottom is filled by thick-oxide, reduces the faying surface of gate electrode contact and drain metal contact
Product, therefore device has lesser Miller charge, further, the separated structure contacted by gate electrode, so that gate electrode connects
The overlapping area of touching and drain metal contact further decreases, and greatly improves the dynamic conversion performance of device.(5) described in
SiC base DMOSFET device has the higher Ba Lijia figure of merit and bigger HF switch compared to traditional DMOSFET device
The figure of merit.
Please refer to Figure 14 to Figure 16, the embodiment of the present invention two.
In SiC base DMOSFET device of the invention, the gate electrode, which contacts, offers second groove 132, and described second
Groove 132 is located at the first groove 110, and the insulating material layer 140 fills the second groove 132.In embodiment two
Gate electrode contact is the second gate electrode contact 131.
The preparation method of SiC base DMOSFET device of the invention, wherein step S1 to step S5 and other not described parts
Please refer to the embodiment of the present invention one.
Step S6, gate electrode contact is formed in the upper surface of the JFET trench oxide；
Step S6-1, in the position of the first groove 110, gate electrode contact is performed etching, the second ditch is formed
Slot 132, the depth of the second groove 132 extend substantially downward to the JFET trench oxide；
Refering to fig. 14, using film deposition techniques such as physical vapour deposition (PVD), chemical vapor deposition, atomic layer depositions,
It is formed on the surface of JFET trench oxide and fills highly doped polysilicon.Recycle the etching such as photo etched mask and physics, chemistry
Means, such as reactive ion etching (RIE) either inductively coupled plasma (ICP), dry etching are deposited highly doped more
Crystal silicon forms second groove 132, gate electrode contact finally is made on 121 surface of gate oxide, wherein 120 table of bottom oxide
On face and there is no gate electrode contact in second groove 132.
Step S7, insulating material layer 140 is formed in the upper surface of gate electrode contact, the insulating material layer 140 is opened
Equipped with contact through hole, source electrode contact 150 is formed in the upper surface of the insulating material layer 140, the source electrode contact 150 is logical
Crossing contact through hole has source dopant region connection with described；
Step S7-1, the described insulating material layer 140 also fills up the second groove 132.
Refering to fig. 15, using film deposition techniques such as physical vapour deposition (PVD), chemical vapor deposition, atomic layer depositions,
It is formed and deposits insulating material layer 140 on the SiC substrate of gate electrode contact, which fills second groove simultaneously
132, there is hardware and software platform surface.
Refering to fig. 16, using photolithography patterning, by the etching means such as physics, chemistry, dry etching insulator layer such as reacts
Ion etching (RIE) either inductively coupled plasma (ICP) etc. forms contact through hole, the etching gas of the dry etching
It can be SF6/O2、NF3/Ar、CF4、CHF3/O2、C4F8/O2Deng combination of gases；Photolithography patterning, using electron beam evaporation or
The membrane deposition methods such as sputtering, successively deposit the multiple layer metal of Ni, Ti, Al, and removing forms source electrode contact 150.
Step S8, drain electrode contact 160 is formed in the lower surface of the n++ type substrate base 10.
It referring again to Figure 16, is protected in SiC substrate front resist coating, and removes n++ type substrate base 10 with diluted HF
The oxide layer at the back side utilizes the membrane deposition methods such as electron beam evaporation or sputtering overleaf deposited metal, the metal layer
It can be the metals such as AlTi, Ni, TiW, AlTi or their combination, drain electrode contact 160 be made, then remove front photoresist.
In 900 DEG C~1100 DEG C of temperature range, nitrogen or argon gas condition annealing source electrode contact 150, drain electrode are connect
Touching 160, forms it into Ohmic contact.The membrane deposition methods such as deposited by electron beam evaporation or sputtering deposit thicker in SiC substrate front
Metal layer forms contact interconnection.
Substrate material used by above specific embodiment is not limited to SiC material, can also include silicon, nitridation
The power electronic semiconductors material such as gallium, gallium oxide, diamond.When using other semiconductor materials as substrate, final institute
Manufactured DMOSFET device and preparation method with low on-resistance and Miller charge should be included in the protection model of the disclosure
Within enclosing.
121 material of gate oxide used by particular embodiments described above is not limited to SiO2, can also be it
He is oxide material such as Al2O3、SixNy(x, y are element ratio) and AlN, AlON, HfO2Contour k dielectric material and they
Combination.
It should be noted that the direction term mentioned in embodiment, for example, "upper", "lower", etc., be only the side with reference to attached drawing
To being not used to limit the protection scope of the disclosure.Through attached drawing, identical element is by same or similar appended drawing reference come table
Show.When may cause understanding of this disclosure and cause to obscure, conventional structure or construction will be omitted.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
It describes in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in guarantor of the invention
Within the scope of shield.
Claims (10)
1. a kind of SiC base DMOSFET device, it is characterised in that: including SiC epitaxial material substrate, have source dopant region, JFET doping
Area, JFET trench oxide, gate electrode contact, source electrode contact are contacted with drain electrode, and the SiC epitaxial material substrate includes n+
+ type substrate base, n+ type buffer layer and n-type drift layer, the n+ type buffer layer are located at the upper table of the n++ type substrate base
Face, the n-type drift layer are located at the upper surface of the n+ type buffer layer, and described to have source dopant region include the area p well, n++ type
Source region and p++ type base area, the n++ type source region are built in the area the p well, and p++ type base area is built in the n++ type
It source region and is connect with the area the p well；
A plurality of p well area's periodic arrangements are located at adjacent in the upper surface of the n- drift layer, the JFET doped region
Between the area the p well, the JFET doped region offers first groove, and the JFET trench oxide is covered in described
One groove, the JFET doped region and the area the p well, the gate electrode contact are located at the JFET trench oxide
Upper surface, adjacent gate electrode contact are equipped with gap, and the insulating material layer is located at the upper surface of gate electrode contact
And the filling gap, the source electrode contact are located at the upper surface of the insulating material layer and penetrate and the n++ type downwards
Source region and the connection of p++ type base area, the drain electrode contact are located at the lower surface of the n++ type substrate base.
2. a kind of SiC base DMOSFET device as described in claim 1, it is characterised in that: the gate electrode contact offers the
Two grooves, the second groove are located at the first groove, and the insulating material layer fills the second groove.
3. a kind of SiC base DMOSFET device as described in claim 1, it is characterised in that: the gate electrode contact is polysilicon
Gate electrode contact, the source electrode contact are that metal source contacts, and the drain electrode contact is that metal leakage pole contacts.
4. a kind of preparation method of SiC base DMOSFET device, it is characterised in that: include:
Step S1, SiC epitaxial material substrate is cleaned；
Step S2, injecting in the upper surface autoregistration of the SiC epitaxial material substrate a plurality of has source doping in periodic arrangement
Area；
Step S3, autoregistration between source dopant region described in adjacent injects JFET doped region；
Step S4, the Self-aligned etching first groove in the JFET doped region；
Step S5, JFET groove is formed in the upper surface of the first groove, the JFET doped region and the area the p well
Oxide；
Step S6, gate electrode contact is formed in the upper surface of the JFET trench oxide；
Step S7, insulating material layer is formed in the upper surface of gate electrode contact, it is logical that the insulating material layer offers contact
Hole forms source electrode contact in the upper surface of the insulating material layer, and the source electrode contact has by contact through hole with described
Source dopant region connection；
Step S8, drain electrode contact is formed in the lower surface of the SiC epitaxial material substrate.
5. a kind of preparation method of SiC base DMOSFET device according to claim 4, it is characterised in that: the step S1
In SiC epitaxial material substrate include n++ type substrate base, n+ type buffer layer, n-type drift layer, n+ type buffer layer elder generation shape
The upper surface of n++ type substrate base described in Cheng Yu, the n-type drift layer are re-formed in the upper surface of the n+ type buffer layer；
The step S2 specifically: injected in the upper surface autoregistration of the n-type drift layer a plurality of in the active of periodic arrangement
Doped region；
The step S8 specifically: form drain electrode contact in the lower surface of the n++ type substrate base.
6. a kind of preparation method of SiC base DMOSFET device according to claim 4, it is characterised in that: the step S2
In the source dopant region that has include the area p well, n++ type source region and p++ type base area, the step S2 is further are as follows: first described
A plurality of areas the p well in periodic arrangement are injected in the upper surface autoregistration of SiC epitaxial material substrate, then at the P
The n++ type source region is formed in the area well, and p++ type base area, P++ type base area are formed in the n++ type source region
Also it is connect with the area the p well.
7. a kind of preparation method of SiC base DMOSFET device according to claim 4, it is characterised in that: the step S3
In autoregistration implant operation and the step S2 in autoregistration implant operation be using identical reticle.
8. a kind of preparation method of SiC base DMOSFET device according to claim 4, it is characterised in that: first ditch
The depth of slot is less than or equal to the thickness in the area p well.
9. a kind of preparation method of SiC base DMOSFET device according to claim 4, it is characterised in that: the step S5
Middle formation JFET trench oxide is using film deposition techniques and lithographic technique.
10. a kind of preparation method of SiC base DMOSFET device according to claim 4, it is characterised in that: in the step
Further include step S6-1 after rapid S6, further include step S7-1 after the step S7:
Step S6-1, in the position of the first groove, gate electrode contact is performed etching, forms second groove, it is described
The depth of second groove extends substantially downward to the JFET trench oxide；
Step S7-1, the described insulating material layer also fills up the second groove.
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| CN116646242A (en) * | 2023-06-13 | 2023-08-25 | 山东大学 | Ohmic contact of SiC device and preparation method and application thereof |
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