CN116013989A - With SiO 2 Vertical structure Ga of barrier layer 2 O 3 Transistor and preparation method - Google Patents
With SiO 2 Vertical structure Ga of barrier layer 2 O 3 Transistor and preparation method Download PDFInfo
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Abstract
The invention discloses a silicon dioxide (SiO) containing material 2 Vertical structure Ga of barrier layer 2 O 3 The transistor and the preparation method mainly solve the problem that the existing vertical gallium oxide field effect transistor does not block the leakage structure between the source and the drain, resulting in poor device performance and reliability. The device comprises a drain electrode, a gallium oxide substrate layer, a gallium oxide epitaxial layer, a gate oxide layer and a gate electrode from bottom to top; the inner periphery of the epitaxial layer is provided with SiO 2 The current blocking layer is provided with a vertical heavily doped conductive channel at the center, an n-type conductive layer grown by ALD is arranged above the current blocking layer, and a source electrode is arranged above the n-type conductive layer. The invention is provided with vertical heavy doped conductive channelFor the existing structure, the on-resistance of the device is reduced; and due to the arrangement of SiO at the inner periphery of the epitaxial layer 2 Compared with the existing structure, the blocking layer effectively reduces the electric leakage between the source and the drain of the device, improves the breakdown voltage of the device, and can be used for preparing high-power integrated circuits.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to Ga with a vertical structure 2 O 3 The field effect transistor can be used for manufacturing high-voltage transformer circuit chips, high-speed railway power transmission systems, civil electric vehicle charging modules and the like.
Technical Field
With the development of the fourth generation ultra-wide band gap semiconductor, gallium oxide materials gradually become the focus of new generation semiconductor materials. Gallium oxide materials currently available are in the form of five crystals, α, β, γ, δ and ε, since several other metastable phases are converted to β -Ga when subjected to high temperature processing 2 O 3 Monoclinic beta-Ga 2 O 3 With the best thermal stability, most of research work is done around beta-Ga 2 O 3 And (5) unfolding. beta-Ga 2 O 3 This feature has an ultra-large forbidden band width of 4.85eV, which results in a lower ionization rate and thus higher breakdown field strength, a theoretical calculation limit of about 8MV/cm, about 20 times higher than that of the first generation semiconductor Si, and one to two times higher than that of the third generation semiconductors SiC and GaN. Furthermore, due to beta-Ga 2 O 3 Has higher electron mobility, dielectric constant and critical electric field intensity, and the Baliga quality of the Baliga reaches 3 times of 4H-SiC and 1.5 times of GaN. In addition, beta-Ga 2 O 3 The theoretical value of on-resistance of the material is very low, so that for unipolar devices under the same breakdown voltage condition, the on-loss of the unipolar devices is at least one order of magnitude lower than that of SiC and GaN devices, and the efficiency of the power devices is improved. Therefore, the gallium oxide material has great potential and development prospect in the aspects of research and manufacture of power devices.
Gallium oxide field effect transistors are mainly of two types, namely horizontal structures and vertical structures. As the technology and structure are more mature, gallium oxide field effect transistors are still based on horizontal structures in the current published article. For a field effect transistor with a horizontal structure, if a larger saturation current and a higher breakdown voltage are to be obtained, the size of a channel must be increased, the area of a chip is sacrificed, and new reliability problems are caused by the increase of the total number of defects of a bulk material while the area is increased.
In order to fully exert the advantages of the gallium oxide material in terms of high voltage resistance and high power, the gallium oxide field effect transistor with a vertical structure is better selected, and for a device with a vertical structure, a reverse bias electric field is distributed on a whole body material, so that the reliability problem caused by surface breakdown can be avoided while the electric field bearing area is increased, higher breakdown voltage can be obtained, larger on-current can be easily obtained due to the structural characteristics of the device, and the higher breakdown voltage can be obtained by increasing the thickness of a drift region under the condition that the area of a chip is not sacrificed.
However, because the valence band of the gallium oxide material is too gentle and the acceptor ionization energy is too much influenced, the P-type doping is difficult to realize in the preparation process of the gallium oxide material and the device, and the pn junction cannot be used for effectively blocking the electric leakage between the source and the drain like the traditional vertical structure.
The current vertical gallium oxide field effect transistor has two structures:
the first is a non-planar multi-fin structure used in early operation, which includes, from bottom to top, a drain electrode, a gallium oxide substrate layer, a gallium oxide drift layer, a fin channel, an aluminum oxide gate oxide layer, a silicon dioxide isolation layer, a gate electrode, and a source electrode, as shown in fig. 1. The structure realizes the electrical isolation between the source and the drain by a side wall modulation method, and successfully realizes the basic function of the vertical gallium oxide field effect transistor. However, the corner of the trench gate oxide layer of the fin structure is subjected to strong field stress, so that the reliability of the device is reduced, the breakdown voltage is only 1000V, and the production process of the device is very difficult due to the complex process implementation and high precision requirement of the fin structure.
The second is a gallium oxide field effect transistor with a full ion implantation current blocking layer structure, as shown in fig. 2, the structure comprises a drain electrode, a tin heavy doped gallium oxide substrate layer, a silicon doped gallium oxide drift layer, a magnesium ion implantation current blocking layer, a silicon ion doped gallium oxide channel, a source electrode, an aluminum oxide gate oxide layer and a gate electrode from bottom to top, the structure reduces the production difficulty of the vertical gallium oxide field effect transistor by introducing a planar gate structure, and avoids the problem of strong field stress at the corner of the device, but because the implanted ions are activated by high-temperature annealing in the preparation process of the structural device, the high temperature can lead the introduced electron trap center ions to diffuse, so that non-ideal leakage channels are generated between the source and the drain, thereby generating larger leakage current, the breakdown voltage of the leakage current cannot exceed 300V, and the device performance is quite unstable.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a silicon dioxide (SiO) film 2 Vertical structure Ga of barrier layer 2 O 3 The transistor and the preparation method are used for improving the breakdown voltage of the device, avoiding leakage current generated by thermal diffusion between source and drain, improving the output current of the drain of the transistor and solving the problem of difficult growth process of a high-doped ohmic region.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
1. SiO-containing material 2 Vertical structure Ga of barrier layer 2 O 3 The transistor comprises a gallium oxide substrate layer, a gallium oxide epitaxial layer and a gate oxide layer, wherein a gate electrode is arranged above the gate oxide layer, and the lower surface of the gallium oxide substrate layer is a drain electrode, and is characterized in that:
the epitaxial layer is provided with SiO at the inner periphery 2 The current blocking layer is used for realizing effective electric isolation between the source electrode and the drain electrode, and a vertical heavily doped conductive channel is arranged in the center of the current blocking layer so as to reduce the on-resistance of the device; an n-type conducting layer is arranged above the gallium oxide material to realize the regrowth of the gallium oxide material;
a source electrode is arranged above the n-type conductive layer.
Further, the gallium oxide substrate layer adopts a thickness of 500um-700um and a concentration of 1×10 18 -5×10 18 cm -3 Is highly doped with beta-Ga 2 O 3 A material.
Further, the gallium oxide epitaxial layer adopts a thickness of3um-10um, concentration of 1.5X10 16 -1×10 17 cm -3 Is low doped with beta-Ga 2 O 3 A material.
Further, the transistor is characterized in that: the SiO is 2 The current blocking layer has a thickness of 500nm-1000nm.
Further, the transistor is characterized in that: the n-type conductive layer has a thickness of 5nm-50nm and a concentration of 1×10 17 -5×10 19 cm -3 N-type highly doped GaN or SiC or In 2 O 3 A wide band gap or ultra wide band gap n-type conductive material.
Further, the transistor is characterized in that: the vertical heavily doped conductive channel has a thickness of 1um-10um, a width of 2um-20um, and a concentration of 1×10 17 -5×10 19 cm -3 Is highly doped with beta-Ga 2 O 3 A material.
2. Preparation of SiO-containing material 2 Vertical structure Ga of barrier layer 2 O 3 A method of forming a transistor, comprising the steps of:
1) Washing an epitaxial wafer, namely sequentially putting a homoepitaxial gallium oxide wafer into an acetone solution, an absolute ethanol solution and deionized water, carrying out ultrasonic washing for 5-10 min respectively, and then drying by nitrogen;
2) Photoetching is carried out on the cleaned epitaxial wafer to form a region to be etched, and then the region to be etched is put into a reactive ion etching RIE system, and gallium oxide on the region to be etched of the epitaxial wafer is etched to form a groove structure;
3) Placing the etched gallium oxide epitaxial wafer into an inductively coupled plasma enhanced chemical vapor deposition (ICP-CVD) reaction chamber of an ICP-CVD system, setting the temperature of the reaction chamber to be 80-90 ℃, and depositing SiO with the thickness of 500-1000 nm on the surface of the epitaxial wafer 2 Then the deposited flakes are put into stripping liquid to form SiO through stripping 2 A barrier layer;
4) Depositing an n-type conductive material with the thickness of 10nm-20nm on the surface of the gallium oxide epitaxial wafer by an atomic layer deposition ALD process;
5) Photoetching the deposited epitaxial wafer to form a region to be etched, putting the region into a Reactive Ion Etching (RIE) system, and etching n-type conductive material on the region to be etched of the epitaxial wafer to form an ohmic contact region;
6) Photoetching is carried out on the etched epitaxial wafer to form an area to be ion-implanted, and then n-type conductive ions are implanted into the area through an ion implantation technology;
7) Depositing Al with the thickness of 20nm-50nm on the surface of the gallium oxide epitaxial wafer after ion implantation by an atomic layer deposition ALD process 2 O 3 ；
8) At Al 2 O 3 Etching the source electrode through hole by using a reactive ion etching RIE system to remove Al in the electrode through hole area 2 O 3 ；
9) Photoetching the etched epitaxial wafer again to form a source electrode area, depositing Ti/Au on the source electrode area by an E-Beam evaporation E-Beam system, forming a source electrode by stripping, depositing Ti/Au on the surface of a substrate to form a drain electrode, and forming a source electrode on N 2 Annealing in the environment to form ohmic contact;
10 Photoetching the gallium oxide epitaxial wafer after ohmic contact is formed, and forming a metal oxide film on Al 2 O 3 And forming a grid electrode region on the surface, depositing Ni/Au on the grid electrode region by an E-Beam evaporation E-Beam system, and stripping to form a grid electrode to finish the device manufacture.
Compared with the prior art, the invention has the following advantages:
1. the invention not only ensures that the voltage-resistant capability of the device is not obviously affected, but also improves the output current of the device because the heavily doped vertical conductive channel structure is arranged in the center of the epitaxial layer.
2. The invention is characterized in that SiO is arranged on the upper part of the epitaxial layer 2 High-quality current blocking layer structure realizes the electrical isolation of source and drain regions, and simultaneously due to SiO 2 The high dielectric constant will significantly increase the breakdown voltage of the vertical structure gallium oxide field effect transistor device.
3. The invention is characterized in that SiO is arranged on the upper part of the epitaxial layer 2 High quality current blocking layer structure, compared with the existing ion implantation region implantationThe technology of forming a current blocking layer between the source and the drain by Mg ions or N ions avoids the problem that the subsequent high-temperature process can cause larger leakage current generated by thermal diffusion of the Mg ions or the N ions.
4. According to the invention, the ohmic contact is formed by adopting the n-type conductive material deposited by the atomic layer deposition ALD process, and the ohmic contact is not generated by adopting the ion implantation process, so that the damage of ion implantation to crystal lattices is reduced, the defect density of a semiconductor is reduced, the integrity of the crystal lattices is improved, and the voltage-resistant capability of a device is further improved.
5. The invention is characterized in that SiO is deposited 2 The high doping ohmic region is formed on the current blocking layer by depositing n-type conductive material through atomic layer deposition ALD process, so that SiO is avoided 2 The process of regrowing gallium oxide material on the barrier layer can not be realized.
Drawings
Fig. 1 is a schematic diagram of a conventional gallium oxide field effect transistor with a multi-fin structure.
Fig. 2 is a schematic diagram of a gallium oxide field effect transistor with a conventional full ion implantation current blocking layer structure.
FIG. 3 is a schematic diagram of a SiO-containing material according to the present invention 2 Vertical structure Ga of barrier layer 2 O 3 The transistor structure is schematically shown.
FIG. 4 shows the preparation of SiO-containing particles according to the present invention 2 Vertical structure Ga of barrier layer 2 O 3 The implementation flow diagram of the transistor is shown.
Detailed Description
The invention is provided with SiO in the following with reference to the accompanying drawings 2 Vertical structure Ga of barrier layer 2 O 3 The transistor structure and fabrication process are described in further detail.
Referring to FIG. 3, the present invention has SiO 2 Vertical structure Ga of barrier layer 2 O 3 The transistor includes: drain electrode D, source electrode S, substrate layer 1, drift layer 2, gate oxide layer 3, vertical heavily doped channel 5, siO 2 Layer 4, n-type conductivity material layer 6 and gate source electrode G, wherein:
the substrate layer 1 has a thickness of 500um-700um and a concentration of 1×10 18 -5×10 18 cm -3 Is highly doped with beta-Ga 2 O 3 A material;
the drift layer 2 has a thickness of 3um-10um and a concentration of 1.5X10 16 -1×10 17 cm -3 Is low doped with beta-Ga 2 O 3 A material located above the substrate layer 1;
the gate oxide layer 3 adopts Al with the thickness of 20nm-50nm 2 O 3 A material located above the drift layer 2;
the SiO is 2 The thickness of the layer 4 is 500nm-1000nm, and the layer is positioned inside the etched groove;
the vertical heavily doped channel 5 is formed from beta-Ga 2 O 3 The upper surface of the drift layer 2 extends into the drift region to a thickness of 1um-10um, a width of 2um-20um, and a concentration of 1×10 17 -5×10 19 cm -3 ；
The n-type conductive material layer 6 is positioned on SiO 2 Above layer 4, a thickness of 5nm-50nm is used, at a concentration of 1×10 17 -5×10 19 cm -3 N-type highly doped GaN, siC or In 2 O 3 A material;
the gate electrode G is positioned on the upper part of the gate oxide layer 3;
the source electrode S is positioned on the upper part of the N-type conductive material layer 6;
the drain electrode D is positioned at the N-type high-doped beta-Ga 2 O 3 A lower portion of the substrate layer 1.
Referring to FIG. 4, the present invention prepares a silicon oxide film with SiO 2 Vertical structure Ga of barrier layer 2 O 3 The method of the transistor gives the following three examples:
example 1: manufacture of N-type beta-Ga 2 O 3 The thickness of the substrate layer is 500um and the doping is 1 multiplied by 10 18 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the N-type beta-Ga 2 O 3 The drift layer has a thickness of 3um and a doping of 1.5X10 16 cm -3 ；SiO 2 500nm thick, 2um vertical heavily doped channel width, 1um thick, 1 x 10 doping concentration 17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The n-type conductive material is In 2 O 3 5nm thick, doped 1X 10 17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the Grid electrodeVertical structure Ga with oxide layer thickness of 20nm 2 O 3 And a transistor.
Step 1: cleaning beta-Ga 2 O 3 Epitaxial wafer, as shown in fig. 4 (a).
Washing an epitaxial wafer, namely sequentially placing a homoepitaxial gallium oxide wafer into an acetone solution, an absolute ethanol solution and deionized water, carrying out ultrasonic washing for 5min, and then drying by using nitrogen;
step 2: the trench structure is etched as shown in fig. 4 (b).
And photoetching the cleaned epitaxial wafer to form a region to be etched, putting the region into a reactive ion etching RIE system, and etching the region to be etched of the epitaxial wafer to remove gallium oxide on the region to be etched of the epitaxial wafer to form a groove structure.
The process conditions of the reactive ion etching RIE system are as follows:
reaction chamber pressure: 1500mtorr
Reaction chamber gas: SF (sulfur hexafluoride) 6 、CHF 3 、He
Reaction chamber gas flow rate ratio: SF (sulfur hexafluoride) 6 :CHF 3 :He＝5.5sccm:32sccm:150sccm
An RF radio frequency source: 150W.
Step 3: deposition of SiO 2 As shown in fig. 4 (c).
Placing the etched gallium oxide epitaxial wafer into an ICP-CVD reaction chamber of an inductively coupled plasma enhanced chemical vapor deposition system, and depositing SiO with the thickness of 500nm on the surface of the epitaxial wafer 2 Then the deposited flakes are put into stripping liquid to form SiO through stripping 2 A barrier layer.
The ICP-CVD process conditions of the chemical vapor deposition system are as follows:
reaction chamber temperature: 80 DEG C
Reaction chamber pressure: 500Pa
Reaction chamber gas flow rate: 300sccm
Step 4: an n-type conductive material layer is fabricated as shown in fig. 4 (d).
Depositing n-type conductive material In with thickness of 5nm on the surface of the gallium oxide epitaxial wafer by atomic layer deposition ALD process 2 O 3 The method comprises the steps of carrying out a first treatment on the surface of the After deposition ofPhotoetching is carried out on the epitaxial wafer to form a region to be etched, then the region to be etched is put into a reactive ion etching RIE system, and n-type conductive material on the region to be etched of the epitaxial wafer is etched to form an ohmic contact region material;
the atomic layer deposition ALD process conditions are:
reaction chamber temperature: 200 DEG C
Reaction chamber pressure: 800Pa
Reaction chamber gas: high purity nitrogen
Reaction chamber gas flow rate: 300sccm
The process conditions of the reactive ion etching RIE system are as follows:
reaction chamber pressure: 1500mtorr
Reaction chamber gas: SF (sulfur hexafluoride) 6 、CHF 3 、He
Reaction chamber gas flow rate ratio: SF (sulfur hexafluoride) 6 :CHF 3 :He＝5.5sccm:32sccm:150sccm
An RF radio frequency source: 150W.
Step 5: ion implantation as shown in fig. 4 (e).
Photoetching the etched epitaxial wafer surface to form a vertical conductive channel ion implantation region, and performing Si ion implantation on the ion implantation region twice with the implantation dose of 1×10 14 cm -2 The implantation energy was 10kev, resulting in a doping concentration of 1X 10 17 cm -3 A highly doped region having a depth of 1 um;
placing the epitaxial wafer after ion implantation in N 2 In the environment, the temperature in the annealing furnace is set to 900 ℃ and annealing is carried out for 30 minutes so as to activate the injected ions.
Step 6: a gate dielectric is grown as shown in fig. 4 (f).
Al with the thickness of 20nm is deposited on the surface of the gallium oxide epitaxial wafer through an atomic layer deposition ALD process 2 O 3 Gate dielectric of (a);
the atomic layer deposition ALD process conditions are:
reaction chamber temperature: 200 DEG C
Reaction chamber pressure: 800Pa
Reaction chamber gas: high purity nitrogen
Reaction chamber gas flow rate: 300sccm
Step 7: the source metal region to be evaporated is formed by photolithography as shown in fig. 4 (g) - (h).
At Al 2 O 3 Surface lithography of source electrode vias, as shown in fig. 4 (g);
etching to remove Al in electrode through hole area by using reactive ion etching RIE system 2 O 3 The source metal region to be evaporated is formed as shown in FIG. 4 (h)
The process conditions of the reactive ion etching RIE system are as follows:
reaction chamber pressure: 10-30mTorr
Reaction chamber gas: BCl (binary coded decimal) 3 、Ar
Reaction chamber gas flow rate ratio: BCl (binary coded decimal) 3 :Ar＝20sccm:10sccm
Etching power: 200W.
Step 8: source drain ohmic electrodes were fabricated as shown in fig. 4 (i).
8.1 Photoetching the etched epitaxial wafer again to form a source end electrode area, and depositing Ti/Au with the thickness of 60nm/120nm on the source end electrode area by an E-Beam evaporation E-Beam system;
8.2 Placing the sheet after electron beam evaporation into stripping liquid, and forming a source electrode through stripping;
8.3 Ti/Au with the thickness of 60nm/120nm is deposited on the surface of the substrate to form a drain electrode, and N is used for forming a drain electrode 2 Setting the temperature in the annealing furnace to 475 ℃ in the environment, and annealing for one minute to form ohmic contact, as shown in (i) of fig. 4;
8.4 At Al) 2 O 3 And carrying out photoetching on the surface to form a gate metal region to be evaporated.
Step 9: a gate electrode is fabricated as shown in fig. 4 (j).
And depositing Ni/Au with the thickness of 50nm/100nm in a gate metal area to be evaporated by an electron Beam evaporation E-Beam system, putting the flakes after the electron Beam evaporation into stripping liquid, and forming a gate electrode by stripping to finish the device manufacture.
Example 2: manufacture of N-type beta-Ga 2 O 3 The thickness of the substrate layer is 600um and the doping is 2.5X10 18 cm -3 N-type beta-Ga 2 O 3 The drift layer has a thickness of 7um and is doped to 5×10 16 cm -3 ,SiO 2 750nm thick, 10um wide vertical heavily doped channel, 5um thick, 5 x 10 doped concentration 18 cm -3 The n-type conductive material is In 2 O 3 A thickness of 25nm and a doping of 5X 10 18 cm -3 Has SiO of (2) 2 Vertical structure Ga of barrier layer and vertical heavily doped channel 2 O 3 A field effect transistor.
Step A: cleaning beta-Ga 2 O 3 And (5) an epitaxial wafer.
The specific implementation of this step is the same as step 1 of example 1.
And (B) step (B): and etching the groove structure.
Photoetching the cleaned epitaxial wafer to form a region to be etched, putting the region into a reactive ion etching RIE system, setting the pressure of a reaction chamber to be 1500mtorr, and setting the gas of the reaction chamber to be SF 6 、CHF 3 The ratio of the flow rate of the gas in the reaction chamber is SF 6 :CHF 3 And (3) etching with the depth of 810nm under the process conditions of He=5.5 sccm:32sccm:150sccm and RF source power of 175W to etch gallium oxide on the to-be-etched area of the epitaxial wafer to form a groove structure.
Step C: deposition of SiO 2 。
Placing the etched gallium oxide epitaxial wafer into an inductively coupled plasma enhanced chemical vapor deposition (ICP-CVD) reaction chamber of an ICP-CVD system, setting the temperature of the reaction chamber to be 85 ℃, the pressure of the reaction chamber to be 550Pa, and depositing SiO with the thickness of 750nm on the surface of the epitaxial wafer under the process condition that the gas flow rate of the reaction chamber is 300sccm 2 Then the deposited flakes are put into stripping liquid to form SiO through stripping 2 A barrier layer.
Step D: and manufacturing an n-type conductive material layer.
Adopting atomic layer deposition ALD method, setting reaction chamber temperature as 200 deg.C, reaction chamber pressure as 850Pa, reaction chamber gas as high purity nitrogen gas, reaction chamber gas flow rate as 300sccm, depositing n-type guide with thickness of 25nm on gallium oxide epitaxial wafer surfaceElectric material In 2 O 3 The method comprises the steps of carrying out a first treatment on the surface of the Photoetching the deposited epitaxial wafer to form a region to be etched, putting the region into a reactive ion etching RIE system, setting the pressure of a reaction chamber to be 1500mtorr, and setting the gas of the reaction chamber to be SF 6 、CHF 3 The ratio of the flow rate of the gas in the reaction chamber is SF 6 :CHF 3 Etching n-type conductive material on a region to be etched of the epitaxial wafer under the process conditions that He=5.5 sccm:32sccm:150sccm and RF radio frequency source power is 175W to form ohmic contact region material;
step E: and (5) ion implantation.
Photoetching the etched epitaxial wafer surface to form a vertical conductive channel ion implantation region, and performing Ge ion implantation twice on the ion implantation region, wherein the implantation dosage is 3 multiplied by 10 14 cm -2 The implantation energy was 10kev, resulting in a doping concentration of 5X 10 18 cm -3 A highly doped region having a depth of 5 um;
placing the epitaxial wafer after ion implantation in N 2 In the environment, the temperature in the annealing furnace is set to 950 ℃ and annealing is carried out for 30 minutes to activate the injected ions.
Step F: and growing a gate dielectric.
Adopting atomic layer deposition ALD method, setting the temperature of a reaction chamber to 220 ℃, the pressure of the reaction chamber to 850Pa, the gas of the reaction chamber to be high-purity nitrogen, the gas flow rate of the reaction chamber to be 300sccm, and depositing Al with the thickness of 35nm on the surface of the gallium oxide epitaxial wafer 2 O 3 Is formed on the substrate.
And G, photoetching to form a source metal region to be evaporated.
At Al 2 O 3 The surface photoetching source end electrode through hole is provided with a reaction chamber pressure of 20mTorr of a reactive ion etching RIE system, and the gas of the reaction chamber is BCl 3 Ar, reaction chamber gas flow rate ratio is BCl 3 Ar=20sccm:10sccm, the etching power is 300W, and Al in the electrode through hole area is etched and removed 2 O 3 And forming a source metal region to be evaporated.
And H, manufacturing source-drain ohmic electrodes.
H.1 Photoetching the etched epitaxial wafer again to form a source end electrode area, and depositing Ti/Au with the thickness of 70nm/130nm on the source end electrode area by an E-Beam evaporation E-Beam system;
h.2 Placing the sheet after electron beam evaporation into stripping liquid, and forming a source electrode through stripping;
h.3 Ti/Au with the thickness of 70nm/130nm is deposited on the surface of the substrate to form a drain electrode, and N is used for forming a drain electrode 2 Setting the temperature in an annealing furnace to 475 ℃ in the environment, and annealing for one minute to form ohmic contact;
h.4 At Al) 2 O 3 And carrying out photoetching on the surface to form a gate metal region to be evaporated.
And step I, manufacturing a gate electrode.
And depositing Ni/Au with the thickness of 55nm/110nm in a gate metal area to be evaporated by an electron Beam evaporation E-Beam system, putting the flakes after the electron Beam evaporation into stripping liquid, and forming a gate electrode by stripping to finish the device manufacture.
Example 3 preparation of N-type beta-Ga 2 O 3 The thickness of the substrate layer is 700um and the doping is 5 multiplied by 10 18 cm -3 N-type beta-Ga 2 O 3 The drift layer has a thickness of 10um and a doping of 1×10 17 cm -3 ,SiO 2 1000nm in thickness, 20um in width, 10um in thickness and 5×10 in doping concentration 19 cm -3 The n-type conductive material is In 2 O 3 A thickness of 50nm and a doping of 5X 10 19 cm -3 Has SiO of (2) 2 Vertical structure Ga of barrier layer and vertical heavily doped channel 2 O 3 A field effect transistor.
Step one: cleaning beta-Ga 2 O 3 And (5) an epitaxial wafer.
The specific implementation of this step is the same as step 1 of example 1.
Step two: and etching the groove structure.
Photoetching the cleaned epitaxial wafer to form a region to be etched, putting the region into a reactive ion etching RIE system, setting the pressure of a reaction chamber to be 1500mtorr, and setting the gas of the reaction chamber to be SF 6 、CHF 3 He, reaction chamber gasBulk flow rate ratio SF 6 :CHF 3 And etching the epitaxial wafer at a depth of 1010nm under the process conditions of He=5.5 sccm:32sccm:150sccm and RF radio frequency source power of 200W to etch gallium oxide on the region to be etched of the epitaxial wafer, thereby forming a groove structure.
Step three: deposition of SiO 2 。
Placing the etched gallium oxide epitaxial wafer into an inductively coupled plasma enhanced chemical vapor deposition (ICP-CVD) reaction chamber of an ICP-CVD system, and depositing SiO with the thickness of 1000nm on the surface of the epitaxial wafer under the process conditions that the temperature of the reaction chamber is 90 ℃, the pressure of the reaction chamber is 600Pa and the gas flow rate of the reaction chamber is 300sccm 2 Then the deposited flakes are put into stripping liquid to form SiO through stripping 2 A barrier layer.
Step four: and manufacturing an n-type conductive material layer.
An atomic layer deposition ALD method is used for depositing an n-type conductive material In with the thickness of 50nm on the surface of a gallium oxide epitaxial wafer under the process conditions that the temperature of a reaction chamber is 200 ℃, the pressure of the reaction chamber is 900Pa, the gas of the reaction chamber is high-purity nitrogen and the flow rate of the gas of the reaction chamber is 300sccm 2 O 3 The method comprises the steps of carrying out a first treatment on the surface of the Photoetching the deposited epitaxial wafer to form a region to be etched, putting the region into a reactive ion etching RIE system, setting the pressure of a reaction chamber to be 1500mtorr, and setting the gas of the reaction chamber to be SF 6 、CHF 3 The ratio of the flow rate of the gas in the reaction chamber is SF 6 :CHF 3 Etching n-type conductive material on a region to be etched of the epitaxial wafer under the process conditions that He=5.5 sccm:32sccm:150sccm and RF radio frequency source power is 200W to form ohmic contact region material;
and step five, ion implantation.
Photoetching the etched epitaxial wafer surface to form a vertical conductive channel ion implantation region, and carrying out Sn ion implantation twice on the ion implantation region, wherein the implantation dosage is 5 multiplied by 10 14 cm -2 The implantation energy was 10kev, resulting in a doping concentration of 5X 10 18 cm -3 A highly doped region having a depth of 5 um;
placing the epitaxial wafer after ion implantation in N 2 Setting the internal temperature of the annealing furnace in the environmentThe degree was 950 ℃ and annealing was performed for 30 minutes to activate the implanted ions.
And step six, growing a gate dielectric.
Adopting atomic layer deposition ALD method, depositing Al with thickness of 50nm on the surface of gallium oxide epitaxial wafer under the process condition that the temperature of a reaction chamber is 240 ℃, the pressure of the reaction chamber is 900Pa, the gas of the reaction chamber is high-purity nitrogen and the flow rate of the gas of the reaction chamber is 300sccm 2 O 3 Gate dielectric of (a);
and seventhly, photoetching to form a source metal region to be evaporated.
At Al 2 O 3 The surface photoetching source end electrode through hole is provided with a reaction chamber pressure of 20mTorr of a reactive ion etching RIE system, and the gas of the reaction chamber is BCl 3 Ar, reaction chamber gas flow rate ratio is BCl 3 Ar=20sccm:10sccm, the etching power is 400W, and Al in the electrode through hole area is etched and removed 2 O 3 And forming a source metal region to be evaporated.
And step eight, manufacturing source-drain ohmic electrodes.
Photoetching the etched epitaxial wafer again to form a source end electrode area, and depositing Ti/Au with the thickness of 80nm/140nm in the source end electrode area by an electron Beam evaporation E-Beam system; then the film after the electron beam evaporation is put into stripping liquid, and a source electrode is formed through stripping; then Ti/Au with the thickness of 80nm/140nm is deposited on the surface of the substrate to form a drain electrode, and N is used for forming a drain electrode 2 Setting the temperature in an annealing furnace to 475 ℃ in the environment, and annealing for one minute to form ohmic contact; finally at Al 2 O 3 And carrying out photoetching on the surface to form a gate metal region to be evaporated.
And step nine, manufacturing a gate electrode.
And depositing Ni/Au with the thickness of 60nm/120nm in a gate metal area to be evaporated by an electron Beam evaporation E-Beam system, putting the flakes after the electron Beam evaporation into stripping liquid, and forming a gate electrode by stripping to finish the device manufacture.
The foregoing is only three embodiments of the invention and is not intended to limit the invention in any way, but it will be apparent to those skilled in the art that various modifications and changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (13)
1. SiO-containing material 2 Vertical structure Ga of barrier layer 2 O 3 The transistor comprises a gallium oxide substrate layer (1), a gallium oxide epitaxial layer (2) and a gate oxide layer (3), wherein a gate electrode (G) is arranged above the gate oxide layer (3), and the lower surface of the gallium oxide substrate layer (1) is provided with a drain electrode (D), and is characterized in that:
the epitaxial layer (2) is provided with SiO on the inner periphery 2 A current blocking layer (4) for realizing effective electric isolation between source and drain, wherein a vertical heavily doped conductive channel (5) is arranged at the center of the current blocking layer so as to reduce the on-resistance of the device; an n-type conductive layer (6) is arranged above the silicon substrate to realize the regrowth of n-type conductive materials;
a source electrode (S) is provided above the n-type conductive layer (6).
2. A transistor according to claim 1, characterized in that: the gallium oxide substrate layer (1) adopts the thickness of 500um-700um and the concentration of 1 multiplied by 10 18 -5×10 18 cm -3 Is highly doped with beta-Ga 2 O 3 A material.
3. A transistor according to claim 1, characterized in that: the gallium oxide epitaxial layer (2) has a thickness of 3um-10um and a concentration of 1.5X10 16 -1×10 17 cm -3 Is low doped with beta-Ga 2 O 3 A material.
4. A transistor according to claim 1, characterized in that: the SiO is 2 A current blocking layer (4) having a thickness of 500nm to 1000nm.
5. A transistor according to claim 1, characterized in that: the n-type conductive layer (6) has a thickness of 5nm-50nm and a concentration of 1×10 17 -5×10 19 cm -3 N-type highly doped GaN or SiC or In 2 O 3 A wide band gap or ultra wide band gap n-type conductive material.
6. A transistor according to claim 1, characterized in that: the vertical heavy doped conductive channel (5) adopts the thickness of 1um-10um, the width of 2um-20um and the concentration of 1 multiplied by 10 17 -5×10 19 cm -3 Is highly doped with beta-Ga 2 O 3 A material.
7. Preparation of SiO-containing material 2 Vertical structure Ga of barrier layer 2 O 3 A method of forming a transistor, comprising the steps of:
1) Washing an epitaxial wafer, namely sequentially putting a homoepitaxial gallium oxide wafer into an acetone solution, an absolute ethanol solution and deionized water, carrying out ultrasonic washing for 5-10 min respectively, and then drying by nitrogen;
2) Photoetching is carried out on the cleaned epitaxial wafer to form a region to be etched, and then the region to be etched is put into a reactive ion etching RIE system, and gallium oxide on the region to be etched of the epitaxial wafer is etched to form a groove structure;
3) Placing the etched gallium oxide epitaxial wafer into an inductively coupled plasma enhanced chemical vapor deposition (ICP-CVD) reaction chamber of an ICP-CVD system, setting the temperature of the reaction chamber to be 80-90 ℃, and depositing SiO with the thickness of 500-1000 nm on the surface of the epitaxial wafer 2 Then the deposited flakes are put into stripping liquid to form SiO through stripping 2 A barrier layer;
4) Depositing an n-type conductive material with the thickness of 10nm-20nm on the surface of the gallium oxide epitaxial wafer by an atomic layer deposition ALD process;
5) Photoetching the deposited epitaxial wafer to form a region to be etched, putting the region into a Reactive Ion Etching (RIE) system, and etching n-type conductive material on the region to be etched of the epitaxial wafer to form an ohmic contact region;
6) Photoetching is carried out on the etched epitaxial wafer to form an area to be ion-implanted, and then n-type conductive ions are implanted into the area through an ion implantation technology;
7) Depositing Al with the thickness of 20nm-50nm on the surface of the gallium oxide epitaxial wafer after ion implantation by an atomic layer deposition ALD process 2 O 3 ；
8) At Al 2 O 3 Etching the source electrode through hole by using a reactive ion etching RIE system to remove Al in the electrode through hole area 2 O 3 ；
9) Photoetching the etched epitaxial wafer again to form a source electrode area, depositing Ti/Au on the source electrode area by an E-Beam evaporation E-Beam system, forming a source electrode by stripping, depositing Ti/Au on the surface of a substrate to form a drain electrode, and forming a source electrode on N 2 Annealing in the environment to form ohmic contact;
10 Photoetching the gallium oxide epitaxial wafer after ohmic contact is formed, and forming a metal oxide film on Al 2 O 3 And forming a grid electrode region on the surface, depositing Ni/Au on the grid electrode region by an E-Beam evaporation E-Beam system, and stripping to form a grid electrode to finish the device manufacture.
8. The method of claim 7, wherein the reactive ion etching RIE process is used in step 2) under the following process conditions:
reaction chamber pressure: 1500-2000mtorr
Reaction chamber gas: SF (sulfur hexafluoride) 6 、CHF 3 、He
Reaction chamber gas flow rate ratio: SF (sulfur hexafluoride) 6 :CHF 3 :He＝5.5sccm:32sccm:150sccm
An RF radio frequency source: 150-300W.
9. The method of claim 7 wherein the n-type material is deposited in step 4) using an atomic layer deposition ALD process under the following process conditions:
reaction chamber pressure: 800-900Pa
Reaction chamber gas: high purity nitrogen
Reaction chamber gas flow rate: 300sccm.
10. The method of claim 7, wherein step 6) The ion implantation is performed in the ion implantation region by implanting a dose of 1e14cm on the epitaxial wafer -2 -5e14cm -2 One of the ions Si, ge, sn, F, cl having an energy of 10keV is formed to have a doping concentration of 1e19cm -3 -5e19cm -3 And implanting a highly doped region with a depth of 1-10 um.
11. The method of claim 7, wherein the step 7) is performed by atomic layer deposition ALD to deposit Al 2 O 3 The process conditions of the molding material are as follows:
reaction chamber pressure: 800-900Pa
Reaction chamber gas: high purity nitrogen
Reaction chamber gas flow rate: 300sccm.
12. The method of claim 7, wherein the etching of Al in step 8) is performed by a reactive ion etching RIE process 2 O 3 The process conditions are as follows:
reaction chamber pressure: 10-30mTorr
Reaction chamber gas: BCl (binary coded decimal) 3 、Ar
Reaction chamber gas flow rate ratio: BCl (binary coded decimal) 3 :Ar＝20sccm:10sccm
Etching power: 200-400W.
13. The method of claim 7, wherein:
the Ti/Au deposited in the step 9) has the thickness of 60nm/120nm-80nm/140nm;
the thickness of Ni/Au deposited in the step 10) is 50nm/100nm-60nm/120nm.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117276352A (en) * | 2023-11-23 | 2023-12-22 | 三峡智能工程有限公司 | Transistor structure, preparation method thereof, recording medium and system |
| CN118431270A (en) * | 2024-07-01 | 2024-08-02 | 深圳市港祥辉电子有限公司 | Field-stop gallium oxide IGBT device and preparation method thereof |
| CN118486735A (en) * | 2024-07-10 | 2024-08-13 | 深圳市港祥辉电子有限公司 | Enhanced planar gate gallium oxide VDMOS device and preparation method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117276352A (en) * | 2023-11-23 | 2023-12-22 | 三峡智能工程有限公司 | Transistor structure, preparation method thereof, recording medium and system |
| CN117276352B (en) * | 2023-11-23 | 2024-02-06 | 三峡智能工程有限公司 | Transistor structure, preparation method thereof, recording medium and system |
| CN118431270A (en) * | 2024-07-01 | 2024-08-02 | 深圳市港祥辉电子有限公司 | Field-stop gallium oxide IGBT device and preparation method thereof |
| CN118486735A (en) * | 2024-07-10 | 2024-08-13 | 深圳市港祥辉电子有限公司 | Enhanced planar gate gallium oxide VDMOS device and preparation method thereof |
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