CN116013989A - With SiO 2 Vertical structure Ga of barrier layer 2 O 3 Transistor and preparation method - Google Patents

Abstract

The invention discloses a silicon dioxide (SiO) containing material ₂ Vertical structure Ga of barrier layer ₂ O ₃ The transistor and the preparation method mainly solve the problem that the existing vertical gallium oxide field effect transistor does not block the leakage structure between the source and the drain, resulting in poor device performance and reliability. The device comprises a drain electrode, a gallium oxide substrate layer, a gallium oxide epitaxial layer, a gate oxide layer and a gate electrode from bottom to top; the inner periphery of the epitaxial layer is provided with SiO ₂ The current blocking layer is provided with a vertical heavily doped conductive channel at the center, an n-type conductive layer grown by ALD is arranged above the current blocking layer, and a source electrode is arranged above the n-type conductive layer. The invention is provided with vertical heavy doped conductive channelFor the existing structure, the on-resistance of the device is reduced; and due to the arrangement of SiO at the inner periphery of the epitaxial layer ₂ Compared with the existing structure, the blocking layer effectively reduces the electric leakage between the source and the drain of the device, improves the breakdown voltage of the device, and can be used for preparing high-power integrated circuits.

Description

Vertical structure Ga2O3 transistor with SiO2 barrier layer and its preparation method

technical field

The invention belongs to the technical field of microelectronics, and in particular relates to a Ga ₂ O ₃ field effect transistor with a vertical structure, which can be used for making high-voltage circuit transformer circuit chips, high-speed railway power transmission systems, and charging modules for civilian electric vehicles.

technical background

With the development of the fourth-generation ultra-wide bandgap semiconductors, gallium oxide materials have gradually become the focus of the new generation of semiconductor materials. At present, there are five crystal forms of gallium oxide materials that can be prepared: α, β, γ, δ, and ε. Since several other metastable phases will be converted into β-Ga ₂ O ₃ during high-temperature processing, the monoclinic β -Ga ₂ O ₃ has the best thermal stability, and most of the current research work is carried out around β-Ga ₂ O ₃ . β-Ga ₂ O ₃ has a large forbidden band width of 4.85eV. This feature makes its ionization rate low, so the breakdown field strength is high. The theoretical calculation limit is about 8MV/cm, which exceeds the first-generation semiconductor Si About 20 times, the third generation semiconductor SiC and GaN one to two times. In addition, due to the high electron mobility, dielectric constant and critical electric field strength of β-Ga ₂ O ₃ , its Baliga quality is 3 times that of 4H-SiC and 1.5 times that of GaN. In addition, the theoretical value of on-resistance of β-Ga ₂ O ₃ material is very low, so for unipolar devices under the same breakdown voltage condition, its conduction loss is at least an order of magnitude lower than that of SiC and GaN devices, which is conducive to improving power device s efficiency. Therefore, gallium oxide materials have great potential and development prospects in the research and manufacture of power devices.

Gallium oxide field effect transistors mainly have two types: horizontal structure and vertical structure. Due to the more mature process and structure, in the currently published articles, the gallium oxide field effect transistor is still dominated by a horizontal structure. For horizontal field effect transistors, if you want to obtain a larger saturation current and a higher breakdown voltage, you must increase the size of the channel, thereby sacrificing the chip area, and at the same time increasing the area due to bulk material defects The increase in the total number brings new reliability problems.

In order to give full play to the advantages of gallium oxide materials in terms of high voltage resistance and high power, vertical structure gallium oxide field effect transistors are a better choice. For vertical structure devices, the reverse bias electric field is distributed on the entire bulk material, increasing the The large electric field bearing area can not only avoid the reliability problems caused by the surface breakdown, but also obtain a higher breakdown voltage, and because of its structural characteristics, it is easy to obtain a larger conduction current, and without In the case of sacrificing more chip area, a higher breakdown voltage can be obtained by increasing the thickness of the drift region.

However, due to the flat valence band of gallium oxide materials and the influence of excessive principal ionization energy, it is difficult to achieve p-type doping in the preparation process of gallium oxide materials and devices, and it is impossible to use pn junctions like traditional vertical structures to The leakage between source and drain is effectively blocked.

At present, there are two structures of vertical gallium oxide field effect transistors:

The first is the non-planar multi-fin structure used in early work, as shown in Figure 1, the structure includes drain electrode, gallium oxide substrate layer, gallium oxide drift layer, fin channel, oxide oxide from bottom to top. Aluminum gate oxide layer, silicon dioxide isolation layer, gate electrode and source electrode. The structure realizes the electrical isolation between the source and the drain through the method of sidewall modulation, and successfully realizes the basic function of the vertical gallium oxide field effect transistor. However, the corners of the trench gate oxide layer of the fin structure will be subject to strong field stress, which will reduce the reliability of the device, and the breakdown voltage is only 1000V, and due to the complex process and high precision requirements of the fin structure, the production of the device The process is very difficult.

The second type is a gallium oxide field effect transistor with a full ion implantation current blocking layer structure, as shown in Figure 2, the structure includes a drain electrode, a heavily tin-doped gallium oxide substrate layer, a silicon-doped gallium oxide drift Layer, magnesium ion implantation current blocking layer, silicon ion doped gallium oxide channel, source electrode, aluminum oxide gate oxide layer and gate electrode, this structure reduces the production difficulty of vertical gallium oxide field effect transistors by introducing a planar gate structure, It also avoids the problem of strong field stress at the corner of the device, but due to the high temperature annealing required to activate the implanted ions during the preparation of the device, the high temperature will cause the introduced electron trap center ions to diffuse, resulting in non-ideal between the source and drain. Leakage channel, resulting in a large leakage current, the breakdown voltage can not exceed 300V, the performance of the device is very unstable.

Contents of the invention

The purpose of the present invention is to address the above-mentioned deficiencies in the prior art, and propose a vertical _Ga2O3 transistor with a _SiO2 barrier layer and its preparation method, so as to improve the breakdown voltage of the device and avoid thermal diffusion between _the source and drain. Leakage current, increase transistor drain output current, and solve the difficult problem of high-doped ohmic region growth process.

To achieve the above object, the technical scheme of the present invention is as follows:

1. A vertical structure Ga ₂ O ₃ transistor with SiO barrier layer, _comprising a gallium oxide substrate layer, a gallium oxide epitaxial layer, a gate oxide layer, a gate electrode is arranged above the gate oxide layer, and the gallium oxide substrate layer lower surface is a leakage current Pole, characterized by:

The epitaxial layer is provided with a _SiO2 current blocking layer on its inner periphery to achieve effective electrical isolation between source and drain, and a vertical heavily doped conductive channel is provided in the center to reduce the on-resistance of the device; above it is provided with an n-type Conductive layer to enable regrowth of gallium oxide material;

A source electrode is arranged above the n-type conductive layer.

Further, the gallium oxide substrate layer is made of N-type highly doped β-Ga ₂ O ₃ material with a thickness of 500um-700um and a concentration of 1×10 ¹⁸ -5×10 ¹⁸ cm ^-3 .

Further, the gallium oxide epitaxial layer is made of an N-type low-doped β-Ga ₂ O ₃ material with a thickness of 3um-10um and a concentration of 1.5×10 ¹⁶ -1×10 ¹⁷ cm ^-3 .

Further, the transistor is characterized in that: the SiO ₂ current blocking layer has a thickness of 500nm-1000nm.

Further, the transistor is characterized in ^that : the n-type conductive layer is made of N-type highly ^doped GaN ^or SiC or In ₂ O ₃ wide or ultra-wide bandgap n-type conductive material.

Further, the transistor is characterized in that: the vertical heavily doped conductive channel adopts an N-type high-density channel with a thickness of 1um-10um, a width of 2um-20um, and a concentration of 1×10 ¹⁷ -5×10 ¹⁹ cm ^-3 Doped β- _{Ga2O3 material} .

2. A method for preparing a vertical structure Ga ₂ O ₃ transistor with SiO ₂ barrier layer, characterized in that, comprising the following steps:

1) Cleaning the epitaxial wafer, that is, putting the homoepitaxial gallium oxide wafer into acetone solution, absolute ethanol solution and deionized water in sequence for ultrasonic cleaning for 5min-10min, and then blowing dry with nitrogen;

2) Perform photolithography on the cleaned epitaxial wafer to form the area to be etched, and then put it into the reactive ion etching RIE system to etch away the gallium oxide on the area to be etched on the epitaxial wafer to form a trench structure;

3) Put the etched gallium oxide epitaxial wafer into the ICP-CVD reaction chamber of the inductively coupled plasma enhanced chemical vapor deposition system, set the temperature of the reaction chamber at 80°C-90°C, and deposit a thickness of 500nm- 1000nm SiO ₂ , and then put the deposited sheet into the stripping solution to form a SiO ₂ barrier layer by stripping;

4) Deposit an n-type conductive material with a thickness of 10nm-20nm on the surface of the gallium oxide epitaxial wafer by atomic layer deposition ALD process;

5) Perform photolithography on the deposited epitaxial wafer to form the area to be etched, and then put it into the reactive ion etching RIE system to etch away the n-type conductive material on the area to be etched on the epitaxial wafer to form an ohmic contact area;

6) Perform photolithography on the etched epitaxial wafer to form a region to be ion implanted, and then implant n-type conductive ions in this region by ion implantation technology;

7) Depositing Al ₂ O ₃ with a thickness of 20nm-50nm on the surface of the gallium oxide epitaxial wafer after ion implantation by atomic layer deposition ALD process;

8) Lithographically etch the through hole of the source end electrode on the surface of Al ₂ O ₃ , and use the reactive ion etching RIE system to etch and remove the Al ₂ O ₃ in the area of the electrode through hole;

9) The etched epitaxial wafer is photolithographically formed again to form the source electrode area, and Ti/Au is first deposited on the source electrode area by electron beam evaporation E-Beam system, and the source electrode is formed by stripping, and then the substrate Deposit Ti/Au on the surface to form a drain terminal electrode, and anneal in _N2 environment to form an ohmic contact;

10) Perform photolithography on the gallium oxide epitaxial wafer after the ohmic contact is formed, form a gate region on the surface of Al ₂ O ₃ , and then deposit Ni/Au on the gate region by electron beam evaporation E-Beam system, and form a gate region by lift-off Electrode, complete device fabrication.

Compared with the prior art, the present invention has the following advantages:

1. Since the present invention is provided with a heavily doped vertical conductive channel structure in the center of the epitaxial layer, it not only ensures that the withstand voltage capability of the device is not significantly affected, but also improves the output current of the device.

2. Since the present invention is provided with a _SiO2 high-quality current blocking layer structure on the upper part of the epitaxial layer, the electrical isolation of the source and drain regions is realized, and at the same time, due to the high dielectric constant of _SiO2 , the field effect of the vertical structure gallium oxide will be significantly improved Transistor device breakdown voltage.

3. The present invention is owing to be provided with _SiO on epitaxial layer top The high-quality electric current blocking layer structure, compares existing ion implantation region implantation Mg ion or the technology of N ion forming electric current blocking layer between source and drain, has avoided in follow-up The high temperature process will cause the problem of large leakage current generated by the thermal diffusion of Mg ions or N ions.

4. The present invention forms the ohmic contact due to the n-type conductive material deposited by the atomic layer deposition (ALD) process, and does not use the ion implantation process to produce the ohmic contact, thereby reducing the damage of the ion implantation to the crystal lattice and making the semiconductor defect density Reduced, the integrity of the lattice is improved, and then the withstand voltage capability of the device is improved.

5. In the present invention, due to depositing n-type conductive material by atomic layer deposition (ALD) process on the deposited _SiO2 current blocking layer to form a highly doped ohmic region, it is avoided that the re-growth gallium oxide material process cannot be realized on the _SiO2 blocking layer The problem.

Description of drawings

FIG. 1 is a schematic diagram of a conventional gallium oxide field effect transistor with a multi-fin structure.

FIG. 2 is a schematic structural diagram of a gallium oxide field effect transistor with an existing full ion implantation current blocking layer structure.

FIG. 3 is a schematic structural diagram of a Ga ₂ O ₃ transistor with a vertical structure having a SiO ₂ barrier layer according to the present invention.

Fig. 4 is a schematic flow chart of the present invention for preparing a vertical Ga ₂ O ₃ transistor with a SiO ₂ barrier layer.

Detailed ways

The structure and preparation process of the vertical structure Ga ₂ O ₃ transistor with SiO ₂ barrier layer of the present invention will be further described in detail below with reference to the accompanying drawings.

Referring to Fig. 3, _the vertical structure _Ga2O3 transistor with _SiO2 barrier layer of the present invention includes: drain electrode D, source electrode S, substrate layer 1, drift layer 2, gate oxide layer 3, vertical heavily doped channel 5, SiO ₂ layer 4, n-type conductive material layer 6 and gate-source electrode G, wherein:

The substrate layer 1 is made of an N-type highly doped β-Ga ₂ O ₃ material with a thickness of 500um-700um and a concentration of 1×10 ¹⁸ -5×10 ¹⁸ cm ^-3 ;

The drift layer 2 is made of an N-type low-doped β-Ga ₂ O ₃ material with a thickness of 3um-10um and a concentration of 1.5×10 ¹⁶ -1×10 ¹⁷ cm ^-3 , which is located on the substrate layer 1;

The gate oxide layer 3 is made of Al ₂ O ₃ material with a thickness of 20nm-50nm, and is located above the drift layer 2;

The thickness of the SiO ₂ layer 4 is 500nm-1000nm, which is located inside the etched trench;

The vertical heavily doped channel 5 penetrates from the upper surface of the β-Ga ₂ O ₃ drift layer 2 to the inside of the drift region, with a thickness of 1um-10um, a width of 2um-20um, and a concentration of 1×10 ¹⁷ -5×10 ^{19 cm- 3} ;

The n-type conductive material layer 6 is located above the SiO ₂ layer 4, using N-type highly doped GaN, SiC or In ₂ O with a thickness of 5nm-50nm and a concentration of 1×10 ¹⁷ -5×10 ¹⁹ cm ^-3 ₃ materials;

The gate electrode G is located on the top of the gate oxide layer 3;

The source electrode S is located on the upper part of the N-type conductive material layer 6;

The drain electrode D is located under the N-type highly doped β-Ga ₂ O ₃ substrate layer 1 .

Referring to FIG. 4, the method for preparing a _Ga2O3 transistor with a vertical structure having _{a SiO2} barrier layer according to the present invention provides the following three examples:

Example 1: Making an N-type β-Ga ₂ O ₃ substrate layer with a thickness of 500um and a doping of 1×10 ¹⁸ cm ^-3 ; an N-type β-Ga ₂ O ₃ drift layer with a thickness of 3um and a doping of 1.5×10 ¹⁶ cm ^-3 ; the thickness of SiO ₂ is 500nm, the vertical heavily doped channel width is 2um, the thickness is 1um, and the doping concentration is 1×10 ¹⁷ cm ^-3 ; the n-type conductive material is In ₂ O ₃ , the thickness is 5nm, The doping is 1×10 ¹⁷ cm ^-3 ; the thickness of the gate oxide layer is 20nm and the vertical structure Ga ₂ O ₃ transistor.

Step 1: cleaning the β-Ga ₂ O ₃ epitaxial wafer, as shown in Figure 4(a).

Clean the epitaxial wafer, that is, put the homoepitaxial gallium oxide wafer into acetone solution, absolute ethanol solution and deionized water in sequence for ultrasonic cleaning for 5 minutes, and then dry it with nitrogen;

Step 2: Etching the trench structure, as shown in Figure 4(b).

Perform photolithography on the cleaned epitaxial wafer to form the area to be etched, and then put it into the reactive ion etching RIE system for etching with a depth of 510nm to etch away the oxidation on the area to be etched on the epitaxial wafer Gallium, forming a trench structure.

Reactive ion etching RIE system process conditions are:

Reaction chamber pressure: 1500mtorr

Reactor gas: SF ₆ , CHF ₃ , He

Reaction chamber gas flow rate ratio: SF ₆ :CHF ₃ :He=5.5sccm:32sccm:150sccm

RF radio frequency source: 150W.

Step 3: Deposit SiO ₂ , as shown in Figure 4(c).

Put the etched gallium oxide epitaxial wafer into the ICP-CVD reaction chamber of the inductively coupled plasma enhanced chemical vapor deposition system, deposit SiO ₂ with a thickness of 500nm on the surface of the epitaxial wafer, and then put the deposited wafer into the stripping solution, the _SiO2 barrier layer was formed by exfoliation.

Chemical vapor deposition system ICP-CVD process conditions are:

Reaction chamber temperature: 80°C

Reaction chamber pressure: 500Pa

Reaction chamber gas flow rate: 300sccm

Step 4: Fabricate an n-type conductive material layer, as shown in Figure 4(d).

By atomic layer deposition ALD process, deposit n-type conductive material In ₂ O ₃ with a thickness of 5nm on the surface of the gallium oxide epitaxial wafer; perform photolithography on the deposited epitaxial wafer to form the area to be etched, and then place it Enter the reactive ion etching RIE system to etch away the n-type conductive material on the area to be etched of the epitaxial wafer to form the material of the ohmic contact area;

Atomic layer deposition ALD process conditions are:

Reaction chamber temperature: 200°C

Reaction chamber pressure: 800Pa

Reaction chamber gas: high-purity nitrogen

Reaction chamber gas flow rate: 300sccm

Reactive ion etching RIE system process conditions are:

Reaction chamber pressure: 1500mtorr

Reactor gas: SF ₆ , CHF ₃ , He

Reaction chamber gas flow rate ratio: SF ₆ :CHF ₃ :He=5.5sccm:32sccm:150sccm

RF radio frequency source: 150W.

Step 5: Ion implantation, as shown in Figure 4(e).

Perform photolithography on the surface of the etched epitaxial wafer to form a vertical conductive channel ion implantation area, and then perform Si ion implantation on the ion implantation area twice, the implantation dose is 1×10 ¹⁴ cm ^-2 , and the implantation energy is 10kev to form a doped A highly doped region with a dopant concentration of 1×10 ¹⁷ cm ^-3 and a depth of 1um;

Place the epitaxial wafer after ion implantation in N ₂ environment, set the temperature in the annealing furnace to 900° C., and perform annealing for 30 minutes to activate the implanted ions.

Step 6: growing a gate dielectric, as shown in Figure 4(f).

Deposit Al ₂ O ₃ gate dielectric with a thickness of 20nm on the surface of gallium oxide epitaxial wafer through atomic layer deposition ALD process;

Atomic layer deposition ALD process conditions are:

Reaction chamber temperature: 200°C

Reaction chamber pressure: 800Pa

Reaction chamber gas: high-purity nitrogen

Reaction chamber gas flow rate: 300sccm

Step 7: Photolithography forms the source metal region to be evaporated, as shown in Figure 4(g)-(h).

Photoetching the through-holes of the source terminal electrodes on the surface of Al ₂ O ₃ , as shown in Figure 4(g);

Use the reactive ion etching RIE system to etch away the Al ₂ O ₃ in the electrode through hole area to form the source metal area to be evaporated as shown in Figure 4(h)

Reactive ion etching RIE system process conditions are:

Reaction chamber pressure: 10-30mTorr

Reaction chamber gas: BCl ₃ , Ar

Reaction chamber gas flow rate ratio: BCl ₃ :Ar=20sccm:10sccm

Etching power: 200W.

Step 8: Make source-drain ohmic electrodes, as shown in Figure 4(i).

8.1) Form the source electrode region by photolithography on the etched epitaxial wafer again, and deposit Ti/Au with a thickness of 60nm/120nm on the source electrode region by electron beam evaporation E-Beam system;

8.2) Put the sheet after electron beam evaporation into the stripping solution, and form the source terminal electrode by stripping;

8.3) Deposit Ti/Au with a thickness of 60nm/120nm on the surface of the substrate to form a drain terminal electrode, and set the temperature in the annealing furnace to 475°C in an _N2 environment, and anneal for one minute to form an ohmic contact, as shown in Figure 4 (i);

8.4) Perform photolithography on the surface of Al ₂ O ₃ to form a gate metal region to be evaporated.

Step 9: Make a gate electrode, as shown in Figure 4(j).

Deposit Ni/Au with a thickness of 50nm/100nm on the gate metal area to be evaporated by electron beam evaporation E-Beam system, put the sheet after electron beam evaporation into the stripping solution, form the gate electrode by stripping, and complete the device fabrication.

Example 2: Making an N-type β-Ga ₂ O ₃ substrate layer with a thickness of 600um and a doping of 2.5×10 ¹⁸ cm ^-3 , and an N-type β-Ga ₂ O ₃ drift layer with a thickness of 7um and a doping of 5×10 ¹⁶ cm ^-3 , the thickness of SiO ₂ is 750nm, the vertical heavily doped channel width is 10um, the thickness is 5um, the doping concentration is 5×10 ¹⁸ cm ^-3 , the n-type conductive material is In ₂ O ₃ , the thickness is 25nm, Vertical structure ^Ga2O3 field effect transistor with _SiO2 barrier layer and vertical heavily doped channel with doping of 5× ¹⁰¹⁸ cm _{- 3} .

Step A: cleaning the β-Ga ₂ O ₃ epitaxial wafer.

The specific implementation of this step is the same as step 1 of Embodiment 1.

Step B: trench structure etching.

Perform photolithography on the cleaned epitaxial wafer to form the area to be etched, then put it into the reactive ion etching RIE system, set the reaction chamber pressure to 1500mtorr, and the reaction chamber gas to be SF ₆ , CHF ₃ , He The gas flow rate ratio is SF ₆ :CHF ₃ :He=5.5sccm:32sccm:150sccm, the RF source power is 175W, and the etching depth is 810nm, so as to etch away the oxidation on the area to be etched of the epitaxial wafer Gallium, forming a trench structure.

Step C: Deposit SiO ₂ .

Put the etched gallium oxide epitaxial wafer into the ICP-CVD reaction chamber of the inductively coupled plasma enhanced chemical vapor deposition system, set the reaction chamber temperature to 85°C, the reaction chamber pressure to 550Pa, and the reaction chamber gas flow rate to 300sccm process conditions , deposit SiO ₂ with a thickness of 750nm on the surface of the epitaxial wafer, and then put the deposited wafer into a stripping solution to form a SiO ₂ barrier layer by stripping.

Step D: making an n-type conductive material layer.

Adopt the atomic layer deposition ALD method, set the temperature of the reaction chamber to be 200°C, the pressure of the reaction chamber to be 850Pa, the gas in the reaction chamber to be high-purity nitrogen, and the flow rate of the gas in the reaction chamber to be 300 sccm. 25nm n-type conductive material In ₂ O ₃ ; perform photolithography on the deposited epitaxial wafer to form the area to be etched, and then put it into the reactive ion etching RIE system, set the reaction chamber pressure to 1500mtorr, and the reaction chamber The gas is SF ₆ , CHF ₃ , He, the gas flow rate ratio in the reaction chamber is SF ₆ :CHF ₃ :He=5.5sccm:32sccm:150sccm, and the RF source power is 175W, and the area to be etched on the epitaxial wafer is etched. The n-type conductive material on the top forms the material of the ohmic contact area;

Step E: Ion implantation.

Perform photolithography on the surface of the etched epitaxial wafer to form a vertical conductive channel ion implantation area, and then perform Ge ion implantation twice on the ion implantation area, the implantation dose is 3×10 ¹⁴ cm ^-2 , and the implantation energy is 10kev, forming a doped A highly doped region with a dopant concentration of 5×10 ¹⁸ cm ^-3 and a depth of 5um;

Place the epitaxial wafer after ion implantation in N ₂ environment, set the temperature in the annealing furnace to 950° C., and perform annealing for 30 minutes to activate the implanted ions.

Step F: growing a gate dielectric.

Adopt atomic layer deposition ALD method, set reaction chamber temperature as 220 ℃, reaction chamber pressure as 850Pa, reaction chamber gas as high-purity nitrogen, reaction chamber gas flow rate as 300sccm process conditions, deposit thickness on gallium oxide epitaxial wafer surface 35nm Al ₂ O ₃ gate dielectric.

Step G: forming the source metal region to be evaporated by photolithography.

Lithograph the through hole of the source electrode on the surface of Al ₂ O ₃ , set the reaction chamber pressure of the reactive ion etching RIE system to 20mTorr, the reaction chamber gas is BCl ₃ , Ar, and the reaction chamber gas flow rate ratio is BCl ₃ :Ar=20sccm:10sccm , the etching power is 300W, and the Al ₂ O ₃ in the electrode through hole area is etched away to form the source metal area to be evaporated.

Step H: making source-drain ohmic electrodes.

H.1) Form the source electrode region by photolithography again on the epitaxial wafer after etching, and deposit Ti/Au with a thickness of 70nm/130nm on the source electrode region by electron beam evaporation E-Beam system;

H.2) Put the sheet after electron beam evaporation into the stripping solution, and form the source terminal electrode by stripping;

H.3) Deposit Ti/Au with a thickness of 70nm/130nm on the surface of the substrate to form a drain terminal electrode, and set the temperature in the annealing furnace to 475°C in an _N2 environment, and anneal for one minute to form an ohmic contact;

H.4) Perform photolithography on the surface of Al ₂ O ₃ to form a gate metal region to be evaporated.

Step 1: make gate electrode.

Deposit Ni/Au with a thickness of 55nm/110nm on the gate metal area to be evaporated by electron beam evaporation E-Beam system, put the sheet after electron beam evaporation into the stripping solution, form the gate electrode by stripping, and complete the device fabrication.

Example 3, making an N-type β-Ga ₂ O ₃ substrate layer with a thickness of 700um and a doping of 5×10 ¹⁸ cm ^-3 , and an N-type β-Ga ₂ O ₃ drift layer with a thickness of 10um and a doping of 1×10 ¹⁷ cm ^-3 , the thickness of SiO ₂ is 1000nm, the vertical heavily doped channel width is 20um, the thickness is 10um, the doping concentration is 5×10 ¹⁹ cm ^-3 , the n-type conductive material is In ₂ O ₃ , the thickness is 50nm, Vertically structured _Ga2O3 field-effect transistor with _SiO2 barrier layer and vertical heavily doped channel with doping of 5× ¹⁰¹⁹ cm ^- ₃ .

Step 1: cleaning the β-Ga ₂ O ₃ epitaxial wafer.

The specific implementation of this step is the same as step 1 of Embodiment 1.

Step 2: trench structure etching.

Perform photolithography on the cleaned epitaxial wafer to form the area to be etched, then put it into the reactive ion etching RIE system, set the reaction chamber pressure to 1500mtorr, and the reaction chamber gas to be SF ₆ , CHF ₃ , He The gas flow rate ratio is SF ₆ :CHF ₃ :He=5.5sccm:32sccm:150sccm, the RF source power is 200W, and the etching depth is 1010nm to etch away the oxidation on the area to be etched of the epitaxial wafer Gallium, forming a trench structure.

Step 3: Deposit SiO ₂ .

Put the etched gallium oxide epitaxial wafer into the ICP-CVD reaction chamber of the inductively coupled plasma enhanced chemical vapor deposition system. The reaction chamber temperature is 90°C, the reaction chamber pressure is 600Pa, and the reaction chamber gas flow rate is 300sccm. Next, deposit SiO ₂ with a thickness of 1000 nm on the surface of the epitaxial wafer, and then put the deposited wafer into a stripping solution to form a SiO ₂ barrier layer by stripping.

Step 4: making an n-type conductive material layer.

Using the atomic layer deposition ALD method, under the process conditions that the reaction chamber temperature is 200°C, the reaction chamber pressure is 900Pa, the reaction chamber gas is high-purity nitrogen, and the reaction chamber gas flow rate is 300sccm, the thickness is deposited on the surface of the gallium oxide epitaxial wafer. 50nm n-type conductive material In ₂ O ₃ ; carry out photolithography on the deposited epitaxial wafer to form the area to be etched, and then put it into the reactive ion etching RIE system, set the reaction chamber pressure to 1500mtorr, and react The chamber gas is SF ₆ , CHF ₃ , He, the reaction chamber gas flow rate ratio is SF ₆ :CHF ₃ :He=5.5sccm:32sccm:150sccm, the RF source power is 200W, and the epitaxial wafer is etched to be etched n-type conductive material on the region, forming an ohmic contact region material;

Step five: ion implantation.

Perform photolithography on the surface of the etched epitaxial wafer to form a vertical conductive channel ion implantation region, and then perform Sn ion implantation on the ion implantation region twice, with an implantation dose of 5×10 ¹⁴ cm ^-2 and an implantation energy of 10 keV to form a doped A highly doped region with a dopant concentration of 5×10 ¹⁸ cm ^-3 and a depth of 5um;

Place the epitaxial wafer after ion implantation in N ₂ environment, set the temperature in the annealing furnace to 950° C., and perform annealing for 30 minutes to activate the implanted ions.

Step six: growing gate dielectric.

Using the atomic layer deposition ALD method, under the process conditions of the reaction chamber temperature of 240°C, the reaction chamber pressure of 900Pa, the reaction chamber gas of high-purity nitrogen, and the reaction chamber gas flow rate of 300sccm, the thickness is deposited on the surface of the gallium oxide epitaxial wafer. 50nm Al ₂ O ₃ gate dielectric;

Step 7: Forming the source metal region to be evaporated by photolithography.

Lithograph the through hole of the source electrode on the surface of Al ₂ O ₃ , set the reaction chamber pressure of the reactive ion etching RIE system to 20mTorr, the reaction chamber gas is BCl ₃ , Ar, and the reaction chamber gas flow rate ratio is BCl ₃ :Ar=20sccm:10sccm , the etching power is 400W, and the Al ₂ O ₃ in the electrode through hole area is etched away to form the source metal area to be evaporated.

Step 8: Make source-drain ohmic electrodes.

The etched epitaxial wafer was photolithographically formed again to form the source electrode area, and Ti/Au with a thickness of 80nm/140nm was deposited on the source electrode area by electron beam evaporation E-Beam system; Put the chip into the stripping solution, and form the source terminal electrode by stripping; then deposit Ti/Au with a thickness of 80nm/140nm on the substrate surface to form the drain terminal electrode, and set the temperature in the _annealing furnace to 475 ℃, annealing for one minute to form an ohmic contact; finally, photolithography is performed on the surface of Al ₂ O ₃ to form a gate metal region to be evaporated.

Step 9: Make the gate electrode.

Deposit Ni/Au with a thickness of 60nm/120nm on the gate metal area to be evaporated by electron beam evaporation E-Beam system, put the sheet after electron beam evaporation into the stripping solution, form the gate electrode by stripping, and complete the device fabrication.

The above are only three embodiments of the present invention, and do not constitute any limitation to the present invention. Obviously, for those skilled in the art, after understanding the content and principles of the present invention, it is possible without departing from the principles and structures of the present invention. In some cases, various modifications and changes in form and details are made, but these modifications and changes based on the idea of the present invention are still within the protection scope of the claims of the present invention.

Claims (13)

1. A vertical structure Ga ₂ O ₃ transistor with SiO ₂ blocking layer, comprising gallium oxide substrate layer (1), gallium oxide epitaxial layer (2), gate oxide layer (3), and setting gate oxide layer (3) top There is a gate electrode (G), and the lower surface of the gallium oxide substrate layer (1) is a drain electrode (D), which is characterized in that: The epitaxial layer (2) is provided with a _SiO2 current blocking layer (4) on its inner periphery to achieve effective electrical isolation between source and drain, and a vertical heavily doped conductive channel (5) is provided at its center to reduce the device conductivity. On-resistance; an n-type conductive layer (6) is arranged above it to realize the re-growth of n-type conductive material; A source electrode (S) is arranged above the n-type conductive layer (6). 2. The transistor according to claim 1, characterized in that: ^the gallium ^oxide substrate layer (1) is made of N ^- type high Doped β-Ga ₂ O ₃ material. 3. The transistor according to claim 1, characterized in that: the gallium oxide epitaxial layer (2) is an N-type layer with a thickness of 3um-10um and a concentration of 1.5×10 ¹⁶ -1×10 ¹⁷ cm ^-3 Low-doped β-Ga ₂ O ₃ material. 4. The transistor according to claim 1, characterized in that: the SiO ₂ current blocking layer (4) has a thickness of 500nm-1000nm. 5. The transistor according to claim 1, characterized in that: the n-type conductive layer (6) is an N-type conductive layer with a thickness of 5nm-50nm and a concentration of 1×10 ¹⁷ -5×10 ¹⁹ cm ^-3 Highly doped GaN or SiC or In ₂ O ₃ wide or ultra-wide bandgap n-type conductive material. 6. The transistor according to claim 1, characterized in that: the vertical heavily doped conductive channel (5) has a thickness of 1um-10um, a width of 2um-20um, and a concentration of 1×10 ¹⁷ -5×10 ¹⁹ cm ^-3 N-type highly doped β-Ga ₂ O ₃ material. 7. A method for preparing a vertical structure Ga ₂ O ₃ transistor with SiO ₂ barrier layer, characterized in that, comprising the steps: 1) Cleaning the epitaxial wafer, that is, putting the homoepitaxial gallium oxide wafer into acetone solution, absolute ethanol solution and deionized water in sequence for ultrasonic cleaning for 5min-10min, and then blowing dry with nitrogen; 2) Perform photolithography on the cleaned epitaxial wafer to form the area to be etched, and then put it into the reactive ion etching RIE system to etch away the gallium oxide on the area to be etched on the epitaxial wafer to form a trench structure; 3) Put the etched gallium oxide epitaxial wafer into the ICP-CVD reaction chamber of the inductively coupled plasma enhanced chemical vapor deposition system, set the temperature of the reaction chamber at 80°C-90°C, and deposit a thickness of 500nm- 1000nm SiO ₂ , and then put the deposited sheet into the stripping solution to form a SiO ₂ barrier layer by stripping; 4) Deposit an n-type conductive material with a thickness of 10nm-20nm on the surface of the gallium oxide epitaxial wafer by atomic layer deposition ALD process; 5) Perform photolithography on the deposited epitaxial wafer to form the area to be etched, and then put it into the reactive ion etching RIE system to etch away the n-type conductive material on the area to be etched on the epitaxial wafer to form an ohmic contact area; 6) Perform photolithography on the etched epitaxial wafer to form a region to be ion implanted, and then implant n-type conductive ions in this region by ion implantation technology; 7) Depositing Al ₂ O ₃ with a thickness of 20nm-50nm on the surface of the gallium oxide epitaxial wafer after ion implantation by atomic layer deposition ALD process; 8) Lithographically etch the through hole of the source end electrode on the surface of Al ₂ O ₃ , and use the reactive ion etching RIE system to etch and remove the Al ₂ O ₃ in the area of the electrode through hole; 9) The etched epitaxial wafer is photolithographically formed again to form the source electrode area, and Ti/Au is first deposited on the source electrode area by electron beam evaporation E-Beam system, and the source electrode is formed by stripping, and then the substrate Deposit Ti/Au on the surface to form a drain terminal electrode, and anneal in _N2 environment to form an ohmic contact; 10) Perform photolithography on the gallium oxide epitaxial wafer after the ohmic contact is formed, form a gate region on the surface of Al ₂ O ₃ , and then deposit Ni/Au on the gate region by electron beam evaporation E-Beam system, and form a gate region by lift-off Electrode, complete device fabrication. 8. The method according to claim 7, wherein step 2) adopts reactive ion etching (RIE) process etching, and its processing conditions are as follows: Reaction chamber pressure: 1500-2000mtorr Reactor gas: SF ₆ , CHF ₃ , He Reaction chamber gas flow rate ratio: SF ₆ :CHF ₃ :He=5.5sccm:32sccm:150sccm RF radio frequency source: 150-300W. 9. The method according to claim 7, wherein in the step 4) adopting atomic layer deposition (ALD) technique to deposit n-type material, its process condition is as follows: Reaction chamber pressure: 800-900Pa Reaction chamber gas: high-purity nitrogen Reaction chamber gas flow rate: 300 sccm. 10. The method according to claim 7, wherein performing ion implantation in the ion implantation region in step 6) is to implant Si, Ge, Sn, ions with a dose of 1e14cm ⁻² to 5e14cm ⁻² and an energy of 10keV on the epitaxial wafer. F, one of Cl, forming a high-doped region with a doping concentration of 1e19cm ^-3 -5e19cm ^-3 and an implantation depth of 1-10um. 11. The method according to claim 7, wherein _in the step 7), the ALD process is used to deposit the _Al2O3 type material, and its processing conditions are as follows: Reaction chamber pressure: 800-900Pa Reaction chamber gas: high-purity nitrogen Reaction chamber gas flow rate: 300 sccm. 12. The method according to claim 7, wherein in step 8), the reactive ion etching (RIE) process is used to etch Al ₂ O ₃ , and the process conditions are as follows: Reaction chamber pressure: 10-30mTorr Reaction chamber gas: BCl ₃ , Ar Reaction chamber gas flow rate ratio: BCl ₃ :Ar=20sccm:10sccm Etching power: 200-400W. 13. The method of claim 7, wherein: The Ti/Au deposited in the step 9) has a thickness of 60nm/120nm-80nm/140nm; The Ni/Au deposited in step 10) has a thickness of 50nm/100nm-60nm/120nm.

Images