CN112133757B - Gate-controlled gallium oxide field effect transistor based on p-i-n structure and preparation method thereof - Google Patents
Gate-controlled gallium oxide field effect transistor based on p-i-n structure and preparation method thereof Download PDFInfo
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 40
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 40
- 230000005669 field effect Effects 0.000 title claims abstract description 22
- 238000002360 preparation method Methods 0.000 title abstract description 6
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 claims abstract description 62
- 239000010410 layer Substances 0.000 claims abstract description 62
- 239000010409 thin film Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000005468 ion implantation Methods 0.000 claims abstract description 20
- 239000011241 protective layer Substances 0.000 claims abstract description 10
- 239000010408 film Substances 0.000 claims description 61
- 238000000151 deposition Methods 0.000 claims description 40
- 238000000137 annealing Methods 0.000 claims description 34
- 150000002500 ions Chemical class 0.000 claims description 32
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- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000000231 atomic layer deposition Methods 0.000 claims description 12
- 239000000243 solution Substances 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 11
- 230000008020 evaporation Effects 0.000 claims description 11
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 10
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- 239000007788 liquid Substances 0.000 claims description 8
- 238000001465 metallisation Methods 0.000 claims description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 7
- 229910052593 corundum Inorganic materials 0.000 claims description 7
- 238000005566 electron beam evaporation Methods 0.000 claims description 7
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000009616 inductively coupled plasma Methods 0.000 claims description 6
- 229910052594 sapphire Inorganic materials 0.000 claims description 6
- 239000010980 sapphire Substances 0.000 claims description 6
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000008367 deionised water Substances 0.000 claims description 5
- 229910021641 deionized water Inorganic materials 0.000 claims description 5
- JEGUKCSWCFPDGT-UHFFFAOYSA-N h2o hydrate Chemical compound O.O JEGUKCSWCFPDGT-UHFFFAOYSA-N 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 5
- 238000005406 washing Methods 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 238000001035 drying Methods 0.000 claims description 4
- 239000002243 precursor Substances 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims 3
- 229910001873 dinitrogen Inorganic materials 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 235000012431 wafers Nutrition 0.000 description 21
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 239000000463 material Substances 0.000 description 6
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- 241001354791 Baliga Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
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- 238000005137 deposition process Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910000480 nickel oxide Inorganic materials 0.000 description 1
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H01L29/42312—Gate electrodes for field effect devices
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Abstract
The invention discloses a gate-controlled gallium oxide field effect transistor based on a p-i-n structure and a preparation method thereof, and mainly solves the problems that the conventional n-type gallium oxide field effect transistor is low in breakdown voltage and difficult to turn off. It includes from bottom to top: ga2O3Substrate, n-Ga2O3The two ends of the upper part of the epitaxial layer are provided with ion implantation regions, and the middle region is provided with a gate electrode; the upper part of the ion implantation area is respectively provided with a source electrode and a drain electrode; n-Ga between its inner surface and gate electrode and source and drain electrodes, respectively2O3Al is provided on the epitaxial layer2O3A protective layer; i-Ga is arranged between the epitaxial layer and the gate electrode2O3A thin film layer and a p-type NiO thin film layer, i-Ga2O3Thin film layer and n-Ga2O3The epitaxial layers form a p-i-n structure. The invention improves the performance and reliability of the device and can be used for preparing an enhanced gallium oxide device with high breakdown voltage.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a gate-controlled gallium oxide field effect transistor which can be used for preparing a high-voltage-resistant enhanced gallium oxide device.
Technical Field
Gallium oxide has five crystal forms of alpha, beta, gamma, delta and epsilon, wherein monoclinic beta-Ga2O3Has the best thermal stability, and other metastable phases are easy to be converted into beta-Ga at high temperature2O3Therefore, most studies are now around β -Ga2O3And (4) unfolding. beta-Ga2O3The silicon nitride has an ultra-large forbidden band width (4.4-4.9eV), and the ionization rate is low, so that the breakdown field strength is high, about 8MV/cm, which is more than 20 times that of Si and more than twice that of SiC and GaN. Furthermore, beta-Ga2O3The quality factor of the GaN-based material is more than 8 times that of 4H-SiC and more than 4 times that of GaN; the high frequency Baliga merit value is about 150 times that of Si, about 3 times that of 4H-SiC, and about 1.5 times that of GaN. Ga2O3The theoretical value of the on-resistance of the material is very low, and the on-loss of the unipolar device under the same condition is at least one order of magnitude lower than that of a SiC device and a GaN device, so that the efficiency of the device is improved. Analysis in general, beta-Ga2O3Is a power semiconductor material with great prospect and is based on beta-Ga2O3The power semiconductor device has great potential in high-frequency, high-voltage and high-power application.
The horizontal structure of the currently prepared n-type gallium oxide field effect transistor is mainly the structure shown in figure 1, and comprises a substrate layer and n-Ga2O3A layer, a source electrode, a drain electrode, a dielectric layer, and a gate electrode. Usually, SiO is used for the substrate layer2Sapphire insulating substrate or semi-insulating Ga doped with Fe and Mg2O3A layer; n-Ga2O3The layer is a channel layer doped with Si or Sn, and the regulation and control of an n-type gallium oxide crystal carrier in a larger range can be realized by doping Si and Sn; the source electrode adopts metal Ti/Au or Ti/Al/Ni/Au; the dielectric layer is made of Al2O3Or HfO; the gate electrode is made of metal Ni/Au. Although the ideal breakdown voltage of the material of the gallium oxide field effect transistor with the horizontal structure shown in fig. 1 is large, the breakdown voltage of the actually prepared device is far lower than the ideal value, and the leakage current is large; in addition, the turn-off can be realized only by applying a certain negative gate voltage, namely, when the gate voltage is in a zero bias state, the device is in a non-turn-off state, so that the reliability of the device is reduced, the static power consumption of the device is increased, and the application range of the device is limited.
Disclosure of Invention
Objects of the inventionAiming at the defects of the n-type gallium oxide device, a grid-control gallium oxide field effect transistor based on a p-i-n structure and a preparation method thereof are provided, so that other p-type materials are used for being matched with i-Ga2O3And n-Ga2O3The p-i-n junction is constructed, the breakdown voltage of the device is improved, the static loss of the device is obviously reduced by introducing the p-i-n junction structure into the grid end, and the enhanced gallium oxide device with good performance and high reliability is realized.
In order to achieve the above object, the gate-controlled gallium oxide field effect transistor based on p-i-n structure of the present invention comprises, from bottom to top: substrate, n-Ga2O3Epitaxial layer of n-Ga2O3Ion implantation regions are arranged at two ends of the upper part of the epitaxial layer, a source electrode and a drain electrode are respectively arranged at the upper part of the ion implantation regions, and n-Ga is arranged2O3The middle region of the upper end of the epitaxial layer is provided with a gate electrode, and n-Ga between the gate electrode and the source electrode and between the gate electrode and the drain electrode is respectively2O3Al is provided on the epitaxial layer and on the inner surfaces of the source and drain electrodes2O3A protective layer, characterized by:
the n-Ga2O3i-Ga is arranged between the epitaxial layer and the gate electrode2O3A thin film layer and a p-type NiO thin film layer, i-Ga2O3Thin film layer and n-Ga2O3The epitaxial layer forms a p-i-n structure to form a high-voltage-resistant enhanced gallium oxide device.
Further, Ga is adopted as the substrate2O3Substrate, SiO2Any one of a substrate and a sapphire insulating substrate; the source electrode and the drain electrode both adopt Ti/Au with the thickness of 60nm/120 nm; the gate electrode adopts Ni/Au with the thickness of 60nm/60 nm; i-Ga2O3The thickness of the thin film layer is 80nm-120 nm; the thickness of the p-type NiO thin film layer is 200nm-300 nm.
In order to achieve the above purpose, the preparation method of the gate-controlled gallium oxide field effect transistor based on the p-i-n structure comprises the following steps:
1) selecting and cleaning a gallium oxide epitaxial wafer, namely sequentially putting the gallium oxide epitaxial wafer into an acetone solution and an absolute ethyl alcohol solution, respectively ultrasonically cleaning for 5-10 min, then washing with a large amount of deionized water, and then drying with nitrogen;
2) depositing i-Ga with the thickness of 80nm-120nm on the cleaned n-epitaxial layer2O3Annealing the film in an oxygen environment at 900 ℃ for 1 h;
3) in depositing i-Ga2O3Photoetching the surface of the device of the film, namely firstly coating photoresist outside the ion region to be implanted with i-Ga2O3On the film, obtaining an ion region to be implanted which is not protected by the photoresist through a series of process flows of pre-baking, alignment and exposure, post-baking, development, film hardening and pattern detection;
4) implanting n-type ions into an ion region to be implanted formed after the photoetching is finished to form a high-doping region with the doping concentration of 5e19 and the depth of 90nm-130 nm; then, annealing the sample after ion implantation, namely N2In the environment, setting the annealing temperature in the furnace to be 950 ℃ and the annealing time to be 30min so as to activate the injected n-type ions;
5) i-Ga after ion implantation is completed2O3Photoetching the surface of the film to form a source electrode area and a drain electrode area, depositing Ti/Au with the thickness of 60nm/120nm on the source electrode area and the drain electrode area through an electron Beam evaporation E-Beam system, putting the wafer after metal deposition into stripping liquid, and stripping to form a source electrode and a drain electrode; then the sample is placed in an annealing furnace at N2In the environment, setting the annealing temperature in the furnace to be 480 ℃ and the annealing time to be 1min to form a source electrode and a drain electrode with good ohmic contact;
6) i-Ga for manufacturing source and drain electrodes2O3Photoetching the film, namely forming a p-NiO area to be deposited through a series of process flows of photoresist coating, prebaking, aligning and exposing, postbaking, developing, film hardening and pattern detection;
7) inductively coupled plasma chemical vapor deposition (ICP-CVD) is applied to i-Ga2O3Depositing a NiO film with the thickness of 200nm-300nm in a p-type NiO area to be deposited on the film;
8) forming a gate region on the sample piece on which the p-type NiO film is deposited by photoetching, depositing Ni/Au with the thickness of 60nm/60nm in the gate region by an electron Beam evaporation E-Beam system, putting the sheet on which the metal is deposited into stripping liquid, and forming a gate electrode by stripping;
9) by atomic layer deposition ALD process with trimethylaluminum TMA and water H2O as a precursor, i-Ga between the gate electrode and the source and drain electrodes, respectively2O3Depositing Al with a thickness of 20nm on the thin film layer and the inner surfaces of the source and drain electrodes2O3And as a protective layer, completing the manufacture of the device.
The invention has the following advantages:
1. the invention introduces i-Ga into an n-type gallium oxide MOSFET device2O3The thin film and the p-type NiO thin film are made of the p-type NiO thin film and the i-Ga2O3Thin film, n-Ga2O3The epitaxial layer forms a p-i-n junction, and the p-i-n junction has higher voltage withstanding property, so that the breakdown voltage of the device can be effectively improved, and the device has a large development space in the aspect of high-voltage power electronic devices.
2. According to the invention, the p-i-n junction gate control structure is introduced into the MOSFET to form the enhanced gallium oxide device, so that the device is in a turn-off state when the gate voltage is in a zero-bias state, the static loss of the device is reduced, and the reliability of the device is improved.
3. When depositing NiO film, the invention applies inductively coupled plasma chemical vapor deposition ICP-CVD process to form large area, high uniformity and high electron density plasma under low temperature and low pressure, thereby obtaining high quality nickel oxide film with good uniformity and high compactness by rapid deposition.
Drawings
Fig. 1 is a schematic horizontal structure diagram of a conventional n-type gallium oxide field effect transistor.
FIG. 2 is a schematic diagram of a gated gallium oxide field effect transistor based on a p-i-n structure according to the present invention.
FIG. 3 is a schematic diagram of an implementation process for manufacturing a gate-controlled gallium oxide field effect transistor based on a p-i-n structure according to the present invention.
Detailed Description
The structure and the preparation process of the gated gallium oxide field effect transistor with the p-i-n structure of the invention are further described in detail in the following with the attached drawings.
It was found that in the NiO film, there is a significant p-type conductivity without artificial doping, and the hole concentration is relatively high, about 1X 1019cm-3. Therefore, NiO was chosen as the p-type material and i-Ga2O3And n-Ga2O3And constructing a p-i-n junction to improve the performance and reliability of the device.
Referring to FIG. 2, the invention relates to a gated gallium oxide field effect transistor based on a p-i-n structure, which comprises a substrate 1 and n-Ga2O3Epitaxial layer 2, ion implantation region 3, i-Ga2O3Thin film layer 4, source electrode 5, drain electrode 6, Al2O3A protective layer 7, a p-type NiO thin film layer 8 and a gate electrode 9. Wherein, the substrate 1 is positioned at the bottommost part of the device and adopts Ga with the thickness of 300nm2O3Substrate, SiO2Any one of a substrate or a sapphire insulating substrate; n-Ga2O3The epitaxial layer is 2 on the substrate 1, and the thickness is 200 nm; the ion implantation region 3 is located in n-Ga2O3The depth of two ends of the upper part of the epitaxial layer 2 is 90nm-130 nm; i-Ga2O3The thin film layer 4 is positioned at n-Ga2O3The thickness of the epitaxial layer 2 is 80nm-120 nm; the source electrode 5 and the drain electrode 6 are respectively positioned at the upper parts of the two ion injection regions 3 and both adopt Ti/Au with the thickness of 60nm/120 nm; the gate electrode 9 is positioned in the middle area of the upper part of the layer 4 and is made of Ni/Au with the thickness of 60nm/60 nm; the p-type NiO thin film layer 8 is positioned between the gate electrode 9 and the i-Ga2O3Between the thin film layers 4, the thin film and i-Ga2O3Film 4 and n-Ga2O3The epitaxial layer 2 forms a p-i-n structure so as to improve the breakdown voltage of the device and realize an enhanced gallium oxide device; al (Al)2O3A protective layer 7 of i-Ga between the gate electrode 9 and the source and drain electrodes 5 and 6, respectively2O3On the thin film layer 4, and the inner surfaces of the source electrode 5 and the drain electrode 6.
Referring to fig. 3, the present invention provides three examples of preparing a gated gallium oxide field effect transistor based on a p-i-n structure as follows:
example 1, a p-type NiO film with a thickness of 200nm was formed on a gallium oxide substrate with a thickness of 300nm and an n-type gallium oxide homoepitaxial wafer with a thickness of 200nm, i-Ga2O3A gallium oxide transistor having a thin film thickness of 100 nm.
Step 1, cleaning the epitaxial wafer, as shown in fig. 3 (a).
Selecting homoepitaxy gallium oxide epitaxial wafers and cleaning, namely sequentially placing the homoepitaxy gallium oxide epitaxial wafers into an acetone solution and an absolute ethyl alcohol solution for ultrasonic cleaning for 5min respectively, then washing with a large amount of deionized water, and then drying with nitrogen.
Step 2, depositing i-Ga2O3Film, fig. 3 (b).
Depositing i-Ga with the thickness of 100nm on the cleaned epitaxial wafer2O3And annealing the thin film layer in an oxygen environment at 900 ℃ for 1h to improve the interface contact performance.
Step 3, forming an ion region to be implanted by photolithography, as shown in fig. 3 (c).
In the deposition of i-Ga2O3Photoetching the surface of a sample piece of the film, namely firstly coating photoresist outside an ion region to be implanted with i-Ga2O3And (3) obtaining an ion region to be implanted which is not protected by the photoresist on the film through a series of specific process flows of pre-baking, aligning and exposing, post-baking, developing, hardening and pattern detection.
And 4, ion implantation, as shown in fig. 3 (d).
Implanting Si ions into an ion region to be implanted formed after the completion of the photoetching to form a high-doping region with the doping concentration of 5e19 and the depth of 110 nm; then, annealing the sample after ion implantation, namely N2In the environment, the annealing temperature in the furnace is set to 950 ℃, and the annealing time is set to 30min, so as to activate the implanted Si ions.
And 5, manufacturing a source-drain ohmic electrode as shown in fig. 3 (e).
i-Ga after ion implantation is completed2O3Photoetching the surface of the film to form a source electrode area and a drain electrode area, depositing Ti/Au with the thickness of 60nm/120nm on the source electrode area and the drain electrode area through an electron Beam evaporation E-Beam system, putting the wafer after metal deposition into stripping liquid, and stripping to form a source electrode and a drain electrode; then the sample is placed in an annealing furnace at N2In the environment, the annealing temperature in the furnace is set to be 480 ℃, and the annealing time is set to be 1min, so that the source electrode and the drain electrode with good ohmic contact are formed.
And 6, depositing a p-type NiO film as shown in figure 3 (f).
Photoetching is carried out on an epitaxial wafer on which source end and drain end electrodes are manufactured, namely a p-NiO area to be deposited is formed through a series of processes of photoresist coating, prebaking, aligning and exposing, postbaking, developing, film hardening and pattern detection; then applying inductively coupled plasma chemical vapor deposition (ICP-CVD) to the i-Ga2O3And a NiO film with the thickness of 200nm is deposited in the p-type NiO area to be deposited on the film.
Step 7, a gate electrode is fabricated, as shown in fig. 3 (g).
Forming a gate region on the epitaxial wafer on which the p-type NiO film is deposited by photoetching, evaporating an E-Beam system by using an electron Beam, setting the evaporation rate to be 3A/s, the pre-evaporation power to be 30, the working vacuum to be 5E-4Pa, the working temperature to be 20 ℃, and depositing Ni/Au with the thickness of 60nm/60nm on the gate region; and then placing the wafer after the metal deposition into stripping liquid, and forming a gate electrode by stripping.
Step 8, depositing Al2O3See fig. 3 (h).
By atomic layer deposition ALD process with trimethylaluminum TMA and water H2O as a precursor, i-Ga between the gate electrode and the source and drain electrodes, respectively2O3Depositing Al with a thickness of 20nm on the thin film layer and the inner surfaces of the source and drain electrodes2O3And as a protective layer, completing the manufacture of the device.
Example 2 SiO at a thickness of 300nm2Insulating substrate with thickness of 200nmn-Ga of2O3The thickness of the p-type NiO film manufactured on the film is 300nm, i-Ga2O3A gallium oxide transistor with a thin film thickness of 120 nm.
Step one, cleaning the sample wafer, as shown in fig. 3 (a).
2.1) mixing n-Ga with a thickness of 200nm2O3Film transfer to SiO 300nm thick2An insulating substrate;
2.2) putting the sample wafer after the transfer into an acetone solution and an absolute ethyl alcohol solution in sequence, performing ultrasonic cleaning for 8min respectively, washing with a large amount of deionized water, and then drying with nitrogen.
Step two, depositing i-Ga2O3Film, fig. 3 (b).
n-Ga after cleaning2O3Depositing i-Ga with the thickness of 120nm on the film2O3And annealing the thin film layer in an oxygen environment at 900 ℃ for 1h to improve the interface contact performance.
And step three, forming an ion region to be implanted by photoetching, as shown in figure 3 (c).
In depositing i-Ga2O3Firstly coating photoresist on the surface of a device of the film outside an ion region to be implanted with i-Ga2O3And (3) obtaining an ion region to be implanted which is not protected by the photoresist on the film through a series of specific process flows of pre-baking, aligning and exposing, post-baking, developing, hardening and pattern detection.
Step four, ion implantation, as shown in fig. 3 (d).
4.1) implanting Sn ions into an ion region to be implanted formed after the photoetching is finished to form a high-doping region with the doping concentration of 5e19 and the depth of 130 nm;
4.2) annealing the sample after ion implantation, i.e. in N2In the environment, the annealing temperature in the furnace is set to 950 ℃, and the annealing time is set to 30min, so as to activate the implanted Sn ions.
And fifthly, manufacturing a source-drain ohmic electrode as shown in fig. 3 (e).
5.1) i-Ga after ion implantation2O3Surface of filmPhotoetching is carried out to form a source electrode area and a drain electrode area, and Ti/Au with the thickness of 60nm/120nm is deposited in the source electrode area and the drain electrode area through an electron Beam evaporation E-Beam system;
5.2) placing the sample wafer after the metal deposition into stripping liquid, and stripping to form a source electrode and a drain electrode;
5.3) placing the stripped sample piece in an annealing furnace, and adding N2In the environment, the annealing temperature in the furnace is set to be 480 ℃, and the annealing time is set to be 1min, so that the source electrode and the drain electrode with good ohmic contact are formed.
And step six, depositing a p-type NiO film, as shown in figure 3 (f).
6.1) i-Ga for making source and drain electrodes2O3Forming a p-NiO area to be deposited on the film through a series of processes of photoresist coating, prebaking, aligning and exposing, postbaking, developing, film hardening and pattern detection;
6.2) applying inductively coupled plasma chemical vapor deposition (ICP-CVD) on i-Ga2O3Depositing a NiO film with the thickness of 200nm on an area to be deposited with p-type NiO on the film;
and step seven, manufacturing a gate electrode, as shown in fig. 3 (g).
7.1) forming a grid region on a sample wafer on which a p-type NiO film is deposited by photoetching, evaporating an E-Beam system by electron beams, setting the evaporation rate to be 3A/s, the pre-evaporation power to be 30, the working vacuum to be 5E-4Pa, the working temperature to be 20 ℃, and depositing Ni/Au with the thickness of 60nm/60nm on the grid region;
and 7.2) putting the wafer subjected to metal deposition into a stripping solution, and forming a gate electrode by stripping.
Step eight, depositing Al2O3See fig. 3 (h).
By atomic layer deposition ALD process with trimethylaluminum TMA and water H2O as a precursor, i-Ga between the gate electrode and the source and drain electrodes, respectively2O3Depositing Al with a thickness of 20nm on the thin film layer and the inner surfaces of the source and drain electrodes2O3And as a protective layer, completing the manufacture of the device.
Example 3 n-Ga with thickness of 200nm on a sapphire insulating substrate with thickness of 300nm2O3The thickness of the p-type NiO film manufactured on the film is 200nm, i-Ga2O3A gallium oxide transistor having a thin film thickness of 80 nm.
Step A, washing the sample wafer, as shown in FIG. 3 (a).
Firstly, n-Ga with the thickness of 200nm2O3Transferring the thin film layer to a sapphire insulating substrate with the thickness of 300 nm;
then, the sample wafer after the transfer is sequentially placed into an acetone solution and an absolute ethyl alcohol solution for ultrasonic cleaning for 6min, then is washed by a large amount of deionized water, and then is dried by nitrogen.
Step B, depositing i-Ga2O3Film, fig. 3 (b).
n-Ga after cleaning2O3Depositing i-Ga with the thickness of 80nm on the film2O3And annealing the thin film layer in an oxygen environment at 900 ℃ for 1h to improve the interface contact performance.
Step C, forming an ion region to be implanted by photolithography, as shown in FIG. 3 (C).
In the deposition of i-Ga2O3Photoetching the surface of a sample piece of the film, namely firstly coating photoresist outside an ion region to be implanted with i-Ga2O3And (3) obtaining an ion region to be implanted which is not protected by the photoresist on the film through a series of specific process flows of pre-baking, aligning and exposing, post-baking, developing, hardening and pattern detection.
And D, ion implantation, as shown in figure 3 (D).
Firstly, Si ions are implanted into an ion region to be implanted formed after photoetching is finished to form a high-doping region with the doping concentration of 5e19 and the depth of 90 nm;
then, the sample after ion implantation is annealed, i.e. at N2In the environment, the annealing temperature in the furnace is set to 950 ℃, and the annealing time is set to 30min, so as to activate the implanted Si ions.
And E, manufacturing a source-drain ohmic electrode as shown in figure 3 (E).
First, i-Ga after ion implantation is completed2O3Photoetching the surface of the film to form a source electrode area and a drain electrode area, evaporating an E-Beam system by an electron Beam, setting the evaporation rate to be 5A/s, the pre-evaporation power to be 35, the working vacuum to be 5E-4Pa, the working temperature to be 20 ℃, and depositing Ti/Au with the thickness of 60nm/120nm on the source electrode area and the drain electrode area;
then, putting the wafer after the metal deposition into stripping liquid, and stripping to form a source electrode and a drain electrode;
thereafter, the sample was placed in an annealing furnace at N2In the environment, the annealing temperature in the furnace is set to be 480 ℃, and the annealing time is set to be 1min, so that the source electrode and the drain electrode with good ohmic contact are formed.
Step F, depositing a p-type NiO film, as shown in FIG. 3 (F).
First, i-Ga of source and drain electrodes is manufactured2O3Photoetching the film, and forming a p-NiO area to be deposited by a series of processes of photoresist coating, prebaking, aligning and exposing, postbaking, developing, film hardening and pattern detection;
then, inductively coupled plasma chemical vapor deposition (ICP-CVD) is applied to the i-Ga2O3Depositing a NiO film with the thickness of 200nm in an area to be deposited with p-type NiO on the film;
and G, manufacturing a gate electrode, as shown in fig. 3 (G).
Firstly, forming a gate region on a sample wafer on which a p-type NiO film is deposited by photoetching, and then depositing Ni/Au with the thickness of 60nm/60nm on the gate region by an electron Beam evaporation E-Beam system, wherein the deposition process conditions are as follows: setting the evaporation rate to be 3A/s, the pre-evaporation power to be 30, the working vacuum to be 5e-4Pa and the working temperature to be 20 ℃;
then, the wafer after the metal deposition is put into a stripping solution, and a gate electrode is formed by stripping.
Step H, depositing Al2O3See fig. 3 (h).
By atomic layer deposition ALD process with trimethylaluminum TMA and water H2O asPrecursor, i-Ga between gate electrode and source and drain electrodes respectively2O3Depositing Al with a thickness of 20nm on the thin film layer and the inner surfaces of the source and drain electrodes2O3And as a protective layer, completing the manufacture of the device.
While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A gate-controlled gallium oxide field effect transistor based on a p-i-n structure comprises the following components from bottom to top: substrate (1), n-Ga2O3Epitaxial layer (2), n-Ga2O3Two ends of the upper part of the epitaxial layer (2) are provided with ion injection regions (3), the upper part of the ion injection regions (3) is respectively provided with a source electrode (5) and a drain electrode (6), and n-Ga2O3A gate electrode (9) is arranged in the middle area of the upper end of the epitaxial layer (2), and n-Ga is respectively arranged between the gate electrode (9) and the source electrode (5) and the drain electrode (6)2O3Al is arranged on the epitaxial layer (2) and on the inner surfaces of the source electrode (5) and the drain electrode (6)2O3A protective layer (7), characterized in that:
the n-Ga2O3i-Ga is arranged between the epitaxial layer (2) and the gate electrode (9)2O3A thin film layer (4) and a p-type NiO thin film layer (8), the p-type NiO thin film layer (8) and i-Ga2O3Thin film layer (4) and n-Ga2O3The epitaxial layer (2) forms a p-i-n structure to form a high-withstand-voltage enhancement-type gallium oxide device.
2. The field effect transistor of claim 1, wherein the substrate (1) is Ga2O3Substrate, SiO2Any one of a substrate and a sapphire insulating substrate.
3. The field effect transistor according to claim 1, wherein the source electrode (5) and the drain electrode (6) each employ Ti/Au having a thickness of 60nm/120 nm.
4. The field effect transistor according to claim 1, wherein the gate electrode (9) uses Ni/Au with a thickness of 60nm/60 nm.
5. The field effect transistor of claim 1, wherein i-Ga2O3The thickness of the thin film layer (4) is 80nm-120 nm; the thickness of the p-type NiO thin film layer (8) is 200nm-300 nm.
6. A manufacturing method of a gate-controlled gallium oxide field effect transistor with a p-i-n structure comprises the following steps:
1) selecting and cleaning a gallium oxide epitaxial wafer, namely sequentially putting the gallium oxide epitaxial wafer into an acetone solution and an absolute ethyl alcohol solution, respectively ultrasonically cleaning for 5-10 min, then washing with a large amount of deionized water, and then drying with nitrogen;
2) depositing i-Ga with the thickness of 80nm-120nm on the cleaned n-epitaxial layer2O3Annealing the film in an oxygen environment at 900 ℃ for 1 h;
3) in depositing i-Ga2O3Photoetching the surface of the device of the film, namely firstly coating photoresist outside the ion region to be implanted with i-Ga2O3On the film, obtaining an ion region to be implanted which is not protected by the photoresist through a series of process flows of pre-baking, alignment and exposure, post-baking, development, film hardening and pattern detection;
4) implanting n-type ions into an ion region to be implanted formed after the photoetching is finished to form a high-doping region with the doping concentration of 5e19 and the depth of 90nm-130 nm; then, annealing the sample after ion implantation, namely N2In the environment, setting the annealing temperature in the furnace to be 950 ℃ and the annealing time to be 30min so as to activate the injected n-type ions;
5) i-Ga after ion implantation is completed2O3Photoetching the surface of the film to form source and drain regionsDepositing Ti/Au with the thickness of 60nm/120nm in a source electrode area and a drain area by an electron Beam evaporation E-Beam system, putting the wafer after metal deposition into stripping liquid, and stripping to form a source electrode and a drain electrode; then the sample is placed in an annealing furnace at N2In the environment, setting the annealing temperature in the furnace to be 480 ℃ and the annealing time to be 1min to form a source electrode and a drain electrode with good ohmic contact;
6) i-Ga for manufacturing source and drain electrodes2O3Photoetching the film, namely forming a p-NiO area to be deposited through a series of process flows of photoresist coating, prebaking, aligning and exposing, postbaking, developing, film hardening and pattern detection;
7) inductively coupled plasma chemical vapor deposition (ICP-CVD) is applied to i-Ga2O3Depositing a NiO film with the thickness of 200nm-300nm in a p-type NiO area to be deposited on the film;
8) forming a gate region on the sample piece on which the p-type NiO film is deposited by photoetching, depositing Ni/Au with the thickness of 60nm/60nm in the gate region by an electron Beam evaporation E-Beam system, putting the sheet on which the metal is deposited into stripping liquid, and forming a gate electrode by stripping;
9) by atomic layer deposition ALD process with trimethylaluminum TMA and water H2O as precursor, i-Ga between the gate electrode and the source and drain electrodes, respectively2O3Depositing Al with a thickness of 20nm on the thin film layer and the inner surfaces of the source and drain electrodes2O3And as a protective layer, completing the manufacture of the device.
7. The method as claimed in claim 6, wherein the n-type ions to be implanted into the ion implantation region in 4) are implanted with Si or Sn at a dose of 1e15 and an energy of 50KeV-80KeV to form a final doping concentration of 5e19cm-3And the depth is 90nm-130 nm.
8. The method of claim 6, wherein in 5) an E-Beam evaporation E-Beam system is used to deposit the metal Ti/Au in the source and drain regions under the following process conditions:
evaporation rate: 0.1-20A/s
Pre-evaporation power: 5-45
Evaporation power: 0-60
Working vacuum: 5e-4Pa
Working temperature: 20-200 ℃.
9. The method of claim 6, wherein 7) the low-temperature deposition equipment ICP-CVD is used for depositing the p-type NiO film, and the process conditions are as follows:
reaction chamber pressure: 10mTorr
Ionization voltage: 1.8-4.5KV
Plasma ionization electrode: ni
Reaction chamber gas: o is2、N2、Ar。
10. The method of claim 6, wherein the atomic layer deposition ALD process is used to deposit Al in 9)2O3The process conditions are as follows:
pressure in the reaction chamber: 880Pa
Reaction chamber gas: high purity nitrogen gas
Reaction chamber gas flow rate: 300sccm
Al2O3Growth rate: 0.5nm/min
Al2O3And (3) growth time: 40min-100 min.
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