CN104952868A - Grid-control PIN junction electrostatic discharge protection device triggered by diode chain - Google Patents
Grid-control PIN junction electrostatic discharge protection device triggered by diode chain Download PDFInfo
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- CN104952868A CN104952868A CN201510037402.3A CN201510037402A CN104952868A CN 104952868 A CN104952868 A CN 104952868A CN 201510037402 A CN201510037402 A CN 201510037402A CN 104952868 A CN104952868 A CN 104952868A
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Abstract
The invention relates to the technical field of the electrostatic discharge protection of the integrated circuit, especially to a grid-control PIN junction electrostatic discharge protection device triggered by a diode chain. The electrostatic discharge protection device comprises a P type substrate, n N type well regions, and a grid-control PIN junction, wherein n is a constant. The n N type well regions and the grid-control PIN junction are formed on the P type substrate; the N type well regions are connected with an input terminal; and the grid-control PIN junction is arranged at one side, connecting the input terminal, of each N type well region. A second N+ doping region is formed between the grid-control PIN junction and the N type well regions; a first N+ doping region is formed at the other side of the grid-control PIN junction; and a first P+ doping region is formed on the first N+ doping region. The P+ doping regions in the N type well regions and the N+ doping regions are in the identical opposite position relation. According to the grid-control PIN junction electrostatic discharge protection device, on the basis of no increase of electricity leakage, the trigger voltage can be effectively adjusted, thereby meeting the different I/O requirements.
Description
Technical field
The present invention relates to the electrostatic discharge (ESD) protection technical field of integrated circuit, particularly relate to the grid-control PIN junction electrostatic discharge protector that a kind of diode chain triggers.
Background technology
Static discharge (Electrostatic Discharge, the ESD) phenomenon of integrated circuit be chip when suspension joint, a large amount of electric charges pours into the instantaneous process of integrated circuit from outside to inside.Because the internal resistance of integrated circuit (IC) chip is very low, when ESD phenomenon occurs, instantaneous (100 ~ 200 nanoseconds consuming time can be produced, rise time was only about for 0.1 ~ 10 nanosecond), the electric current of peak value (several amperes), and produce a large amount of Joule heats, thus the problem that integrated circuit (IC) chip lost efficacy can be caused.
For the integrated circuit technology of advanced person, the ESD safeguard structure of diode chain auxiliary triggering with the feature of its adjustable trigger voltage, and is widely used among I/O electrostatic defending.The ESD protective device structure chart that traditional diode chain triggers as shown in Figure 1, flows out from the substrate of ground connection because PNP that Darlington effect diode chain is parasitic in vertical direction can collect a large amount of electric currents, thus brings larger quiescent dissipation.And in the process that temperature rises, leakage current can increase fast, has caused the further increase of quiescent dissipation.
Summary of the invention
The technical problem to be solved in the present invention there is provided a kind of not increasing on the basis of electric leakage, grid-control PIN junction static discharge (the Diode Chain Triggered Gated-P-I-N Junction ESD) protection device that can effectively regulate the diode chain of trigger voltage to trigger.
In order to solve the problems of the technologies described above, the invention provides the grid-control PIN junction electrostatic discharge protector that a kind of diode chain triggers, comprising: P type substrate, a n N-type well region and grid-control PIN junction, wherein, n is constant;
A described n N-type well region and described grid-control PIN junction are formed in described P type substrate;
A described n N-type well region is connected with input, and described grid-control PIN junction is arranged at the side that a described n N-type well region connects described input; 2nd N+ doped region is formed between described grid-control PIN junction and a described n N-type well region, and a N+ doped region is formed at the opposite side of described grid-control PIN junction, and a P+ doped region is formed on a described N+ doped region;
In a described n N-type well region, P+ doped region has identical relative position relation with N+ doped region.
Preferably, described grid-control PIN junction comprises P-type layer, N-type layer and I layer;
Described N-type layer is formed in described P type substrate, and described N-type layer is provided with channel region, and described P-type layer is formed in described channel region; Described I layer is formed in described P type substrate;
Described I layer contacts with described P-type layer, N-type layer.
Preferably, described I floor comprises oxide layer district and multi-crystal silicon area; Described oxide layer district is formed in described P type substrate, and described multi-crystal silicon area is formed in described oxide layer district.
Preferably, a described P+ doped region is by metal area ground connection, N+ doped region in n-th N-type well region is by metal area ground connection, and the N+ doped region of the previous N-type well region of two N-type well region that a described n N-type well region is adjacent is connected by metal area with the P+ doped region of a rear N-type well region.
Preferably, the 2nd P+ doped region in described 2nd N+ doped region and the first N-type well region is electrostatic input.
Preferably, the distance between a described n N-type well region is adjustable.
Technique scheme tool of the present invention has the following advantages: the problem being reduced the larger electric leakage that right side diode chain causes due to the existence of Darlington effect by the introducing being positioned at N-type well region front grid-control PIN junction, and suppress the increase of leaking electricity in the process that can rise in temperature, reduce quiescent dissipation; Replaced the number thus the object reaching adjustment trigger voltage that change diode by the distance changed between N-type well region, realize the increase adjustable basis of trigger voltage not being brought electric leakage.
Accompanying drawing explanation
Fig. 1 is the electrostatic discharge protector structural representation that traditional diode chain triggers;
Fig. 2 is the electrostatic discharge protector structural representation that the embodiment of the present invention provides;
Fig. 3 is the relation schematic diagram between the change diode number that provides of the embodiment of the present invention and trigger voltage, leakage current;
Fig. 4 is the relation schematic diagram between distance between the adjacent well region of change that the embodiment of the present invention provides and trigger voltage, leakage current;
Fig. 5 is the schematic diagram that electrostatic discharge protector that the embodiment of the present invention provides carries out DC test under 2.5V normal working voltage different temperatures.
In figure: 101:P type substrate; 201: the one N well regions; 202: the two N well regions; 203: the three N well regions; 204: the four N well regions; 205: the five N well regions; 301: the one N+ doped regions; 302: the two N+ doped regions; 303: the three N+ doped regions; 304: the four N+ doped regions; 305: the five N+ doped regions; 306: the six N+ doped regions; 307: the seven N+ doped regions; 401: the one P+ doped regions; 402: the two P+ doped regions; 403: the three P+ doped regions; 404: the four P+ doped regions; 405: the five P+ doped regions; 406: the six P+ doped regions; 501: oxide layer district; 502: multi-crystal silicon area; 601: the first metal areas; 602: the second metal areas; 603: the three metal areas; 604: the four metal areas; 605: the five metal areas; 606: the six metal areas; 607: the seven metal areas; 608: the eight metal areas; 609: the nine metal areas; 610: the ten metal areas; 611: the ten one metal areas; 612: the ten two metal areas.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples for illustration of the present invention, but are not used for limiting the scope of the invention.
As shown in Figure 2, be electrostatic discharge protector structural representation that the embodiment of the present invention provides.
This electrostatic discharge protector comprises: P type substrate 101, a n N-type well region and grid-control PIN junction, and wherein, n is constant; N N-type well region and grid-control PIN junction are formed in P type substrate 101; N N-type well region is connected with input V
eSD, grid-control PIN junction is arranged at n N-type well region and is connected with input V
eSDside; 2nd N+ doped region 302 is formed between PIN junction and n N-type well region, and a N+ doped region 301 is formed at the opposite side of grid-control PIN junction, and a P+ doped region 401 is formed on a N+ doped region 301; In n N-type well region, P+ doped region has identical relative position relation with N+ doped region.
Further, grid-control PIN junction comprises P-type layer, N-type layer and I layer; N-type layer is formed in P type substrate, and N-type layer is provided with channel region, and P-type layer is formed in channel region; I layer is formed in P type substrate; I layer contacts with P-type layer, N-type layer.Wherein, I floor comprises oxide layer district 501 and multi-crystal silicon area 502; Oxide layer district 501 is formed in P type substrate 101, and multi-crystal silicon area 502 is formed in oxide layer district 501.
Further, for n=5 in the embodiment of the present invention, as shown in Fig. 2 B-B cross section and C-C schematic cross-section, electrostatic discharge protector is made up of 5 N-type well region.Namely in the grid-control PIN junction electrostatic discharge protector that triggers of diode chain provided by the invention, the number of diode is 5, but not as limit, in diode chain, the number of diode adjusts according to the actual requirements.
Further, 5 N-type well region are formed in P type substrate 101, and grid-control PIN junction is formed on P type substrate 101; 4th N well region 204 is formed at the left side of the 5th N well region 205, and the 3rd N well region 203 is formed at the left side of the 4th N well region 204, and the 2nd N well region 202 is formed at the left side of the 3rd N well region 203, and a N well region 201 is formed at the left side of the 2nd N well region 202.
As shown in Figure 2 wherein, the 2nd P+ doped region 402 is formed at N well region the 201, a three N+ doped region 303 and is formed at a N well region 201, is formed on the right side of the 2nd P+ doped region 402; 3rd P+ doped region 403 is formed at the 2nd N well region the 202, four N+ doped region 304 and is formed at the 2nd N well region 202, is formed on the right side of the 3rd P+ doped region 403; 4th P+ doped region 404 is formed at the 3rd N well region the 203, five N+ doped region 305 and is formed at the 3rd N well region 203, is formed on the right side of the 4th P+ doped region 404; 5th P+ doped region 405 is formed at the 4th N well region the 204, six N+ doped region 306 and is formed at the 4th N well region 204, is formed at the 5th P+ doped region 405 right; 6th P+ doped region 406 is formed at the 5th N well region the 205, seven N+ doped region 307 and is formed at the 5th N well region 205, is formed on the right side of the 6th P+ doped region 406.
Further, the grid-control PIN junction being positioned at diode chain high order end is formed in P type substrate 101, is formed at the left side of a N well region 201.Grid-control PIN junction comprises oxide layer district 501 and multi-crystal silicon area 502, and oxide layer district 501 to be formed in P type substrate 101, and multi-crystal silicon area 502 is formed in oxide layer district 501.2nd N+ doped region 302 is formed between grid-control PIN junction and a N well region 201, and a N+ doped region 301 is formed at grid-control PIN junction high order end, and a P+ doped region 401 is formed on a N+ doped region 301.
Further, a P+ doped region 401 forms the first metal area 601; 2nd N+ doped region 302 is formed the second metal area 602; 2nd P+ doped region 402 forms the 3rd metal area 603; 3rd N+ doped region 303 forms the 4th metal area 604; 3rd P+ doped region 403 forms the 5th metal area 605; 4th N+ doped region 304 forms the 6th metal area 606; 4th P+ doped region 404 forms the 7th metal area 607; 5th N+ doped region 305 forms the 8th metal area 608; 5th P+ doped region 405 forms the 9th metal area 609; 6th N+ doped region 306 forms the tenth metal area 610; 6th P+ doped region 406 forms the 11 metal area 611; 7th N+ doped region 307 forms the 12 metal area 612.Wherein, the 3rd N+ doped region 303 in a N well region 201 and the 3rd P+ doped region 403 in the 2nd N well region 202, be connected by the 4th metal area 604 and the 5th metal area 605; The 4th N+ doped region 304 in 2nd N well region 202 and the 4th P+ doped region 404 in the 3rd N well region 203, be connected by the 6th metal area 606 and the 7th metal area 607; The 5th N+ doped region 305 in 3rd N well region 203 and the 5th P+ doped region 405 in the 4th N well region 204, be connected by the 8th metal area 608 and the 9th metal area 609; The 6th N+ doped region 306 in 4th N well region 204 and the 6th P+ doped region 406 in the 5th N well region 205, be connected by the tenth metal area, metal area the 610 and the 11 611.
Further, the 2nd N+ doped region 302 is by the second metal area 602 and input V
eSDbe connected, the 2nd P+ doped region 402 in a N well region 201 is by the 3rd metal area 603 and input V
eSDbe connected.One P+ doped region 401 is by the first metal area 601 ground connection, and the 7th N+ doped region 307 in the 5th N well region 205 is by the 12 metal area 612 ground connection.
Further, owing to there is a reverse PN junction between the 2nd N+ doped region 302 and P type substrate 101, the avalanche breakdown voltage of PN junction is higher than the cut-in voltage value required for the diode chain unlatching of right side, therefore before trigger voltage does not also reach its puncture voltage, the diode chain that 5, right side N-type well region is formed is opened.The cut-in voltage of diode chain determines the trigger voltage of whole ESD protective device, and the cut-in voltage size of diode chain can be regulated by the quantity changing diode simultaneously.Due to the existence of Darlington effect, when diode chain conducting, P type substrate 101 can be collected a large amount of electric currents and is used for triggering left side grid-control PIN junction, the ESD electric current that grid-control PIN junction can form low impedance path and then can release a large amount of after opening.But in order to meet the demand of different I/O, regulating the trigger voltage of electrostatic discharge protector both can be regulated by the number changing diode, also can be realized by the spacing changed between two N-type well region simultaneously.
Further, transmission line pulse (Transmission Line Pulse, TLP) method of testing simulating ESD strike effect is used to, according to the difference of ESD test model, rise time and the time of delay of transmission line pulse also can make corresponding change to simulate ESD strike effect really.The ESD test model chosen in the embodiment of the present invention is manikin (HBM), therefore the rise time choosing transmission line pulse is 10ns, and time of delay is 100ns.Its test data as shown in Figure 3 and Figure 4.As shown in Figure 3, Figure 4, be respectively the relation between change diode number that the embodiment of the present invention provides and trigger voltage, leakage current, and the distance changed between adjacent well region and trigger voltage, relation schematic diagram between leakage current.Can be found out by contrast: electrostatic discharge protector provided by the invention is by regulating the number of diode and regulating when diode number is constant spacing between two N-type well region effectively can regulate trigger voltage.But, regulate trigger voltage inevitably can attract the increase of electric leakage by regulating the number of diode.And diode number constant when can effectively regulate trigger voltage by the spacing size between change two N-type well region and don't cause the increase of electric leakage, as shown in Figure 4, regulate the distance between N-type well region, distance changes to 0.6um by 0.8um, changed to trigger voltage in the process of 0.4um more first to increase by 0.6um, rear reduction.And the increase of leakage current while regulating the spacing size between two N-type well region to regulate trigger voltage, can not be caused, extra quiescent dissipation can not be brought, thus do not attract extra static power consumption again on the basis meeting different I/O demand.
Further, the device provided the embodiment of the present invention carries out direct current (DC) test at different temperatures.Change to 105 DEG C of processes in temperature from 25 DEG C; be under the test condition of 2.5v in normal working voltage; the electric leakage of the ESD protective device that the embodiment of the present invention provides increases slowly along with the rising of temperature, thus achieve in temperature ramp de suppress electric leakage increase effect as shown in Figure 5.
In sum, the grid-control PIN junction electrostatic discharge protector that diode chain provided by the invention triggers reduces the problem of the larger electric leakage that right side diode chain causes due to the existence of Darlington effect by the introducing being positioned at N-type well region front grid-control PIN junction, and suppress the increase of leaking electricity in the process that can rise in temperature, reduce quiescent dissipation; Replaced the number thus the object reaching adjustment trigger voltage that change diode by the distance changed between N-type well region, realize the increase adjustable basis of trigger voltage not being brought electric leakage.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (6)
1. a grid-control PIN junction electrostatic discharge protector for diode chain triggering, it is characterized in that, comprising: P type substrate, a n N-type well region and grid-control PIN junction, wherein, n is constant;
A described n N-type well region and described grid-control PIN junction are formed in described P type substrate;
A described n N-type well region is connected with input, and described grid-control PIN junction is arranged at the side that a described n N-type well region connects described input; 2nd N+ doped region is formed between described grid-control PIN junction and a described n N-type well region, and a N+ doped region is formed at the opposite side of described grid-control PIN junction, and a P+ doped region is formed on a described N+ doped region;
In a described n N-type well region, P+ doped region has identical relative position relation with N+ doped region.
2. the grid-control PIN junction electrostatic discharge protector of diode chain triggering according to claim 1, it is characterized in that, described grid-control PIN junction comprises P-type layer, N-type layer and I layer;
Described N-type layer is formed in described P type substrate, and described N-type layer is provided with channel region, and described P-type layer is formed in described channel region; Described I layer is formed in described P type substrate;
Described I layer contacts with described P-type layer, N-type layer.
3. the grid-control PIN junction electrostatic discharge protector of diode chain triggering according to claim 2, it is characterized in that, described I floor comprises oxide layer district and multi-crystal silicon area; Described oxide layer district is formed in described P type substrate, and described multi-crystal silicon area is formed in described oxide layer district.
4. the grid-control PIN junction electrostatic discharge protector of diode chain triggering according to claim 1; it is characterized in that; a described P+ doped region is by metal area ground connection; N+ doped region in n-th N-type well region is by metal area ground connection, and the N+ doped region of the previous N-type well region of two N-type well region that a described n N-type well region is adjacent is connected by metal area with the P+ doped region of a rear N-type well region.
5. the grid-control PIN junction electrostatic discharge protector that triggers of diode chain according to claim 1 and 2, is characterized in that, the 2nd P+ doped region in described 2nd N+ doped region and the first N-type well region is electrostatic input.
6. the grid-control PIN junction electrostatic discharge protector of diode chain triggering according to claim 1 and 2, it is characterized in that, the distance between a described n N-type well region is adjustable.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112133757A (en) * | 2020-10-07 | 2020-12-25 | 西安电子科技大学 | Gate-controlled gallium oxide field effect transistor based on p-i-n structure and preparation method thereof |
| CN114914324A (en) * | 2021-02-09 | 2022-08-16 | 爱思开海力士有限公司 | Single photon avalanche diode |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040212936A1 (en) * | 2002-09-27 | 2004-10-28 | Salling Craig T. | Diode-string substrate-pumped electrostatic discharge protection |
| CN103094273A (en) * | 2011-10-31 | 2013-05-08 | 旺宏电子股份有限公司 | Electrostatic discharge protective element |
| US20140342515A1 (en) * | 2010-11-03 | 2014-11-20 | Texas Instruments Incorporated | Esd protection using diode-isolated gate-grounded nmos with diode string |
-
2015
- 2015-01-23 CN CN201510037402.3A patent/CN104952868B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040212936A1 (en) * | 2002-09-27 | 2004-10-28 | Salling Craig T. | Diode-string substrate-pumped electrostatic discharge protection |
| US20140342515A1 (en) * | 2010-11-03 | 2014-11-20 | Texas Instruments Incorporated | Esd protection using diode-isolated gate-grounded nmos with diode string |
| CN103094273A (en) * | 2011-10-31 | 2013-05-08 | 旺宏电子股份有限公司 | Electrostatic discharge protective element |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112133757A (en) * | 2020-10-07 | 2020-12-25 | 西安电子科技大学 | Gate-controlled gallium oxide field effect transistor based on p-i-n structure and preparation method thereof |
| CN112133757B (en) * | 2020-10-07 | 2022-03-04 | 西安电子科技大学 | Gate-controlled gallium oxide field effect transistor based on p-i-n structure and preparation method thereof |
| CN114914324A (en) * | 2021-02-09 | 2022-08-16 | 爱思开海力士有限公司 | Single photon avalanche diode |
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