CN103872039A - Electrostatic discharge protection circuit and manufacturing method thereof - Google Patents

Electrostatic discharge protection circuit and manufacturing method thereof Download PDF

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Publication number
CN103872039A
CN103872039A CN201210530228.2A CN201210530228A CN103872039A CN 103872039 A CN103872039 A CN 103872039A CN 201210530228 A CN201210530228 A CN 201210530228A CN 103872039 A CN103872039 A CN 103872039A
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doped
metal
amber ear
ggnmos
ggnmos transistor
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CN201210530228.2A
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Chinese (zh)
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CN103872039B (en
Inventor
甘正浩
冯军宏
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中芯国际集成电路制造(上海)有限公司
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    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention discloses an electrostatic discharge protection circuit. The electrostatic discharge protection circuit comprises a gate-grounded N type metal oxide semiconductor (GGNMOS) transistor located on a semiconductor substrate, a drain electrode of the GGNMOS transistor is connected an input/output end of a chip circuit, a source electrode and a gate electrode and the semiconductor substrate are all connected to the ground; and the circuit also comprises a Peltier cooling element that is located near the GGNMOS transsitor and used for absorbing heat generated by the GGNMOS transistor. The invention also discloses a manufacturing method of the electrostatic discharge protection circuit. By adoption of the electrostatic discharge protection circuit, the working life of an ESD protection device can be prolonged.

Description

ESD protection circuit and preparation method thereof

Technical field

The present invention relates to integrated circuit and manufacture field, particularly a kind of ESD protection circuit and preparation method thereof.

Background technology

In integrated circuit (IC) chip manufacturing and final application system, along with improving constantly of very lagre scale integrated circuit (VLSIC) technology, CMOS (Complementary Metal Oxide Semiconductor) pipe (CMOS) integrated circuit has entered the sub-micro stage at present, the size of MOS device is constantly dwindled, static discharge (Electrostatic Discharge, ESD) becomes more and more significant to the harm of integrated circuit.According to statistics, in the product of ic failure, have 35% to be because ESD problem is caused.Therefore, integrated circuit is carried out to esd protection design and also become particularly important.

In the time using device to carry out esd protection to integrated circuit, conventional device is grounded-grid NMOS pipe (GGNMOS), controllable silicon (Silicon Controlled Rectifier, SCR), diode etc.Wherein because GGNMOS and integrated circuit CMOS technique are well compatible, and be widely adopted.Fig. 1 is the existing GGNMOS device semiconductor structure chart for esd protection circuit.Fig. 2 is the GGNMOS device equivalent circuit diagram for esd protection circuit corresponding with Fig. 1.As depicted in figs. 1 and 2, this GGNMOS device comprises P type substrate 100; Be positioned at the grid 101 on P type substrate 100 surfaces; The source electrode 102 and the drain electrode 103 that lay respectively in grid 101 both sides substrates, doping type are N-type.In above-mentioned GGNMOS device, comprise that one by source electrode 102 and drain electrode 103, and the parasitic NPN triode that forms of substrate 100 between the two.Wherein, drain electrode 103 as collector electrode, source electrode 102 as emitter, substrate 100 as base stage.P type substrate 100, source electrode 102 and grid 101 are all connected to ground wire GND, and drain electrode 103 are connected to the input/output terminal (I/O) of power line VDD and chip circuit.Due to grid 101 and P type substrate 100 ground connection, GGNMOS device cannot be opened formation conducting channel all the time.In the time that the current potential on power line VDD is positioned at normal operating state, GGNMOS device is closed, and parasitic NPN triode wherein can conducting yet; While causing transient potential too high when being subject to ESD electrostatic pulse on power line VDD; to trigger GGNMOS device endoparasitism NPN triode generation current; make conducting between power line VDD and ground wire GND; the instantaneous large-current that ESD electrostatic pulse produces will flow away by above-mentioned parasitic NPN triode rapidly, thereby reaches the object of protecting internal circuit to be subject to ESD electrostatic impact.After ESD electrostatic pulse disappears, above-mentioned parasitic NPN triode is closed, and can not impact the normal work of protected internal circuit.

It should be noted that when GGNMOS is in moment during by large electric current, can produce a large amount of heats and GGNMOS is burnt out, make it lose esd protection ability, therefore, how to extend the working life of GGNMOS, protective circuit better, becomes and needs the problem that solves.

Summary of the invention

In view of this, the invention provides a kind of ESD protection circuit and preparation method thereof, can extend the working life of esd protection device.

Technical scheme of the present invention is achieved in that

The invention provides a kind of ESD protection circuit, comprise the grounded-grid N-type metal-oxide semiconductor (MOS) ggnmos transistor being positioned in Semiconductor substrate, the drain electrode of described ggnmos transistor connects the input/output terminal of chip circuit, the equal ground connection of source electrode and grid and Semiconductor substrate; This circuit also comprises and being positioned near described ggnmos transistor, for absorbing the amber ear note cooling element of the heat that described ggnmos transistor produces.

Described amber ear note cooling element is thermocouple, this thermocouple comprises N doped portion and P doped portion, and the metal of connection N doped portion and P doped portion, one end not being connected with metal at N doped portion has the first contact electrode, has the second contact electrode in one end not being connected with metal of P doped portion.

Described amber ear note cooling element is in parallel with described ggnmos transistor, and described the first contact electrode is connected with the drain electrode of ggnmos transistor, and described the second contact electrode is connected with ground.

Described the first contact electrode is connected with the drain electrode of ggnmos transistor, and described the second contact electrode is connected with chip circuit.

Described ggnmos transistor is to refer to ggnmos transistor in parallel more.

The metal of described connection N doped portion and P doped portion is copper or aluminium.

The present invention also provides a kind of manufacture method of ESD protection circuit, and the method comprises:

One grounded-grid N-type metal-oxide semiconductor (MOS) ggnmos transistor is provided, and described ggnmos transistor at least comprises the grid that is positioned at semiconductor substrate surface, grid both sides substrate is interior, doping type is N-type source electrode and drain electrode; In forming described source electrode and drain electrode, the redundant area in Semiconductor substrate forms N doped portion and the P doped portion of amber ear note cooling element;

Form intermetallic interconnection layer on ggnmos transistor surface, in described intermetallic interconnection layer, there is the connecting hole that is filled with metal;

Surface at described intermetallic interconnection layer forms interlayer dielectric layer, has the groove or the connecting hole that are filled with metal in described interlayer dielectric layer; When formation is filled with the groove or connecting hole of metal, form the connection N doped portion of amber ear note cooling element and the metal of P doped portion with layer, the metal of described connection N doped portion and P doped portion with described in be filled with between the groove of metal or connecting hole and insulate by interlayer dielectric layer, and by N doped portion and the electric connection of P doped portion of connecting hole and amber ear note cooling element;

The drain electrode of described ggnmos transistor is connected to the input/output terminal of chip circuit, the equal ground connection of source electrode and grid and Semiconductor substrate; By described amber ear note cooling element place in circuit.

The method of described amber ear note cooling element place in circuit is comprised:

Described amber ear note cooling element is connected with the drain electrode of described ggnmos transistor by the first contact electrode in one end not being connected with metal of N doped portion, described amber ear note cooling element is connected with ground by the second contact electrode in one end not being connected with metal of P doped portion.

The method of described amber ear note cooling element place in circuit is comprised:

Described amber ear note cooling element is connected with the drain electrode of described ggnmos transistor by the first contact electrode in one end not being connected with metal of N doped portion, described amber ear note cooling element is connected with chip circuit by the second contact electrode in one end not being connected with metal of P doped portion.

Can find out from such scheme; ESD protection circuit of the present invention has increased amber ear note cooling element on the basis of GGNMOS structure; this amber ear note cooling element is thermocouple, and this thermocouple comprises N doped portion and P doped portion, and connects the metal of N doped portion and P doped portion.Amber ear note cooling element is positioned near of GGNMOS structure; in the time that transient current is very large; also have electric current by this amber ear note cooling element; it can be led away the heat of GGNMOS structure generation in time; be unlikely to GGNMOS structure to burn out; thereby the working life that has extended esd protection device, reaches object of the present invention.

Brief description of the drawings

Fig. 1 is the existing GGNMOS device semiconductor structure chart for esd protection circuit.

Fig. 2 is the GGNMOS device equivalent circuit diagram for esd protection circuit corresponding with Fig. 1.

Fig. 3 is the amber ear note cooling element schematic diagram forming according to peltier effect.

Fig. 4 is the equivalent circuit diagram of first embodiment of the invention ESD protection circuit.

Fig. 5 is ESD protection circuit semiconductor structure generalized section of the present invention.

Fig. 6 is first embodiment of the invention ESD protection circuit semiconductor structure schematic top plan view.

Fig. 7 is the equivalent circuit diagram of second embodiment of the invention ESD protection circuit.

Fig. 8 is second embodiment of the invention ESD protection circuit semiconductor structure schematic top plan view.

Embodiment

For making object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.

Core concept of the present invention is exactly in the esd protection circuit with ggnmos transistor, to have added amber ear note cooling element; amber ear note cooling element is positioned near of ggnmos transistor, and amber ear note cooling element is passing into the effect that can reach cooling ggnmos transistor after electric current.Simply introduce the application background of amber ear note cooling element below.

That flow through connection when electric current and while remaining on two kinds of different conductors under uniform temperature, except Joule heat, also produce radiation or absorb heat.This effect is the phenomenon of first being found by J.C.A.Peltier in 1834, and is called peltier effect.The amber ear note cooling element schematic diagram forming according to peltier effect as shown in Figure 3.This amber ear note cooling element comprises N doped portion 5 and P doped portion 6, and the metal 10 of connection N doped portion and P doped portion, there is the first contact electrode 11 in one end not being connected with metal of N doped portion, there is the second contact electrode 12 in one end not being connected with metal of P doped portion.In the time that electric current flows to P from N; the temperature that connects the metal 10 of N doped portion and P doped portion declines; the temperature rise at the first contact electrode 11 and the second contact electrode 12 places; the metal 10 that the present invention utilizes temperature to decline just; cooling ggnmos transistor, makes ggnmos transistor in the time that transient current is excessive, plays protective circuit effect; be unlikely to again heat too high and be burned, thereby reach object of the present invention.

The equivalent circuit diagram of first embodiment of the invention ESD protection circuit as shown in Figure 4.Amber ear note cooling element 401 is in parallel with ggnmos transistor 402.Wherein, the drain electrode 1 of ggnmos transistor 402 connects the input/output terminal of chip circuit, source electrode 2 and grid 3 and the equal ground connection of Semiconductor substrate 4; The N doped portion of amber ear note cooling element 401 is connected to the drain electrode 1 of ggnmos transistor 402 by the first contact electrode (not shown), the P doped portion of amber ear note cooling element 401 is connected with ground by the second contact electrode (not shown).

The manufacture method of embodiment of the present invention ESD protection circuit; comprise the following steps; below in conjunction with the ESD protection circuit semiconductor structure generalized section of Fig. 5, and the ESD protection circuit semiconductor structure schematic top plan view of Fig. 6 is elaborated.

Step 41, provide a grounded-grid N-type metal-oxide semiconductor (MOS) ggnmos transistor, described ggnmos transistor at least comprises the grid 3 that is positioned at Semiconductor substrate 4 surfaces, in grid 3 both sides substrates, doping type be N-type source electrode 2 and drain electrode 1; In forming described source electrode 2 and drain electrode 1, the redundant area in Semiconductor substrate forms N doped portion 5 and the P doped portion 6 of amber ear note cooling element;

Formation for ggnmos transistor does not repeat them here, and ggnmos transistor is arranged in active area, keeps apart each active area by shallow channel isolation area (STI).Semiconductor substrate 4 is P type substrate, can be monocrystalline silicon, polysilicon, carborundum or silicon Germanium compound etc.Because the effective electronics of NMOS is as majority carrier, so the source electrode of NMOS pipe and drain electrode are N-type, inject N-type element boron fluoride (BF 2) or boron (B) etc.In Semiconductor substrate being carried out to Implantation formation source-drain electrode, there is not the position of function element at semiconductor substrate surface, it is redundant area, also carry out the N doped portion 5 of N-type Implantation formation amber ear note cooling element, the P doped portion 6 that carries out P type Implantation formation amber ear note cooling element in another redundant area, the P type element of injection is phosphorus (P) or arsenic (As) etc.

Step 42, form intermetallic interconnection layer 7 on ggnmos transistor surface, in described intermetallic interconnection layer 7, there is the connecting hole 8 that is filled with metal;

In order to clearly demonstrate amber ear note cooling element of the present invention, in Fig. 5, only show the connecting hole 8 being electrically connected with N doped portion 5 and the P doped portion 6 of amber ear note cooling element, the connecting hole of other and grid, source electrode and drain electrode UNICOM does not all illustrate.This step is to make the fundamental technology of metal interconnecting layer, has just made the connecting hole being electrically connected with N doped portion 5 and the P doped portion 6 of amber ear note cooling element simultaneously.

Step 43, form interlayer dielectric layer 9 on the surface of described intermetallic interconnection layer 7, in described interlayer dielectric layer 9, there is the groove or the connecting hole that are filled with metal; When formation is filled with the groove or connecting hole of metal, form the connection N doped portion 5 of amber ear note cooling element and the metal 10 of P doped portion 6 with layer, the metal 10 of described connection N doped portion and P doped portion with described in be filled with between the groove of metal or connecting hole and insulate by interlayer dielectric layer 9, and be electrically connected by N doped portion 5 and the P doped portion 6 of connecting hole 8 and amber ear note cooling element.

This step is to make the fundamental technology of metal interconnecting layer, has just made the connection N doped portion 5 of amber ear note cooling element and the metal 10 of P doped portion 6 simultaneously.It should be noted that, metal 10 forms with layer with the groove or the connecting hole that are filled with metal, metal 10 requires and is filled with between the groove of metal or connecting hole keeps apart, and metal 10 will be electrically connected with the connecting hole of lower floor 8, can find out from the vertical view of Fig. 6.The metal of filling in above-mentioned connecting hole or groove is copper or aluminium etc.

Step 44, the drain electrode of described ggnmos transistor 1 is connected to the input/output terminal of chip circuit, source electrode 2 and grid 3 and the equal ground connection of Semiconductor substrate 4; By described amber ear note cooling element place in circuit; Wherein, the method of described amber ear note cooling element place in circuit is comprised: described amber ear note cooling element is connected with the drain electrode 1 of described ggnmos transistor by the first contact electrode 11 in one end not being connected with metal of N doped portion, described amber ear note cooling element is connected with ground by the second contact electrode 12 in one end not being connected with metal of P doped portion.

This embodiment specific works principle is as follows:

In the time that ESD occurs, electric current flows through ggnmos transistor 402 and Po Er note cooling element 401 simultaneously, the connection N doped portion 5 of amber ear note cooling element 401 and the metal of P doped portion 6 10 temperature decline, because ggnmos transistor 402 and Po Er note cooling element 401 distances are very near, the temperature declining passes to ggnmos transistor 402 by dielectric layer, the heat that large electric current that ggnmos transistor 402 flows through in the time that ESD occurs produces is rapidly absorbed, is unlikely to ggnmos transistor 402 to burn out.

In addition, in order to improve the resistance ESD ability of GGNMOS device, conventionally can adopt and refer to GGNMOS structure in parallel more, be that multiple GGNMOS are connected in parallel, but this how finger parallel-connection structure can cause non-uniform Trigger Problems: the dead resistance in the leakage path of middle NMOS is larger than the dead resistance in NMOS leakage path around, in the time that the upper generation of power line VDD electrostatic breakdown causes potential rise, middle NMOS is always prior to other NMOS conductings, not only make above-mentionedly to refer to that the conducting homogeneity of GGNMOS structure in parallel is very poor more, and can be burned too greatly due to the heat that middle NMOS produces, make wholely to refer to that GGNMOS structure in parallel loses esd protection ability more.Therefore, amber ear note cooling element 401 of the present invention, its metal 10 that connects N doped portion 5 and P doped portion 6 also can be around these many fingers GGNMOS structure in parallel, and the heat that the NMOS in the middle of effectively absorbing produces, improves the conducting homogeneity that refers to GGNMOS structure in parallel more.

The equivalent circuit diagram of second embodiment of the invention ESD protection circuit as shown in Figure 7.Wherein, the drain electrode 1 of ggnmos transistor 402 connects the input/output terminal of chip circuit, source electrode 2 and grid 3 and the equal ground connection of Semiconductor substrate 4; The N doped portion of amber ear note cooling element 401 is connected to the drain electrode 1 of ggnmos transistor 402 by the first contact electrode (not shown), the P doped portion of amber ear note cooling element 401 is connected with chip circuit by the second contact electrode (not shown).

The manufacture method of ESD protection circuit in this embodiment, basic identical with the first embodiment, when difference is amber ear note cooling element 401 place in circuit, P doped portion is connected with chip circuit by the second contact electrode 12.Second embodiment of the invention ESD protection circuit semiconductor structure schematic top plan view as shown in Figure 8.

This embodiment specific works principle is as follows:

In the time that ESD occurs, electric current flows through ggnmos transistor 402, but unavoidably also have little electric current and flow through amber ear note cooling element 401, at this moment amber ear note cooling element 401 is started working, the connection N doped portion 5 of amber ear note cooling element 401 and the metal of P doped portion 6 10 temperature decline, because ggnmos transistor 402 and Po Er note cooling element 401 distances are very near, the temperature declining passes to ggnmos transistor 402 by dielectric layer, the heat that large electric current that ggnmos transistor 402 flows through in the time that ESD occurs produces is rapidly absorbed, be unlikely to ggnmos transistor 402 to burn out.In like manner; also can in the protective circuit of this embodiment, apply and refer to GGNMOS structure in parallel more; amber ear note cooling element 401; its metal 10 that connects N doped portion 5 and P doped portion 6 is around these many fingers GGNMOS structure in parallel; the heat that NMOS in the middle of effectively absorbing produces, improves the conducting homogeneity that refers to GGNMOS structure in parallel more.

Above-mentioned two embodiment list amber ear note cooling element and are connected to two modes in protective circuit; protection of the present invention is not limited to this; as long as amber ear note cooling element 401 can pass into electric current; and be positioned near of ggnmos transistor; its metal 10 that connects N doped portion 5 and P doped portion 6 is around this ggnmos transistor, the heat producing while effectively absorbing ggnmos transistor by electric current.

By ESD protection circuit of the present invention; utilize amber ear note cooling element to pass into the principle that temperature declines after electric current; this amber ear note cooling element is arranged on near of ggnmos transistor, the heat producing for absorbing ggnmos transistor, thus reach object of the present invention.On the other hand, the embodiment of the present invention, in the time making ESD protection circuit, has been utilized the production process of existing technique, for example, in making source-drain electrode, make N doped portion and the P doped portion of amber ear note cooling element; In making metal interconnecting layer, make the connection N doped portion of amber ear note cooling element and the metal of P doped portion, make manufacture method be simple and easy to realize.

The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any amendment of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.

Claims (9)

1. an ESD protection circuit, comprise the grounded-grid N-type metal-oxide semiconductor (MOS) ggnmos transistor being positioned in Semiconductor substrate, the drain electrode of described ggnmos transistor connects the input/output terminal of chip circuit, the equal ground connection of source electrode and grid and Semiconductor substrate; It is characterized in that, this circuit also comprises and being positioned near described ggnmos transistor, for absorbing the amber ear note cooling element of the heat that described ggnmos transistor produces.
2. ESD protection circuit as claimed in claim 1; it is characterized in that; described amber ear note cooling element is thermocouple; this thermocouple comprises N doped portion and P doped portion; and the metal of connection N doped portion and P doped portion; one end not being connected with metal at N doped portion has the first contact electrode, has the second contact electrode in one end not being connected with metal of P doped portion.
3. ESD protection circuit as claimed in claim 2, is characterized in that, described amber ear note cooling element is in parallel with described ggnmos transistor, and described the first contact electrode is connected with the drain electrode of ggnmos transistor, and described the second contact electrode is connected with ground.
4. ESD protection circuit as claimed in claim 2, is characterized in that, described the first contact electrode is connected with the drain electrode of ggnmos transistor, and described the second contact electrode is connected with chip circuit.
5. the ESD protection circuit as described in claim 2,3 or 4, is characterized in that, described ggnmos transistor is to refer to ggnmos transistor in parallel more.
6. ESD protection circuit as claimed in claim 5, is characterized in that, the metal of described connection N doped portion and P doped portion is copper or aluminium.
7. a manufacture method for ESD protection circuit, the method comprises:
One grounded-grid N-type metal-oxide semiconductor (MOS) ggnmos transistor is provided, and described ggnmos transistor at least comprises the grid that is positioned at semiconductor substrate surface, grid both sides substrate is interior, doping type is N-type source electrode and drain electrode; In forming described source electrode and drain electrode, the redundant area in Semiconductor substrate forms N doped portion and the P doped portion of amber ear note cooling element;
Form intermetallic interconnection layer on ggnmos transistor surface, in described intermetallic interconnection layer, there is the connecting hole that is filled with metal;
Surface at described intermetallic interconnection layer forms interlayer dielectric layer, has the groove or the connecting hole that are filled with metal in described interlayer dielectric layer; When formation is filled with the groove or connecting hole of metal, form the connection N doped portion of amber ear note cooling element and the metal of P doped portion with layer, the metal of described connection N doped portion and P doped portion with described in be filled with between the groove of metal or connecting hole and insulate by interlayer dielectric layer, and by N doped portion and the electric connection of P doped portion of connecting hole and amber ear note cooling element;
The drain electrode of described ggnmos transistor is connected to the input/output terminal of chip circuit, the equal ground connection of source electrode and grid and Semiconductor substrate; By described amber ear note cooling element place in circuit.
8. method as claimed in claim 7, is characterized in that, the method for described amber ear note cooling element place in circuit is comprised:
Described amber ear note cooling element is connected with the drain electrode of described ggnmos transistor by the first contact electrode in one end not being connected with metal of N doped portion, described amber ear note cooling element is connected with ground by the second contact electrode in one end not being connected with metal of P doped portion.
9. method as claimed in claim 7, is characterized in that, the method for described amber ear note cooling element place in circuit is comprised:
Described amber ear note cooling element is connected with the drain electrode of described ggnmos transistor by the first contact electrode in one end not being connected with metal of N doped portion, described amber ear note cooling element is connected with chip circuit by the second contact electrode in one end not being connected with metal of P doped portion.
CN201210530228.2A 2012-12-11 2012-12-11 The manufacture method of ESD protection circuit CN103872039B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990331A (en) * 2015-02-02 2016-10-05 中芯国际集成电路制造(上海)有限公司 Electrostatic discharge protection structure and electronic device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010029084A1 (en) * 2000-02-28 2001-10-11 Gauthier Robert J. Thermal conductivity enhanced semiconductor structures and fabrication processes
CN1378280A (en) * 2001-03-29 2002-11-06 华邦电子股份有限公司 Static discharge protective semiconductor device
CN1873978A (en) * 2005-03-23 2006-12-06 英飞凌科技股份公司 Electrostatic discharge protection process and device for the improvement of a semiconductor circuit
CN101834184A (en) * 2010-03-23 2010-09-15 浙江大学 Substrate-triggered GGNMOS (Grounded-Grid N-Metal-Oxide-Semiconductor) tube
CN101847644A (en) * 2009-03-24 2010-09-29 索尼公司 Semiconductor device
CN101866922A (en) * 2010-05-12 2010-10-20 上海宏力半导体制造有限公司 GGNMOS device used in ESD protective circuit
CN101971380A (en) * 2008-09-03 2011-02-09 奥斯兰姆奥普托半导体有限责任公司 Optoelectronic component

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010029084A1 (en) * 2000-02-28 2001-10-11 Gauthier Robert J. Thermal conductivity enhanced semiconductor structures and fabrication processes
CN1378280A (en) * 2001-03-29 2002-11-06 华邦电子股份有限公司 Static discharge protective semiconductor device
CN1873978A (en) * 2005-03-23 2006-12-06 英飞凌科技股份公司 Electrostatic discharge protection process and device for the improvement of a semiconductor circuit
CN101971380A (en) * 2008-09-03 2011-02-09 奥斯兰姆奥普托半导体有限责任公司 Optoelectronic component
CN101847644A (en) * 2009-03-24 2010-09-29 索尼公司 Semiconductor device
CN101834184A (en) * 2010-03-23 2010-09-15 浙江大学 Substrate-triggered GGNMOS (Grounded-Grid N-Metal-Oxide-Semiconductor) tube
CN101866922A (en) * 2010-05-12 2010-10-20 上海宏力半导体制造有限公司 GGNMOS device used in ESD protective circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990331A (en) * 2015-02-02 2016-10-05 中芯国际集成电路制造(上海)有限公司 Electrostatic discharge protection structure and electronic device
CN105990331B (en) * 2015-02-02 2019-04-09 中芯国际集成电路制造(上海)有限公司 A kind of ESD-protection structure and electronic device

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