CN102544066B - Bidirectional controllable silicon device based on assistant triggering of NPN-type triodes - Google Patents
Bidirectional controllable silicon device based on assistant triggering of NPN-type triodes Download PDFInfo
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- CN102544066B CN102544066B CN201210060437.5A CN201210060437A CN102544066B CN 102544066 B CN102544066 B CN 102544066B CN 201210060437 A CN201210060437 A CN 201210060437A CN 102544066 B CN102544066 B CN 102544066B
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Abstract
The invention discloses a bidirectional controllable silicon device based on the assistant triggering of NPN-type triodes. The bidirectional controllable silicon device comprises a P substrate layer and four NPN-type triodes, wherein a first N trap, a P trap and a second N trap are arranged on the P substrate layer; a first N+ active injection region, a first P+ active injection region and a second N+ active injection region are arranged on the first N trap; a third N+ active injection region, a second P+ active injection region and a fourth N+ active injection region are arranged on the second N trap; the third N+ active injection region is connected with the second NPN-type triode; the first NPN-type triode is connected with a first metal electrode; the second N+ active injection region is connected with the third NPN-type triode; and the fourth NPN-type triode is connected with a second metal electrode. According to the controllable silicon device, the NPN-type triodes are used as assistant triggering units, so that the device has adjustable and relatively low positive and negative breakdown voltage, and can be suitable for electrostatic discharging (ESD) protection application in some hybrid voltage interface circuits.
Description
Technical field
The invention belongs to integrated circuit electrostatic defending technical field, be specifically related to a kind of bidirectional triode thyristor device based on NPN type triode auxiliary triggering.
Background technology
Natural static discharge (ESD) phenomenon has formed serious threat to the reliability of integrated circuit.In industrial quarters, the inefficacy 30% of integrated circuit (IC) products is all owing to suffering static discharge phenomenon caused, and more and more less process, and the probability that thinner gate oxide thickness all makes integrated circuit be subject to static discharge destruction increases greatly.Therefore, the reliability of improving integrated circuit electrostatic discharge protection has very important effect to the rate of finished products that improves product.
The pattern of static discharge phenomenon is divided into four kinds usually: HBM (human-body model), MM (machine discharge mode), CDM (assembly charging and discharging pattern) and electric field induction pattern (FIM).And the most common two kinds of static discharge patterns that are also the industrial quarters product must pass through are HBM and MM.When static discharge occurs, electric charge usually flows into and flows out from the another pin from a pin of chip, and the electric current that now electrostatic charge produces is usually up to several amperes, and the voltage produced at the electric charge input pin is up to even tens volts of several volts.Can cause the damage of inside chip if larger ESD electric current flows into inside chip, simultaneously, the high pressure produced at input pin also can cause internal components generation grid oxygen punch-through, thereby causes circuit malfunction.Therefore, in order to prevent inside chip, damaged by ESD, to each pin of chip, will carry out effective ESD protection, the ESD electric current is released.
In the evolution of ESD protection, the devices such as diode, GGNMOS (the NMOS pipe of grid ground connection), SCR (controllable silicon) are used as the ESD protective unit usually.For modern CMOS (complementary metal oxide semiconductors (CMOS)) integrated circuit, the input of chip output usually with the input buffer stage the grid of output buffer stage or MOS device as input.Therefore, when esd event occurs, ESD stress can be applied directly on grid oxygen, if the ESD device opens not prompt enough or clamping voltage is too high, grid oxygen punch-through probably occurs, thereby chip is damaged.
Because having to hang down, unidirectional SCR structure maintains the characteristics such as voltage, high current drain ability, so unidirectional SCR structure has very wide application in the ESD protection.
Fig. 1 is the unidirectional SCR structure under a kind of CMOS technique, this unidirectional SCR trigger voltage in one direction is higher, and on another direction, be the parasitic diode structure, trigger voltage is very low and non-adjustable, therefore, this structure is difficult to ESD protection on direct application sheet, especially can not be applied in the mixed-voltage domain interface circuit ESD protection that the two-way trigger voltage of ask for something is adjustable and lower.
Fig. 2 is the two-way SCR structure under a kind of CMOS technique, and this structure is compared unidirectional SCR structure, at both direction, all has identical trigger voltage, but trigger voltage value is same too high and non-adjustable, under deep submicron process, is difficult to protect fragile grid oxygen.
Summary of the invention
For the existing above-mentioned technological deficiency of prior art, the invention discloses a kind of bidirectional triode thyristor device based on NPN type triode auxiliary triggering, make controllable silicon there is two-way adjustable and lower trigger voltage on both direction, can directly apply to the ESD protection of some the mixed-voltage interface circuits under deep submicron process.
A kind of bidirectional triode thyristor device based on NPN type triode auxiliary triggering comprises:
P substrate layer and four NPN type triodes;
From left to right be provided with successively a N trap, P trap and the 2nd N trap on described P substrate layer, described P trap is connected with the 2nd N trap side by side with a N trap;
From left to right be provided with side by side successively an active injection region of N+, an active injection region of P+ and the 2nd active injection region of N+ on a described N trap; From left to right be provided with side by side successively the 3rd active injection region of N+, the 2nd active injection region of P+ and the 4th active injection region of N+ on described the 2nd N trap;
A described active injection region of N+ is connected by the first metal electrode with an active injection region of P+, and described the 2nd active injection region of P+ is connected by the second metal electrode with the 4th active injection region of N+;
Described the 3rd active injection region of N+ is connected with the collector electrode of the 2nd NPN type triode, and the emitter of a NPN type triode is connected with the first metal electrode; Described the 2nd active injection region of N+ is connected with the collector electrode of the 3rd NPN type triode, and the emitter of the 4th NPN type triode is connected with the second metal electrode; Base stage, the emitter four of the base stage of the one NPN type triode, collector electrode and the 2nd NPN type triode connect extremely altogether, and base stage, the collector electrode four of the base stage of the 3rd NPN type triode, emitter and the 4th NPN type triode connect extremely altogether.
Shallow-trench isolation is passed through in a described active injection region of N+ and an active injection region of P+, an active injection region of P+ and the 2nd active injection region of N+, the 2nd active injection region of N+ and the 3rd active injection region of N+, the 3rd active injection region of N+ and the 2nd active injection region of P+ or the 2nd active injection region of P+ and the 4th active injection region of N+.
The equivalent electric circuit of described silicon-controlled device consists of four resistance, three triodes and four NPN type triodes; Wherein, one end of the emitter of the first triode and the first resistance and the emitter of a NPN type triode are connected and form the first electrode of silicon-controlled device, base stage is connected with the other end of the first resistance, the collector electrode of the 3rd NPN type triode and emitter or the collector electrode of the 3rd triode, and collector electrode is connected with an end of the 3rd resistance; One end of the emitter of the second triode and the second resistance and the emitter of the 4th NPN type triode are connected and form the second electrode of silicon-controlled device, base stage is connected with the other end of the second resistance, the collector electrode of the 2nd NPN type triode and collector electrode or the emitter of the 3rd triode, and collector electrode is connected with an end of the 4th resistance; The base stage of the 3rd triode is connected with the other end of the 4th resistance with the other end of the 3rd resistance; Base stage, the emitter four of the base stage of the one NPN type triode, collector electrode and the 2nd NPN type triode connect extremely altogether, and base stage, the collector electrode four of the base stage of the 3rd NPN type triode, emitter and the 4th NPN type triode connect extremely altogether.
Described the first triode and the second triode are the positive-negative-positive triode, and described the 3rd triode is NPN type triode.
Described the first triode consists of a described active injection region of P+, a N trap and P trap; Described the second triode consists of described the 2nd active injection region of P+, the 2nd N trap and P trap; Described the 3rd triode consists of a N trap, the 2nd N trap and P trap; The dead resistance that described the first resistance and the 3rd resistance are a N trap; The dead resistance that described the second resistance and the 4th resistance are the 2nd N trap.
The protection voltage range of silicon-controlled device of the present invention can reach (1.2～5) V, and trigger voltage is (5～12) V.
Silicon-controlled device of the present invention utilizes NPN type triode as the auxiliary triggering unit, makes device have adjustable and lower trigger voltage, realizes the ESD protection of low trigger voltage; This silicon-controlled device has two-way forward and reverse puncture voltage simultaneously, makes device applicable to ESD protection on the sheet under deep submicron process, especially applicable to the ESD security application between some mixed-voltage interface circuits or different electrical power territory.
The accompanying drawing explanation
The structural representation that Fig. 1 is traditional one-way SCR device.
Fig. 2 is the structural representation of traditional double to silicon-controlled device.
The enforcement domain that Fig. 3 is silicon-controlled device of the present invention.
Fig. 4 is the generalized section of Fig. 3 along AA ' direction.
The equivalent circuit diagram that Fig. 5 is silicon-controlled device of the present invention.
Fig. 6 (a) is the ESD current drain path profile of silicon-controlled device of the present invention when esd event betides the A port.
Fig. 6 (b) is the ESD current drain path profile of silicon-controlled device of the present invention when esd event betides the K port.
The structural representation that Fig. 7 is silicon-controlled device of the present invention.
Fig. 8 is silicon-controlled device of the present invention and the traditional double current-voltage characteristic schematic diagram to silicon-controlled device.
Embodiment
In order more specifically to describe the present invention, below in conjunction with the drawings and the specific embodiments, technical scheme of the present invention and relative theory thereof are elaborated.
As shown in Figure 3 and Figure 4, a kind of bidirectional triode thyristor device based on NPN type triode auxiliary triggering comprises:
From left to right be provided with successively a N trap 21, P trap 23 and the 2nd N trap 22 on P substrate layer 10, P trap 23 is connected with the 2nd N trap 22 side by side with a N trap 21;
From left to right be provided with side by side successively an active injection region 41 of N+, an active injection region 51 of P+ and the active injection region 42 of the 2nd N+ on the one N trap 21; From left to right be provided with side by side successively the 3rd active injection region 43 of N+, the 2nd active injection region 52 of P+ and the active injection region 44 of the 4th N+ on the 2nd N trap 22;
The one active injection region 41 of N+ is connected by the first metal electrode 61 with an active injection region 51 of P+, and the 2nd active injection region 52 of P+ is connected by the second metal electrode 62 with the 4th active injection region 44 of N+;
The 3rd active injection region 43 of N+ is connected with the collector electrode of the 2nd NPN type triode N2, and the emitter of a NPN type triode N1 is connected with the first metal electrode 61; The 2nd active injection region 42 of N+ is connected with the collector electrode of the 3rd NPN type triode N3, and the emitter of the 4th NPN type triode N4 is connected with the second metal electrode 62; Base stage, the emitter four of the base stage of the one NPN type triode N1, collector electrode and the 2nd NPN type triode N2 connect extremely altogether, and base stage, the collector electrode four of the base stage of the 3rd NPN type triode N3, emitter and the 4th NPN type triode N4 connect extremely altogether.
The active injection region 51 of the one active injection region 41 of N+ and a P+, an active injection region 51 of P+ and the active injection region 42 of the 2nd N+, the 2nd active injection region 42 of N+ and the active injection region 43 of the 3rd N+, the 3rd active injection region 43 of N+ and the active injection region 52 of the 2nd P+ and the active injection region 52 of the 2nd P+ and the active injection region 44 of the 4th N+ all, by shallow slot 3 isolation, are filled with silica in shallow slot 3.
As shown in Figure 5, the equivalent electric circuit of present embodiment silicon-controlled device consists of four resistance R 1～R4, three triode Q1～Q3 and four NPN type triode N1～N4; Wherein, one end of the emitter of the first triode Q1 and the first resistance R 1 and the emitter of a NPN type triode N1 are connected and form the A electrode of silicon-controlled device, base stage is connected with the other end of the first resistance R 1, the collector electrode of the 3rd NPN type triode N3 and emitter or the collector electrode of the 3rd triode Q3, and collector electrode is connected with an end of the 3rd resistance R 3; One end of the emitter of the second triode Q2 and the second resistance R 2 and the emitter of the 4th NPN type triode N4 are connected and form the K electrode of silicon-controlled device, base stage is connected with the other end of the second resistance R 2, the collector electrode of the 2nd NPN type triode N2 and collector electrode or the emitter of the 3rd triode Q3, and collector electrode is connected with an end of the 4th resistance R 4; The base stage of the 3rd triode Q3 is connected with the other end of the 4th resistance R 4 with the other end of the 3rd resistance R 3; Base stage, the emitter four of the base stage of the one NPN type triode N1, collector electrode and the 2nd NPN type triode N2 connect extremely altogether, and base stage, the collector electrode four of the base stage of the 3rd NPN type triode N3, emitter and the 4th NPN type triode N4 connect extremely altogether.
The first triode Q1 and the second triode Q2 are the positive-negative-positive triode, and the 3rd triode Q3 is NPN type triode.
The first triode Q1 consists of an active injection region 51 of P+, a N trap 21 and P trap 23; The second triode Q2 consists of the 2nd active injection region 52 of P+, the 2nd N trap 22 and P trap 23; The 3rd triode Q3 consists of a N trap 21, the 2nd N trap 22 and P trap 23; The dead resistance that the first resistance R 1 and the 3rd resistance R 3 are a N trap 21; The dead resistance that the second resistance R 2 and the 4th resistance R 4 are the 2nd N trap 22.
As shown in Fig. 6 (a) and Fig. 7, when esd event occurs in the A end, and during K end ground connection, the reverse PN junction generation avalanche breakdown that the voltage that the ESD electric current produces on the A end can cause a N trap 21 and P trap 23 to form, when the pressure drop that the charge carrier produced when avalanche breakdown produces on the first resistance R 1 reaches the cut-in voltage (0.7V) of the forward diode that an active injection region 51 of P+ and a N trap 21 form, open in parasitic SCR path, and the A terminal voltage is clamped to one than electronegative potential, ESD electric current now will be released by the SCR path.Existence due to NPN type triode, the reverse PN junction generation avalanche breakdown that the 3rd NPN type triode N3 can form prior to a N trap 21 and P trap 23, provide the auxiliary current path by the 2nd active injection region 42 of N+ added, make the first resistance R 1 produce enough pressure drops and allow the first triode Q1 more early open; Therefore trigger voltage is than low in the situation that does not connect NPN type triode.Owing to occurring in the K end when esd event, and during A end ground connection, if do not add the 4th NPN type triode N4, the ESD stress current can be directly from the reverse parasitic diode path flow of the 3rd NPN type triode N3 mistake, so need add the anti-situation here of the 4th NPN type triode N4 to occur.
As shown in Fig. 6 (b) and Fig. 7, when esd event occurs in the K end, and during A end ground connection, the reverse PN junction generation avalanche breakdown that the voltage that the ESD electric current produces on the K end can cause the 2nd N trap 22 and P trap 23 to form, when the pressure drop that the charge carrier produced when avalanche breakdown produces on the second resistance R 2 reaches the cut-in voltage (0.7V) of the forward diode that the 2nd active injection region 52 of P+ and the 2nd N trap 22 form, open in parasitic SCR path, and the K terminal voltage is clamped to one than electronegative potential, ESD electric current now will be released by the SCR path.Simultaneously, also due to the existence of NPN type triode, the reverse PN junction generation avalanche breakdown that the 2nd NPN type triode N2 can form prior to the 2nd N trap 22 and P trap 23, provide the auxiliary current path by the 3rd active injection region 43 of N+ added, make the second resistance R 2 produce enough pressure drops and allow the second triode Q2 more early open; Therefore trigger voltage is than low in the situation that does not connect NPN type triode.Simultaneously, also owing to occurring in A end when esd event, and during K end ground connection, if do not add a NPN type triode N1, the ESD stress current can be directly from the reverse parasitic diode path flow of the 2nd NPN type triode N2 mistake, so need add the anti-situation here of a NPN type triode N1 to occur.
Shown in Fig. 8 present embodiment and traditional double to silicon-controlled device, at ESD stress, by A, held to the current-voltage characteristic under the K end, as can be seen from the figure traditional double is 34.5V to the trigger voltage of silicon-controlled device, and the trigger voltage of present embodiment only has 9.45V; Because two kinds of structures are two-way and symmetrical, when ESD stress by K to A, the current-voltage characteristic curve symmetry of gained.Existence due to NPN type triode, extra auxiliary current path is provided, parasitic triode is opened in advance, greatly reduce the trigger voltage of silicon-controlled device, and can adjust the size of two-way trigger voltage by adjusting the routed size that collapses voltage of the 2nd NPN type triode and the 3rd NPN type triode, be applicable to ESD protection on the following sheet of deep-submicron.
Claims (1)
1. the bidirectional triode thyristor device based on NPN type triode auxiliary triggering, is characterized in that, comprising:
P substrate layer (10) and four NPN type triodes;
From left to right be provided with successively a N trap (21), P trap (23) and the 2nd N trap (22) on described P substrate layer (10), described P trap (23) is connected with the 2nd N trap (22) side by side with a N trap (21);
From left to right be provided with side by side successively an active injection region of N+ (41), an active injection region of P+ (51) and the 2nd active injection region of N+ (42) on a described N trap (21); From left to right be provided with side by side successively the 3rd active injection region of N+ (43), the 2nd active injection region of P+ (52) and the 4th active injection region of N+ (44) on described the 2nd N trap (22);
A described active injection region of N+ (41) all isolates by shallow slot (3) with the 4th active injection region of N+ (44) with the 2nd active injection region of P+ (52) and the 2nd active injection region of P+ (52) with the 3rd active injection region of N+ (43), the 3rd active injection region of N+ (43) with the 2nd active injection region of N+ (42), the 2nd active injection region of N+ (42) with an active injection region of P+ (51), an active injection region of P+ (51);
A described active injection region of N+ (41) is connected by the first metal electrode (61) with an active injection region of P+ (51), and described the 2nd active injection region of P+ (52) is connected by the second metal electrode (62) with the 4th active injection region of N+ (44);
Described the 3rd active injection region of N+ (43) is connected with the collector electrode of the 2nd NPN type triode, and the emitter of a NPN type triode is connected with the first metal electrode (61); Described the 2nd active injection region of N+ (42) is connected with the collector electrode of the 3rd NPN type triode, and the emitter of the 4th NPN type triode is connected with the second metal electrode (62); Base stage, the emitter four of the base stage of the one NPN type triode, collector electrode and the 2nd NPN type triode connect extremely altogether, and base stage, the collector electrode four of the base stage of the 3rd NPN type triode, emitter and the 4th NPN type triode connect extremely altogether.
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| CN104241265B (en) * | 2013-06-09 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection structure |
| CN104241274B (en) * | 2014-08-30 | 2017-09-29 | 电子科技大学 | A kind of bidirectional ESD protective device based on lateral PNP structure |
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| CN102034858A (en) * | 2010-10-28 | 2011-04-27 | 浙江大学 | Bidirectional triode thyristor for electrostatic discharge protection of radio frequency integrated circuit |
| CN102254912A (en) * | 2011-07-13 | 2011-11-23 | 浙江大学 | Controlled silicon device under auxiliary trigger of embedded P-type MOS (Metal Oxide Semiconductor) transistor |
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| US6756642B2 (en) * | 2002-11-07 | 2004-06-29 | Taiwan Semiconductor Manufacturing Co., Ltd | Integrated circuit having improved ESD protection |
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| CN102034858A (en) * | 2010-10-28 | 2011-04-27 | 浙江大学 | Bidirectional triode thyristor for electrostatic discharge protection of radio frequency integrated circuit |
| CN102254912A (en) * | 2011-07-13 | 2011-11-23 | 浙江大学 | Controlled silicon device under auxiliary trigger of embedded P-type MOS (Metal Oxide Semiconductor) transistor |
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