CN102034858A - Bidirectional triode thyristor for electrostatic discharge protection of radio frequency integrated circuit - Google Patents
Bidirectional triode thyristor for electrostatic discharge protection of radio frequency integrated circuit Download PDFInfo
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- CN102034858A CN102034858A CN 201010522613 CN201010522613A CN102034858A CN 102034858 A CN102034858 A CN 102034858A CN 201010522613 CN201010522613 CN 201010522613 CN 201010522613 A CN201010522613 A CN 201010522613A CN 102034858 A CN102034858 A CN 102034858A
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- trap
- injection region
- integrated circuit
- triode thyristor
- bidirectional triode
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- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 12
- 238000002347 injection Methods 0.000 claims abstract description 80
- 239000007924 injection Substances 0.000 claims abstract description 80
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims abstract description 7
- 230000001681 protective effect Effects 0.000 claims description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 14
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 230000003068 static effect Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/747—Bidirectional devices, e.g. triacs
Abstract
The invention discloses a bidirectional triode thyristor for electrostatic discharge protection of a radio frequency integrated circuit, comprising a P-type substrate on which a P trap, a first N trap and a second N trap are arranged, wherein the first N trap and the second N trap are arranged at two sides of the P trap; a first N<+> injection region, a first P<+> injection region and a third N<+> injection region which are isolated by a shallow ditch are sequentially arranged above the first N trap from the outside to the inside, wherein the third N<+> injection region crosses the junction of the first N trap and the P trap; a second N<+> injection region, a second P<+> injection region and a fourth N<+> injection region which are isolated by a shallow ditch are sequentially arranged above the second N trap from the outside to the inside, wherein the fourth N<+> injection region crosses the junction of the second N trap and the P trap; and the surface of the P trap arranged between the third N<+> injection region and the fourth N<+> injection region is covered with gate oxide and polysilicon gates which are stacked in sequence from bottom to top. By utilizing the source-drain punchthrough of an NMOS (N-Channel Metal Oxide Semiconductor) to assist in triggering, the bidirectional triode thyristor provided by the invention has small starting voltage and parasitic capacitance and strong robustness and can provide bidirectional ESD (Electro-Static Discharge) protection.
Description
Technical field
The present invention relates to technical field of integrated circuits, relate in particular to a kind of bidirectional triode thyristor that is used for the radio frequency integrated circuit electrostatic discharge protective.
Background technology
Natural Electrostatic Discharge phenomenon constitutes serious threat to the reliability of integrated circuit.In industrial quarters, the inefficacy 30% of integrated circuit (IC) products all is owing to suffer the static discharge phenomenon caused, enters the integrated circuit after the nanometer era, and thinner gate oxide thickness all makes integrated circuit be subjected to the probability that static discharge destroys to be increased greatly.Therefore, the reliability of improving integrated circuit electrostatic discharge protection has very important effect to the rate of finished products that improves product.
The pattern of static discharge phenomenon is divided into four kinds usually: HBM (human body discharge mode), MM (machine discharge mode), CDM (assembly charging and discharging pattern) and FIM (electric field induction pattern).And the most common two kinds of static discharge patterns that also are the industrial quarters product must pass through are HBM and MM.When static discharge took place, electric charge flowed into and flows out from the another pin from a pin of chip usually, and the electric current that this moment, electrostatic charge produced is usually up to several amperes, and the voltage that produces at the electric charge input pin is up to several volts even tens volts.Can cause the damage of inside chip if bigger ESD electric current flows into inside chip, simultaneously, the high pressure that produces at input pin also can cause internal components generation grid oxygen punch-through, thereby causes circuit malfunction.Therefore, damaged by ESD, all will carry out effective ESD protection, the ESD electric current is released each pin of chip in order to prevent inside chip.
In the evolution of ESD protection, diode, GGNMOS (NMOS of grid ground connection), SCR devices such as (controllable silicons) are used as the ESD protective unit usually.SCR robustness in all devices is best, but trigger voltage is too high, is not suitable for the ESD protection of low-voltage circuit.Input and output pin for high speed circuit, or the input and output pin of radio frequency integrated circuit, because the parasitic capacitance that diode is introduced is less relatively, can add simulator emulation, and it is simple in structure, design easily, therefore often use diode pair to realize the ESD protection of radio frequency high-speed chip pin, but the anti-ESD energy of the diode of unit are force rate SCR is low.
Controllable silicon commonly used is the two traps of P, N on the P type substrate as shown in Figure 1, and two injection regions are all arranged on P trap and the N trap, is respectively N+ injection region and P+ injection region.Wherein the N+ injection region of N trap is arranged on the end away from the P trap, and the P+ injection region of N trap is arranged on the end near the P trap; The P+ injection region of P trap is arranged on the end away from the N trap, and the N+ injection region of P trap is arranged on the end near the N trap.A N+ injection region is arranged on N trap and top, P trap junction and is connected across the cut-in voltage that is used for reducing SCR between N trap and the P trap, uses shallow trench to isolate (STI) between all injection regions.The N+ injection region of N trap and P+ injection region connect electrical anode (Anode), and the N+ injection region of P trap and P+ injection region connect electrical cathode (Cathode).Fig. 2 is and the corresponding electrical schematic diagram of this SCR structure.
Under the normal operating conditions of integrated circuit, electrostatic discharge protector is to be in closing state, can not influence the current potential on the input and output pin.And externally static pours into integrated circuit and when producing moment high-tension, this device can be opened conducting, emits electrostatic induced current rapidly.But this SCR trigger voltage is generally higher, can not effectively protect for 5V and following operating voltage.
Summary of the invention
The invention provides a kind of bidirectional triode thyristor that is used for the radio frequency integrated circuit electrostatic discharge protective, this device trigger voltage is low, and parasitic capacitance is little.
A kind of bidirectional triode thyristor that is used for the radio frequency integrated circuit electrostatic discharge protective comprises P type substrate, a N trap and the 2nd N trap that described P type substrate is provided with the P trap and is positioned at P trap both sides;
The one N trap top is provided with a N+ injection region, a P+ injection region and the 3rd P+ injection region that isolates by shallow trench from outside to inside successively, and the 3rd P+ injection region is across the intersection of a N trap and P trap;
The 2nd N trap top is provided with the 2nd N+ injection region, the 2nd P+ injection region and the 4th N+ injection region that isolates by shallow trench from outside to inside successively, and wherein the 4th N+ injection region is across the intersection of the 2nd N trap and P trap;
P trap surface is covered with grid oxygen and the polysilicon gate that stacks gradually from bottom to up between the 3rd N+ injection region and the 4th N+ injection region.
The present invention also provides the application of above-mentioned bidirectional triode thyristor in electrostatic discharge protective, comprising:
The one N+ injection region is connected electrical anode with a P+ injection region, and the 2nd N+ injection region is connected electrical cathode with the 2nd P+ injection region.
The 3rd N+ injection region is equivalent to the drain electrode of NMOS structure in the bidirectional triode thyristor of the present invention, the 4th N+ injection region is equivalent to the source electrode of NMOS structure, the polysilicon gate of grid oxygen top is equivalent to the grid of NMOS structure, and the p type island region territory of polysilicon gate below is the raceway groove of NMOS structure.
With respect to traditional controllable silicon, bidirectional triode thyristor of the present invention utilizes the NMOS source to leak the break-through auxiliary triggering, and cut-in voltage and parasitic capacitance are little, and robust performance is strong, and the bi-directional ESD protection can be provided.
Description of drawings
Fig. 1 is the structural representation of existing ESD protective device;
Fig. 2 is the equivalent circuit diagram of protective device shown in Figure 1;
Fig. 3 is the profile of bi-directional ESD protective device of the present invention;
Fig. 4 is the vertical view of bi-directional ESD protective device shown in Figure 3;
Fig. 5 is the equivalent circuit diagram of bi-directional ESD protective device shown in Figure 3.
Embodiment
As shown in Figure 3 and Figure 4, a kind of controllable silicon that is used for electrostatic discharge protective, this controllable silicon comprise 4 layers, and wherein bottom is a P type substrate 31, the second layer is P trap 33, a N trap 32a and the 2nd N trap 32b that is arranged on the P type substrate, and wherein a N trap 32a and the 2nd N trap 32b are positioned at the both sides of P trap 33.
The 3rd layer for being arranged on 4 N+ injection regions and 2 the P+ injection regions on the N trap, wherein N trap 32a top is provided with a N+ injection region 35a, a P+ injection region 37a and the 3rd N+ injection region 39a from outside to inside successively, isolate by shallow trench 36a between the one a N+ injection region 35a and the P+ injection region 37a, isolate by shallow trench 38a between the one P+ injection region 37a and the 3rd N+ injection region 39a, the 3rd N+ injection region 39a is across the intersection of a N trap 32a and P trap 33.
The 2nd N trap 32b top is provided with the 2nd N+ injection region 35b, the 2nd P+ injection region 37b and the 4th N+ injection region 39b from outside to inside successively, isolate by shallow trench 36b between the 2nd N+ injection region 35b and the 2nd P+ injection region 37b, isolate by shallow trench 38b between the 2nd P+ injection region 37b and the 4th N+ injection region 39b, the 4th N+ injection region 39b is across the intersection of the 2nd N trap 32a and P trap 33.
During application, a N+ injection region 35a and a P+ injection region 37a all insert electrical anode, and the 2nd P+ injection region 37b and the 2nd N+ injection region 35b all insert electrical cathode.
From the electrical anode to the electrical cathode, the SCR path is a P+ injection region 37a-N trap 32 and the 3rd N+ injection region 39a-P trap 33-the 2nd N trap 34 and the 4th N+ injection region 39b, constitutes the P-N-P-N SCR structure.From the electrical cathode to the electrical anode, the SCR path is the 2nd P+ injection region 37b-the 2nd N trap 34-P trap 33-the one a N trap 32 and a N+ injection region 35a, constitutes reverse P-N-P-N SCR structure.
As shown in Figure 5, by a P+ injection region 37a, a N trap 32 and P trap 33 constitute PNP parasitic transistor Q1; By a N trap 32, P trap 33 and the 2nd N trap 34 constitute NPN parasitic transistor Q2; Constitute PNP parasitic transistor Q3 by P trap 33, the two N traps 34 and the 2nd P+ injection region 37b.
When the ESD signal appears in anode, being added in voltage bigger on the N trap can cause the source knot of NMOS on the P trap and the depletion region of drain junction to be widened, when the grid of NMOS long less be channel length more in short-term, break-through can take place in the source drain depletion region of NMOS under ESD voltage, the punchthrough current that produces flows to the 2nd N trap from a N trap through the P trap, when electric current flows through the cut-in voltage of the pressure drop of N trap dead resistance generation greater than parasitic PNP triode Q1, PNP parasitic triode Q1 opens, simultaneously because positive feedback is also opened NPN parasitic triode Q2, the whole SCR device that is made of PNP parasitic transistor Q1 and NPN parasitic transistor Q2 is switched on, the ESD electric current that begins to release is clamped down on the device both end voltage simultaneously than electronegative potential.Same principle, because symmetrical configuration when the ESD signal appears in negative electrode, is leaked break-through by the source of P trap top NMOS, the reverse SCR that is made of PNP parasitic transistor Q3 and NPN parasitic transistor Q2 can open smoothly, the ESD electric current of releasing.
In actual applications, the channel length that changes the length of polysilicon gate and grid oxygen in this patent of invention and be NMOS can be adjusted the cut-in voltage of SCR, can adjust the clamp voltage of SCR by adjusting the device anode cathode separation.In application, by rationally being set, NMOS grid length under the normal level signal, can not open, and when the electrostatic induced current signal arrives, smoothly the auxiliary triggering ESD electric current of releasing to guarantee entire device.
Claims (1)
1. a bidirectional triode thyristor that is used for the radio frequency integrated circuit electrostatic discharge protective comprises P type substrate, it is characterized in that: a N trap and the 2nd N trap that described P type substrate is provided with the P trap and is positioned at P trap both sides;
The one N trap top is provided with a N+ injection region, a P+ injection region and the 3rd N+ injection region that isolates by shallow trench from outside to inside successively, and the 3rd N+ injection region is across the intersection of a N trap and P trap;
The 2nd N trap top is provided with the 2nd N+ injection region, the 2nd P+ injection region and the 4th N+ injection region that isolates by shallow trench from outside to inside successively, and wherein the 4th N+ injection region is across the intersection of the 2nd N trap and P trap;
P trap surface is covered with grid oxygen and the polysilicon gate that stacks gradually from bottom to up between the 3rd N+ injection region and the 4th N+ injection region.
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Cited By (18)
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CN102244076A (en) * | 2011-07-27 | 2011-11-16 | 浙江大学 | Electrostatic discharge protective device for radio frequency integrated circuit |
CN102522404A (en) * | 2011-12-30 | 2012-06-27 | 无锡新硅微电子有限公司 | Bidirectional SCR ESD protective circuit for low triggered voltage |
CN102544066A (en) * | 2012-03-09 | 2012-07-04 | 浙江大学 | Bidirectional controllable silicon device based on assistant triggering of NPN-type triodes |
CN102544085A (en) * | 2012-03-09 | 2012-07-04 | 浙江大学 | Bidirectional silicon controlled device based on assistant triggering of PMOS (P-channel Metal Oxide Semiconductor) tubes |
CN102569360A (en) * | 2012-03-09 | 2012-07-11 | 浙江大学 | Bidirectional triode thyristor based on diode auxiliary triggering |
CN104810393A (en) * | 2015-04-16 | 2015-07-29 | 江苏艾伦摩尔微电子科技有限公司 | Controllable silicon with double hysteresis characteristics for electrostatic protection |
CN104810367A (en) * | 2015-04-16 | 2015-07-29 | 江苏艾伦摩尔微电子科技有限公司 | Novel high-area-efficiency and low-triggering silicon controlled |
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CN106783992A (en) * | 2016-11-30 | 2017-05-31 | 辽宁大学 | A kind of two-way SCR structure of NMOS low pressure triggering |
CN108520875A (en) * | 2018-06-07 | 2018-09-11 | 湖南静芯微电子技术有限公司 | A kind of high maintenance voltage NPNPN type bidirectional thyristor electrostatic protection devices |
CN108899314A (en) * | 2018-05-23 | 2018-11-27 | 湖南大学 | electrostatic protection device |
CN109103184A (en) * | 2018-08-24 | 2018-12-28 | 电子科技大学 | Two-way high maintenance electric current ESD protection device |
CN109742071A (en) * | 2019-01-07 | 2019-05-10 | 中国科学院微电子研究所 | A kind of ESD protective device of SOI power switch |
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CN109935581A (en) * | 2019-02-25 | 2019-06-25 | 中国科学院微电子研究所 | Bidirectional triode thyristor ESD-protection structure and soi structure |
CN109935582A (en) * | 2019-02-25 | 2019-06-25 | 中国科学院微电子研究所 | Bidirectional triode thyristor ESD-protection structure and soi structure |
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CN116093153A (en) * | 2023-04-10 | 2023-05-09 | 江苏应能微电子股份有限公司 | Low capacitance bi-directional SCR transient suppression device with high sustain voltage |
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CN110880499A (en) * | 2019-11-19 | 2020-03-13 | 江南大学 | ESD/EOS protection method for substrate auxiliary trigger and voltage clamp |
CN116093153A (en) * | 2023-04-10 | 2023-05-09 | 江苏应能微电子股份有限公司 | Low capacitance bi-directional SCR transient suppression device with high sustain voltage |
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Application publication date: 20110427 |