CN102034814B

CN102034814B - Electrostatic discharge protective device

Info

Publication number: CN102034814B
Application number: CN2010105226152A
Authority: CN
Inventors: 马飞; 韩雁; 董树荣; 宋波; 苗萌; 李明亮; 吴健; 郑剑锋
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2010-10-28
Filing date: 2010-10-28
Publication date: 2012-02-01
Anticipated expiration: 2030-10-28
Also published as: CN102034814A

Abstract

The invention discloses an electrostatic discharge (ESD) protective device which comprises a P-type substrate, wherein the P-type substrate is provided with a P-well; the P-well is provided with a first N<+> injection region, a second N<+> injection region, a first P<+> injection region, a third N<+> injection region, a fourth N<+> injection region, a fifth N<+> injection region, a second P<+> injection region, a sixth N<+> injection region and a third P<+> injection region from inside to outside, which are circularly or annularly concentric; the second N<+> injection region, the first P<+> injection region and the third N<+> injection region are orderly close to each other; the fifth N<+> injection region, the second P<+> injection region and the sixth N<+> injection region are orderly close to each other; the sixth N<+> injection region and the third P<+> injection region are isolated by a shallow ditch; the P-well surfaces between the first N<+> injection region and the second N<+> injection region, between the third N<+> injection region and the fourth N<+> injection region and between the fourth N<+> injection region and the fifth N<+> injection region are coated with gate oxide and polysilicon gate which are orderly stacked from bottom to top. By triggering the annular gate NMOS tube with the substrate, the ESD protective device can effectively improve the conduction uniformity of the interdigital GGNMOS, and has the advantages of small area and uniform current.

Description

A kind of electrostatic discharge protection component

Technical field

The present invention relates to technical field of integrated circuits, relate in particular to a kind of electrostatic discharge protection component.

Background technology

Natural Electrostatic Discharge phenomenon constitutes serious threat to the reliability of integrated circuit.In industrial quarters, the inefficacy 30% of IC products all is owing to suffer the static discharge phenomenon caused, and more and more littler process, and thinner gate oxide thickness all makes integrated circuit receive the probability that static discharge destroys to be increased greatly.Therefore, the reliability of improving integrated circuit electrostatic discharge protection has very important effect to the rate of finished products that improves product.

The pattern of static discharge phenomenon is divided into four kinds usually: HBM (human body discharge mode), MM (machine discharge mode), CDM (assembly charging and discharging pattern) and electric field induction pattern (FIM).And the most common two kinds of static discharge patterns that also are the industrial quarters product must pass through are HBM and MM.When static discharge took place, electric charge flowed into and flows out from the another pin from a pin of chip usually, and the electric current that this moment, electrostatic charge produced is usually up to several amperes, and the voltage that produces at the electric charge input pin is up to several volts even tens volts.Can cause the damage of inside chip if bigger ESD electric current flows into inside chip, simultaneously, the high pressure that produces at input pin also can cause internal components generation grid oxygen punch-through, thereby causes circuit malfunction.Therefore, damaged by ESD, all will carry out effective ESD protection, the ESD electric current is released each pin of chip in order to prevent inside chip.

In the evolution of ESD protection, diode, GGNMOS (n type field effect transistor of grid ground connection), SCR devices such as (controllable silicons) are used as the ESD protective unit usually.

GGNMOS commonly used is as shown in Figure 1, is the P trap on the P type substrate, and two injection regions are arranged on the P trap, is respectively N+ injection region and P+ injection region.Wherein the P+ injection region is arranged on two ends, the outside, and the N+ injection region is arranged on the two ends of polysilicon gate and grid oxygen as source-drain electrode; Use shallow trench to isolate (STI) between P+ and the N+ injection region.The drain electrode of NMOS connects electrical anode (Anode), nmos source N+ injection region, and grid, the P+ injection region connects electrical cathode (Cathode).Fig. 2 is and the corresponding electrical schematic diagram of this GGNMOS structure.

Under the normal operating conditions of integrated circuit, electrostatic discharge protector is to be in closing state, can not influence the current potential on the input and output pin.And externally static pours into integrated circuit and when producing moment high-tension, this device can be opened conducting, emits electrostatic induced current rapidly.But common GGNMOS is because size is bigger, need interdigital more, under the transient state esd pulse each interdigital conducting inhomogeneous, robustness is relatively poor, the ESD protection effect is a greater impact.

Summary of the invention

The invention provides a kind of electrostatic discharge protection component, this device robustness is good, and anti-ESD ability is strong, and it is little to take chip area, and can adjust device size according to anti-ESD grade.

A kind of electrostatic discharge protection component; Comprise P type substrate; Described P type substrate is provided with the P trap, and the P trap is provided with a N+ injection region, the 2nd N+ injection region, a P+ injection region, the 3rd N+ injection region, the 4th N+ injection region, the 5th N+ injection region, the 2nd P+ injection region, the 6th N+ injection region and the 3rd P+ injection region of from inside to outside concentric annular circle or annular;

The 2nd N+ injection region, a P+ injection region and the 3rd N+ injection region are adjacent successively, and the 5th N+ injection region, the 2nd P+ injection region and the 6th N+ injection region are adjacent successively, and the 6th N+ injection region and the 3rd P+ injection region isolate through shallow trench;

Between the one N+ injection region and the 2nd N+ injection region, between the 3rd N+ injection region and the 4th N+ injection region and the P trap surface between the 4th N+ injection region and the 5th N+ injection region is covered with grid oxygen and the polysilicon gate that stacks gradually from bottom to up.

The present invention also provides the application of above-mentioned electro-static discharging device in integrated circuit ESD protection, comprising:

The 3rd P+ injection region, the 4th N+ injection region and all polysilicon gates are connected electrical cathode; The 6th N+ injection region, the 5th N+ injection region, the 3rd N+ injection region and the 2nd N+ injection region connect electrical anode, and a P+ injection region, the 2nd P+ injection region and a N+ injection region interconnect.

Wherein two with the P+ injection region at interval N+ injection region and annular of range upon range of grid oxygen between them and polysilicon gate formation are interdigital; Therefore to be equivalent to be provided with 3 annulars interdigital for said structure; Wherein a N+ injection region, the 4th N+ injection region are equivalent to the source electrode of NMOS pipe; The 2nd N+ injection region, the 3rd N+ injection region, the 5th N+ injection region are equivalent to the drain electrode of NMOS pipe, and polysilicon gate is a grid.

With respect to traditional G GMOS pipe, ESD protective device of the present invention utilizes substrate to trigger ring-shaped gate NMOS pipe, can effectively improve the conducting homogeneity of how interdigital GGNMOS, and it is little to have an area, the electric current advantage of uniform.

Description of drawings

Fig. 1 is the profile of existing GGNMOS pipe;

Fig. 2 is the equivalent circuit theory figure of the pipe of GGNMOS shown in the figure;

Fig. 3 is the profile of electrostatic discharge protection component of the present invention;

Fig. 4 is the vertical view of electrostatic discharge protection component shown in Figure 3;

Fig. 5 is the equivalent circuit theory figure of electrostatic discharge protection component shown in Figure 3.

Embodiment

Like Fig. 3 and shown in Figure 4; A kind of electrostatic discharge protection component; Comprise P type substrate 31; P type substrate 31 is provided with P trap 32, on the P trap 32 with one heart annular in outwards a circular or annular N+ injection region 45, the 2nd N+ injection region 43, a P+ injection region 42, the 3rd N+ injection region 41, the 4th N+ injection region 39, the 5th N+ injection region 37, the 2nd P+ injection region 36, the 6th N+ injection region 35 and the 3rd P+ injection region 33 of concentric ring row.

The 2nd N+ injection region 43, a P+ injection region 42 and the 3rd N+ injection region 41 are adjacent successively, and the 5th N+ injection region 37, the 2nd P+ injection region 36 and the 6th N+ injection region 35 are adjacent successively, and the 6th N+ injection region 35 and the 3rd P+ injection region 33 isolate through shallow trench 34.

Be spaced from each other between the one N+ injection region 45 and the 2nd N+ injection region 43, P trap 32 surfaces between them are covered with grid oxygen 44b and the polysilicon gate 44a that stacks gradually from bottom to up; Be spaced from each other between the 3rd N+ injection region 41 and the 4th N+ injection region 39, P trap 32 surfaces between them are covered with grid oxygen 40b and the polysilicon gate 40a that stacks gradually from bottom to up; The 4th N+ injection region 39 and the 5th N+ injection region 37 are spaced from each other, and P trap 32 surfaces between them are covered with grid oxygen 38b and the polysilicon gate 38a that stacks gradually from bottom to up.

Two N+ spaced apart from each other injection regions and between them P grid oxygen and polysilicon gate and constitute the NMOS pipe with the P trap; Therefore said structure is equivalent to three ring-shaped gate NMOS pipes (i.e. three annular interdigital structures); Wherein a N+ injection region 45, the 4th N+ injection region 39 are equivalent to the source electrode of NMOS pipe; The 2nd N+ injection region 43, the 3rd N+ injection region 41, the 5th N+ injection region 37 are equivalent to the drain electrode of NMOS pipe, and polysilicon gate is a grid.

During application; The 3rd P+ injection region 33 of this device, the 4th N+ injection region 39 are connected electrical cathode with all

polysilicon gate

38a, 40a, 44a; The 2nd P+ injection region 36, a P+ injection region 42 and a N+ injection region 45 link together mutually, and the 6th N+ injection region 35, the 5th N+ injection region 37, the 3rd N+ injection region 41, the 2nd N+ injection region 43 connect electrical anode.

As shown in Figure 5, constitute nmos fet M1 by a N+ injection region 45, the 2nd N+ injection region 43, polysilicon gate 44a and grid oxygen 44b equivalence; Constitute nmos fet M2 by the 4th N+ injection region 39, the 3rd N+ injection region 41, polysilicon gate 40a and grid oxygen 40b equivalence; Constitute nmos fet M3 by the 5th N+ injection region 37, the 4th N+ injection region 39, polysilicon gate 38a and grid oxygen 38b equivalence.

When the ESD signal appears in anode, connect the N+ injection region and the reverse PN junction generation of the P trap avalanche breakdown of anode, because outermost layer P+ injection region is connected to negative electrode with the P trap, avalanche current flows through P trap series resistance can produce pressure drop.Therefore; The nmos fet M1 raceway groove below P well area electromotive force of annular center is higher than the P trap electromotive force of outer region; When the cut-in voltage of this pressure drop greater than nmos fet M1 endophyte NPN triode; The NPN parasitic triode of nmos fet M1 is opened at first; P+ injection region through in the middle of outer nmos fet M2, the nmos fet M3 drain electrode provides the substrate trigger current to inject, and the base of the nmos fet M2 of outer shroud, the parasitic NPN triode of nmos fet M3 is by nmos fet M1 injection current, thereby the parasitic triode of the NPN of auxiliary outer shroud nmos fet M2, nmos fet M3 is opened; The ESD electric current that begins to release is clamped down on electricity anode and cathode voltage than electronegative potential simultaneously.

Claims

1. electrostatic discharge protection component; Comprise P type substrate; Described P type substrate is provided with the P trap, it is characterized in that: the P trap is provided with a N+ injection region, the 2nd N+ injection region, a P+ injection region, the 3rd N+ injection region, the 4th N+ injection region, the 5th N+ injection region, the 2nd P+ injection region, the 6th N+ injection region and the 3rd P+ injection region of from inside to outside concentric annular circle or annular;