CN102034814B - An electrostatic discharge protection device - Google Patents

Abstract

The invention discloses an electrostatic discharge (ESD) protective device which comprises a P-type substrate, wherein the P-type substrate is provided with a P-well; the P-well is provided with a first N<+> injection region, a second N<+> injection region, a first P<+> injection region, a third N<+> injection region, a fourth N<+> injection region, a fifth N<+> injection region, a second P<+> injection region, a sixth N<+> injection region and a third P<+> injection region from inside to outside, which are circularly or annularly concentric; the second N<+> injection region, the first P<+> injection region and the third N<+> injection region are orderly close to each other; the fifth N<+> injection region, the second P<+> injection region and the sixth N<+> injection region are orderly close to each other; the sixth N<+> injection region and the third P<+> injection region are isolated by a shallow ditch; the P-well surfaces between the first N<+> injection region and the second N<+> injection region, between the third N<+> injection region and the fourth N<+> injection region and between the fourth N<+> injection region and the fifth N<+> injection region are coated with gate oxide and polysilicon gate which are orderly stacked from bottom to top. By triggering the annular gate NMOS tube with the substrate, the ESD protective device can effectively improve the conduction uniformity of the interdigital GGNMOS, and has the advantages of small area and uniform current.

Description

An electrostatic discharge protection device

technical field

The invention relates to the technical field of integrated circuits, in particular to an electrostatic discharge protection device.

Background technique

The phenomenon of electrostatic discharge (ESD) in nature poses a serious threat to the reliability of integrated circuits. In the industry, 30% of the failures of integrated circuit products are caused by electrostatic discharge, and the increasingly smaller process size and thinner gate oxide thickness greatly increase the probability of integrated circuit damage by electrostatic discharge. Therefore, improving the reliability of integrated circuit electrostatic discharge protection has a non-negligible effect on improving the yield of products.

The modes of electrostatic discharge phenomena are usually divided into four types: HBM (Human Body Model), MM (Machine Discharge Model), CDM (Component Charge Discharge Model) and Field Induction Model (FIM). The two most common electrostatic discharge modes that industrial products must pass are HBM and MM. When an electrostatic discharge occurs, the charge usually flows in from one pin of the chip and flows out from the other pin. At this time, the current generated by the electrostatic charge is usually as high as several amperes, and the voltage generated at the charge input pin is as high as several volts or even Dozens of volts. If a large ESD current flows into the internal chip, it will cause damage to the internal chip. At the same time, the high voltage generated at the input pin will also cause gate oxide breakdown of the internal device, resulting in circuit failure. Therefore, in order to prevent the internal chip from being damaged by ESD, each pin of the chip must be effectively protected against ESD to discharge the ESD current.

In the development of ESD protection, devices such as diodes, GGNMOS (gate-grounded N-type field effect transistors), and SCR (silicon controlled silicon) are usually used as ESD protection units.

The commonly used GGNMOS is shown in Figure 1. On the P-type substrate is a P-well, and there are two implanted regions on the P-well, namely the N+ implanted region and the P+ implanted region. Wherein the P+ implantation region is arranged at both ends of the outer side, and the N+ implantation region is arranged at both ends of the polysilicon gate and the gate oxide as source and drain; a shallow trench isolation (STI) is used between the P+ and N+ implantation regions. The drain of the NMOS is connected to the electrical anode (Anode), the NMOS source N+ injection region, the gate, and the P+ injection region are connected to the electrical cathode (Cathode). FIG. 2 is an electrical schematic diagram corresponding to the GGNMOS structure.

In the normal working state of the integrated circuit, the electrostatic discharge protection device is in a closed state and will not affect the potential on the input and output pins. When external static electricity is poured into the integrated circuit to generate an instantaneous high voltage, the device will turn on and discharge the static electricity quickly. However, due to the large size of the ordinary GGNMOS, more fingers are required, and the conduction of each finger is uneven under the transient ESD pulse, the robustness is poor, and the ESD protection effect is greatly affected.

Contents of the invention

The invention provides an electrostatic discharge protection device, which has good robustness, strong ESD resistance, small layout area, and the size of the device can be adjusted according to the ESD resistance level.

An electrostatic discharge protection device, comprising a P-type substrate, on which a P-well is provided, and on the P-well is provided a circular or ring-shaped first N+ implantation region concentrically arranged from the inside to the outside, the first Two N+ implantation regions, a first P+ implantation region, a third N+ implantation region, a fourth N+ implantation region, a fifth N+ implantation region, a second P+ implantation region, a sixth N+ implantation region and a third P+ implantation region;

The second N+ implantation region, the first P+ implantation region and the third N+ implantation region are next to each other, the fifth N+ implantation region, the second P+ implantation region and the sixth N+ implantation region are next to each other, the sixth N+ implantation region and the third The P+ injection area is isolated by a shallow moat;

The surface of the P well between the first N+ implantation region and the second N+ implantation region, between the third N+ implantation region and the fourth N+ implantation region, and between the fourth N+ implantation region and the fifth N+ implantation region is covered from bottom to top. Gate oxide and polysilicon gates are stacked in sequence.

The present invention also provides the application of the above-mentioned electrostatic discharge device in integrated circuit ESD protection, including:

Connect the third P+ injection region, the fourth N+ injection region and all polysilicon gates to the electrical cathode, the sixth N+ injection region, the fifth N+ injection region, the third N+ injection region and the second N+ injection region to the electrical anode, and the first The P+ implantation region, the second P+ implantation region and the first N+ implantation region are connected to each other.

Two of them use the P+ implant region to space the N+ implant region and the stacked gate oxide and polysilicon gate between them to form a ring finger, so the above structure is equivalent to setting 3 ring fingers, of which the first N+ implant region, the fourth The N+ implantation region is equivalent to the source of the NMOS transistor, the second N+ implantation region, the third N+ implantation region, and the fifth N+ implantation region are equivalent to the drain of the NMOS transistor, and the polysilicon gate is the gate.

Compared with the traditional GGMOS transistor, the ESD protection device of the present invention uses the substrate to trigger the ring-gate NMOS transistor, which can effectively improve the conduction uniformity of the multi-finger GGNMOS, and has the advantages of small area and uniform current.

Description of drawings

FIG. 1 is a cross-sectional view of an existing GGNMOS tube;

Fig. 2 is the schematic diagram of the equivalent circuit of the GGNMOS tube shown in the figure;

3 is a cross-sectional view of an electrostatic discharge protection device of the present invention;

Fig. 4 is a top view of the electrostatic discharge protection device shown in Fig. 3;

FIG. 5 is a schematic diagram of an equivalent circuit of the electrostatic discharge protection device shown in FIG. 3 .

Detailed ways

As shown in Fig. 3 and Fig. 4, a kind of electrostatic discharge protection device comprises P-type substrate 31, and P-type substrate 31 is provided with P well 32, and the concentric ring row on P well 32 is circled inward and outward. Shaped or annular first N+ implantation region 45, second N+ implantation region 43, first P+ implantation region 42, third N+ implantation region 41, fourth N+ implantation region 39, fifth N+ implantation region 37, second P+ implantation region region 36 , the sixth N+ implantation region 35 and the third P+ implantation region 33 .

The second N+ implantation region 43, the first P+ implantation region 42 and the third N+ implantation region 41 are next to each other successively, the fifth N+ implantation region 37, the second P+ implantation region 36 and the sixth N+ implantation region 35 are successively adjacent to each other, and the sixth The N+ implant region 35 and the third P+ implant region 33 are separated by a shallow moat 34 .

The first N+ implantation region 45 and the second N+ implantation region 43 are separated from each other, and the surface of the P well 32 between them is covered with gate oxide 44b and polysilicon gate 44a stacked sequentially from bottom to top; the third N+ implantation region 41 and The fourth N+ implantation regions 39 are separated from each other, and the surface of the P well 32 between them is covered with gate oxide 40b and polysilicon gate 40a stacked sequentially from bottom to top; the fourth N+ implantation region 39 and the fifth N+ implantation region 37 are mutually The surface of the P well 32 between them is covered with gate oxide 38b and polysilicon gate 38a stacked in sequence from bottom to top.

Two N+ implanted regions separated from each other and the gate oxide of P between them and the polysilicon gate and P well constitute an NMOS transistor, so the above structure is equivalent to three ring gate NMOS transistors (that is, three ring finger structures), where The first N+ implantation region 45, the fourth N+ implantation region 39 are equivalent to the source of the NMOS transistor, the second N+ implantation region 43, the third N+ implantation region 41, and the fifth N+ implantation region 37 are equivalent to the drain of the NMOS transistor. The gate is the gate.

During application, the 3rd P+ injection region 33 of this device, the 4th N+ injection region 39 and all polysilicon gates 38a, 40a, 44a connect electric cathode, the second P+ injection region 36, the first P+ injection region 42 and the first N+ injection region The regions 45 are connected to each other, and the sixth N+ implantation region 35 , the fifth N+ implantation region 37 , the third N+ implantation region 41 , and the second N+ implantation region 43 are connected to the electrical anode.

As shown in Figure 5, the NMOS field effect transistor M1 is equivalently formed by the first N+ implantation region 45, the second N+ implantation region 43, the polysilicon gate 44a and the gate oxide 44b; the fourth N+ implantation region 39, the third N+ implantation region 41. The polysilicon gate 40a and the gate oxide 40b equivalently form an NMOS field effect transistor M2; the fifth N+ implantation region 37, the fourth N+ implantation region 39, the polysilicon gate 38a and the gate oxide 38b equivalently constitute an NMOS field effect transistor M3.

When an ESD signal appears at the anode, an avalanche breakdown occurs between the N+ injection region connected to the anode and the reverse PN junction of the P well. Since the outermost P+ injection region connects the P well to the cathode, the avalanche current flows through the series resistance of the P well to generate a voltage drop. Therefore, the potential of the P well area under the channel of the NMOS field effect transistor M1 in the center of the ring is higher than the potential of the P well area in the outer ring area. When the voltage drop is greater than the turn-on voltage of the parasitic NPN transistor inside the NMOS field effect transistor M1, the NMOS field effect transistor The NPN parasitic transistor of M1 is turned on first, and the substrate trigger current injection is provided through the P+ injection area between the drains of the outer NMOS field effect transistor M2 and NMOS field effect transistor M3, and the outer ring NMOS field effect transistor M2 and NMOS field effect transistor The base area of the parasitic NPN transistor of M3 is injected with current by the NMOS field effect transistor M1, thereby assisting the NPN parasitic transistors of the outer ring NMOS field effect transistor M2 and NMOS field effect transistor M3 to turn on, and start to discharge the ESD current, and at the same time, the electrical Yin and Yang The voltage across the poles is clamped at a lower potential.

Claims (1)

1. An electrostatic discharge protection device, comprising a P-type substrate, the P-type substrate is provided with a P well, and it is characterized in that: the P well is provided with a circular or annular first concentric ring column from the inside to the outside. An N+ implantation region, a second N+ implantation region, a first P+ implantation region, a third N+ implantation region, a fourth N+ implantation region, a fifth N+ implantation region, a second P+ implantation region, a sixth N+ implantation region and a third P+ implantation region Injection area; The second N+ implantation region, the first P+ implantation region and the third N+ implantation region are next to each other, the fifth N+ implantation region, the second P+ implantation region and the sixth N+ implantation region are next to each other, the sixth N+ implantation region and the third The P+ injection area is isolated by a shallow moat; The surface of the P well between the first N+ implantation region and the second N+ implantation region, between the third N+ implantation region and the fourth N+ implantation region, and between the fourth N+ implantation region and the fifth N+ implantation region is covered from bottom to top. Gate oxide and polysilicon gates are stacked in sequence.

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