CN102169881A - Power supply clamping structure method applied to high pressure process integrated circuit - Google Patents
Power supply clamping structure method applied to high pressure process integrated circuit Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
Abstract
The invention comprises a power supply clamping structure method applied to the high pressure process integrated circuit comprising a single MLSCR device which comprises a P trap and an N trap, a bridge shape P+ injection region is arrange between the P trap and the N trap, the size range of the bridge shape P+ injection region is 2.5 mum -10.0 mum. The power supply clamping structure can also adopt at least two single MLSCR devices cascade, wherein each cathode of the last stage single MLSCR device and anode of next stage are in metal connection, moreover. The anode of the first stage single MLSCR device is the anode of cascade structure, and the cathode of the last stage single MLSCR device is the cathode of the cascade. The power supply clamping structure, which has strong unit area electrostatic protection capability, can control the clamping voltage by adjusting the size of the bridge shape P+ injection region. Along with the multiplication of the cascade stage, the trigger voltage value and the clamping voltage value also carry out the multiplication. The method of the invention has little experiment calculation and is easy to be popular in application.
Description
Technical field
The present invention relates to electrostatic discharge protective technical field on the semiconductor integrated circuit chip, specifically is a kind of power supply clamper structure of effect of contracting that is applied to avoid fastening with a bolt or latch in the high-pressure process integrated circuit.
Background technology
Transport and during final system uses, static discharge (Electrostatic discharge ESD) phenomenon all inevitably can occur, and the energy level of ESD abrupt release might be destroyed the fragile device in the IC chip in the manufacturing of integrated circuit (IC) chip, transmission.Therefore, it is very essential using high performance electrostatic discharge protection circuit to come the electric charge of the voltage of each pin of clamper IC chip and the ESD that releases to be without prejudice with protection IC chip.
At present existing multiple electrostatic protection device is suggested, as diode, GGNMOS, SCR etc.But in the ESD protection process of the chip of realizing high-pressure process is made, because the operating voltage of this class chip is usually than higher, can reach 20V-40V even higher, so the trigger voltage of electrostatic defending module to be higher than normal working voltage between its power supply and the ground.
If select many fingers (multi-finger) GGNMOS structure in parallel for use; the NMOS here just must use the high voltage transistor in the high-pressure process; and for high voltage transistor; its puncture voltage much larger than secondary breakdown voltage (vt2＜＜vt1); this will run counter to the primary condition of the even conducting of many fingers device; be Vt1＜Vt2, therefore the esd protection ability of the high pressure NMOS part after the parallel connection of many fingers can not obtain bigger raising on single finger basis.General can increase resistance to improve device secondary breakdown voltage value in each finger of many fingers GGNMOS device, thereby raising conducting homogeneity, but the Vt2 of high pressure NMOS is little more too many than the Vt1 value, even serial resistance in each finger, still can't satisfy the condition of even conducting between each finger, also just be difficult to the ESD protective capacities that reaches high.
If select many fingers SCR structure for use, though can avoid non-homogeneous conduction problem, reach higher electro-static discharge protective ability, if but external noise appears on the port of circuit, false triggering the SCR module between power supply and the ground, form low resistance path, and the clamp voltage of general SCR structure is all very low, about 2～3V, at this moment the clamp voltage at power supply place is just also little than circuit voltage, low-resistance conducting state between power supply and the ground just can keep always, fastens the effect that contracts with a bolt or latch thereby form, and causes this partial circuit to be burnt the most at last.
So the electrostatic storage deflection (ESD) protection circuit in the high-pressure process integrated circuit between power supply and the ground must possess even conducting simultaneously and can avoid because of door bolt that external noise the causes ability that effect takes place that contracts.
At the problems referred to above, the existing solution that disclosed in the document has following three kinds:
At Mingdou; in the paper of Ker " Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs " (EOS/ESD Symposium 2004); the field oxide device (FOD) of varying number reaches the clamp voltage value of the single FOD device of multiplication by the mode of cascade, thereby realizes not having the esd protection of fastening the effect generation of contracting with a bolt or latch.
In the paper " ESD protection for high-voltage CMOS technologies " (EOS/ESD Symposium 2006) of Olivier Quittard; low pressure GGNMOS by the cascade varying number or Gate-up PMOST (GUPMOS) the FET device clamp voltage value of single MOSFET that doubles then is to realize not having the door bolt esd protection that effect takes place that contracts.
Above two kinds of schemes based on FOD device and GGNMOS/GUPMOS device the feature of higher clamp voltage is arranged self, realize the clamp voltage value of expecting requirement by several identical FOD devices of cascade or MOS device.But the unit are esd protection ability of FOD device and GGNMOS/GUPMOS is not high, needs to sacrifice very big chip area and realizes basic esd protection index.
In U.S. Pat 20090212323 " Silicon-Controlled Rectifier (SCR) devices for high-voltage Electrostatic Discharge (ESD) applications ", the clamp voltage that a kind of Novel SCR structure is used for promoting single SCR device architecture has been proposed.This Novel SCR structure is with the emitter (the P+ emitting stage of parasitic PNP and the N+ emitting stage of parasitic NPN) of the parasitic BJT of traditional SCR device P+ and the N+ mode alternately of mixing that vertically replaces at device.The clamp voltage of Novel SCR device will be greatly improved, and by choosing suitable P+ and N+ doping area ratio, can adjust the size of clamp voltage, make the clamp voltage value be higher than circuit normal working voltage scope, thereby effectively avoid fastening with a bolt or latch the generation of the effect that contracts.But should invent in actual applications, and need choose suitable parameters: the promptly anodal area ratio that mixes to the distance between the negative pole, N+ and P+, choosing of these parameters is will be based upon on the more experimental basis, is difficult to be used widely.
Summary of the invention
At the defective that exists in the prior art, the object of the present invention is to provide a kind of power supply clamper structure in the high-pressure process integrated circuit that is applied to, its unit are antistatic capacity is very high, can be so that the entire circuit design area be optimized, size by bridge shape P+ injection region is controlled power supply clamper structure, and along with the multiplication of cascade progression, the trigger voltage value of cascade device and clamp voltage value be and then multiplication also, experimental calculation that need not be more is easy to popularization and application.
For reaching above purpose, the technical scheme that the present invention takes is: a kind ofly be applied to power supply clamper structure in the high-pressure process integrated circuit, comprise monomer M LSCR device, described monomer M LSCR device comprises P trap and N trap, one bridge shape P+ injection region is arranged between described P trap and the N trap, and the size adjustment scope of described bridge shape P+ injection region is between 2.5um～10.0um.
Wherein, described monomer M LSCR device comprises P type substrate, is N extension or N-Tub layer on the P type substrate, is well region on N extension or the N-Tub layer, and well region comprises N trap and P trap, is equipped with two injection regions on N trap and the P trap, is respectively N+ injection region and P+ injection region.
Wherein, the N+ injection region of described N trap is arranged on the end away from the P trap, and the P+ injection region is arranged on the end near the P trap; The P+ injection region of P trap is arranged on the end away from the N trap, and the N+ injection region is arranged on the end near the N trap; Isolate by FOX between N+ injection region and the P+ injection region.
Wherein, described monomer M LSCR device comprises P type substrate, is buried regions on the P type substrate, is well region on the buried regions, and well region comprises dark N trap and dark P trap.
On the basis of such scheme, the present invention has also taked a kind of power supply clamper structure in the high-pressure process integrated circuit that is applied to, comprise the cascade structure that above-mentioned at least monomer M LSCR device forms, the negative pole of described each upper level monomer M LSCR device is connected by metal with the positive pole of next stage monomer M LSCR device, and the positive pole of the just very cascade structure of first order monomer M LSCR device, the negative pole of afterbody monomer M LSCR device is the negative pole of cascade structure.
Wherein, described monomer M LSCR device adopts N-ring to isolate, and adopts P-ring to isolate between the monomer M LSCR device, and N-ring isolates suspension, and P-ring isolates ground connection.
Wherein, each described monomer M LSCR device comprises P type substrate, is N extension or N-Tub layer on the P type substrate, is well region on N extension or the N-Tub layer, and well region comprises N trap and P trap, is equipped with two injection regions on N trap and the P trap, is respectively N+ injection region and P+ injection region.
Wherein, the N+ injection region of each described N trap is arranged on the end away from the P trap, and the P+ injection region is arranged on the end near the P trap; The P+ injection region of P trap is arranged on the end away from the N trap, and the N+ injection region is arranged on the end near the N trap; Isolate by FOX between N+ injection region and the P+ injection region.
Wherein, each described monomer M LSCR device comprises P type substrate, is buried regions on the P type substrate, is well region on the buried regions, and well region comprises dark N trap and dark P trap.
Beneficial effect of the present invention is:
1. monomer M LSCR device has bridge shape P+ injection region, changed the forward break down voltage of traditional SCR structure, be reduced to N-Well/P+ (N trap/P+ injection region) junction breakdown voltage from N-Well/P-Well (N trap/P trap) junction breakdown voltage, reduced the trigger voltage of SCR monomer device;
2. this type of monomer M LSCR device can be by the size of N+ injection region in P+ injection region and the P trap in the adjusting N trap, the distance of N+ injection region and bridge shape P+ injection region in the distance of P+ injection region and bridge shape P+ injection region and the P trap in the N trap, the width dimensions of bridge shape P+ injection region in N trap and P trap realized high clamp voltage, choose suitable dimensions, can make the clamp voltage of monomer M LSCR device move closer to trigger voltage;
3. along with the multiplication of monomer M LSCR device cascade progression, by N-ring, P-ring effective isolation, the trigger voltage value of cascade device and clamp voltage value be and then multiplication also, chooses suitable cascade number, can realize not having the power supply clamper electrostatic storage deflection (ESD) protection circuit design of fastening the effect that contracts with a bolt or latch.
Description of drawings
Fig. 1 is the monomer M LSCR device architecture sectional view of first embodiment of the invention;
Fig. 2 is a monomer M LSCR device cascade structure sectional view among two Fig. 1;
Fig. 3 is the metal cascade vertical view of Fig. 2;
Fig. 4 is the monomer M LSCR device architecture sectional view of second embodiment of the invention;
Fig. 5 is a monomer M LSCR device cascade structure sectional view among two Fig. 4.
Fig. 6 is the monomer M LSCR device cascade structure TLP test characteristic figure of the different numbers of the present invention.
Reference numeral:
First embodiment: P type substrate 1a, N extension or N-Tub layer 2a, N trap 3a, P trap 4a, N+ injection region (21a, 31a, 41a), P+ injection region (22a, 41a, 42a), FOX 5a, bridge shape P+ injection region 6a, 54, two layers of metal 56 of layer of metal, hole 55.
Second embodiment: P type substrate 1b, buried regions 2b, dark N trap 3b, dark P trap 4b, N+ injection region (21b, 31b, 41b), P+ injection region (22b, 41b, 42b), FOX 5b, bridge shape P+ injection region 6b.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are described in further detail.
As shown in Figure 1, be the elementary cell of first embodiment of the present invention cascade structure, the structural section figure of described monomer M LSCR device, it comprises P type substrate 1a, P type substrate 1a goes up and is that it is well region that N extension or N-Tub layer 2a, N extension or N-Tub layer 2a go up, and well region comprises N trap 3a and P trap 4a.Being equipped with two injection regions on N trap 3a and the P trap 4a, is respectively N+ injection region 31a and P+ injection region 32a on the N trap 3a; And N+ injection region 41a on the P trap 4a and P+ injection region 42a.Wherein the N+ injection region 31a of N trap 3a is arranged on the end away from P trap 4a, and P+ injection region 32a is arranged on the end near P trap 4a; The P+ injection region 42a of P trap 4a is arranged on the end away from N trap 3a, and N+ injection region 41a is arranged on the end near N trap 3a; All isolate between N+ injection region on N trap 3a and the P trap 4a and the P+ injection region with FOX 5a.Place in described N trap 3a and P trap 4a boundary has bridge shape P+ injection region 6a to connect N trap 3a and P trap 4a.N+ injection region 31a among the N trap 3a and P+ injection region 32a constitute the positive pole of described monomer M LSCR device, and N+ injection region 41a among the P trap 4a and P+ injection region 42a constitute the negative pole of described monomer M LSCR device.N+ injection region 31a, P+ injection region 32a among the N trap 3a and the width dimensions of the N+ injection region 41a among the P trap 4a, P+ injection region 42a are D1, the width of isolation FOX5a on N trap 3a and the P trap 4a is respectively D2, D5, the width of bridge shape P+ injection region 6a in N trap 3a is D3, and the width in P trap 4a is D4.Regulate the size of D1, D5, D3 and D4, can realize high clamp voltage, choose suitable D3 and D4 value, can be so that clamp voltage moves closer to trigger voltage, in the present embodiment, the width of described bridge shape P+ injection region 6a, promptly the size adjustment scope is between 2.5um～10.0um.
As shown in Figure 2, be first embodiment of the invention, two monomer M LSCR device cascade structures, the negative pole of described first order monomer M LSCR device is made of N+ injection region 41a among the P trap 4a and P+ injection region 42a; The positive pole of described second level monomer M LSCR device is made of N+ injection region 31a among the N trap 3a and P+ injection region 32a; The positive pole of the negative pole of described first order monomer M LSCR device and second level monomer M LSCR device links together by metal.The positive pole that keeps described first order SCR monomer device, is not connected with metal as the positive pole of cascade structure by the N+ injection region 31a among the N trap 3a and P+ injection region 32a.The negative pole that keeps second level monomer M LSCR device, is not connected with metal as the negative pole of cascade structure by the N+ injection region 41a among the P trap 4a and P+ injection region 42a.The N extension of two-stage monomer M LSCR device or N-Tub layer 2a biasing, promptly N-ring (being made of two N+ injection region 21a) suspends, and adopts P-ring (being made of two P+ injection region 22a) to isolate around the two-stage monomer M LSCR device, and P-ring ground connection (GND).
As shown in Figure 3, it is the metal cascade vertical view of first embodiment, the positive pole of every grade of monomer M LSCR device and negative pole all adopt layer of metal 54 to cover, and the cascade between every two-stage monomer M LSCR device adopts two layers of metal 56 to connect, and adopt hole 55 interconnected between layer of metal 54 and two layers of metal 56.
As shown in Figure 4, monomer M LSCR device architecture sectional view for second embodiment of the invention, monomer M LSCR device is basic identical among the structure and first embodiment, the expansion structure that can regard monomer M LSCR device among first embodiment as, difference is: N extension or N-Tub district 2a replace with buried regions 2b, N trap 3a replaces with dark N trap 3b, P trap 4a replaces with dark P trap 4b, be that monomer M LSCR device comprises P type substrate 1b, P type substrate 1b goes up and is buried regions 2b, buried regions 2b goes up and is that well region, well region comprise dark N trap 3b and dark P trap 4b.N+ injection region 41b among N+ injection region 31b, P+ injection region 32b described in the present embodiment among the dark N trap 3b and the dark P trap 4b, the width dimensions of P+ injection region 42b are D1, the width of isolation FOX 5b on dark N trap 3b and the dark P trap 4b is respectively D2, D5, the width of bridge shape P+ injection region 6b in dark N trap 3b is D3, and the width in dark P trap 4b is D4.Regulate the size of D1, D5, D3 and D4, can realize high clamp voltage, choose suitable D3 and D4 value, can be so that clamp voltage moves closer to trigger voltage.
Certainly, in other embodiment, the also replaceable structure of expanding for being correlated with of monomer M LSCR device, with reference to Fig. 3, N extension on the P type substrate 1b or N-Tub layer 2a can replace by shallow doped layer with other N type, N trap 3a can replace by darker than N extension or N-Tub layer 2a (or other shallow doped layer of N type) with doping content, more shallow than N+ injection region 31a N type doped layer, and P trap 4a can replace than N extension or N-Tub layer 2a (or other shallow doped layer of N type) is dark, P+ injection region 42a is shallow P type doped layer with doping content.
As shown in Figure 5, be the cascade structure sectional view of second embodiment, the negative pole of described first order monomer M LSCR device is made of N+ injection region 41b and P+ injection region 42b among the dark P trap 4b; The positive pole of described second level monomer M LSCR device is made of N+ injection region 31b and P+ injection region 32b among the dark N trap 3b; The positive pole of the negative pole of described first order monomer M LSCR device and second level monomer M LSCR device links together by metal.Keep N+ injection region 31b and P+ injection region 32b in the dark N trap of described first order SCR monomer device, as the positive pole of cascade structure.Keep N+ injection region 41b and P+ injection region 42b among the dark P trap of the second level monomer M LSCR device 4b, as the negative pole of cascade structure.The certain interval width of control between the two-stage MLSCR monomer, this interval width value need satisfy that needed minimum value takes place the no latch-up that reaches of appointment in the corresponding process rule, this at interval by P+ injection region 21b connect P type substrate and (GND).
As shown in Figure 6, be current-voltage (I-V) performance plot after the monomer M LSCR device cascade structure TLP of the different numbers test (its hollow core icon indicate be corresponding leakage current value), the diagrammatic representation of monomer M LSCR device, the cascade of two MLSCR devices, the cascade of three MLSCR devices, the cascade of four MLSCR devices is wherein arranged respectively, along with the multiplication of cascade progression, the trigger voltage value of cascade monomer M LSCR device and clamp voltage value be and then multiplication also.By choosing suitable SCR cascade number, can realize not having the power supply clamper electrostatic storage deflection (ESD) protection circuit design of fastening the effect that contracts with a bolt or latch.
The present invention is not limited to above-mentioned execution mode, for those skilled in the art, under the prerequisite that does not break away from the principle of the invention, can also make some improvements and modifications, and these improvements and modifications also are considered as within protection scope of the present invention.
Claims (9)
1. one kind is applied to power supply clamper structure in the high-pressure process integrated circuit, comprises monomer M LSCR device, and described monomer M LSCR device comprises P trap and N trap, it is characterized in that; One bridge shape P+ injection region is arranged between described P trap and the N trap, and the size adjustment scope of described bridge shape P+ injection region is between 2.5um～10.0um.
2. as claimed in claim 1ly be applied to power supply clamper structure in the high-pressure process integrated circuit, it is characterized in that: described monomer M LSCR device comprises P type substrate, on the P type substrate N extension or N-Tub layer, be well region on N extension or the N-Tub layer, well region comprises N trap and P trap, be equipped with two injection regions on N trap and the P trap, be respectively N+ injection region and P+ injection region.
3. as claimed in claim 2ly be applied to power supply clamper structure in the high-pressure process integrated circuit, it is characterized in that: the N+ injection region of described N trap is arranged on the end away from the P trap, and the P+ injection region is arranged on the end near the P trap; The P+ injection region of P trap is arranged on the end away from the N trap, and the N+ injection region is arranged on the end near the N trap; Isolate by FOX between N+ injection region and the P+ injection region.
4. as claimed in claim 1ly be applied to power supply clamper structure in the high-pressure process integrated circuit, it is characterized in that: described monomer M LSCR device comprises P type substrate, is buried regions on the P type substrate, is well region on the buried regions, and well region comprises dark N trap and dark P trap.
5. one kind is applied to power supply clamper structure in the high-pressure process integrated circuit, comprise the cascade structure that the monomer M LSCR device described at least two claims 1 forms, it is characterized in that: the negative pole of described each upper level monomer M LSCR device is connected by metal with the positive pole of next stage monomer M LSCR device, and the positive pole of the just very cascade structure of first order monomer M LSCR device, the negative pole of afterbody monomer M LSCR device is the negative pole of cascade structure.
6. as claimed in claim 5ly be applied to power supply clamper structure in the high-pressure process integrated circuit, it is characterized in that: described monomer M LSCR device adopts N-ring to isolate, adopt P-ring to isolate between the monomer M LSCR device, N-ring isolates suspension, and P-ring isolates ground connection.
7. as claimed in claim 5ly be applied to power supply clamper structure in the high-pressure process integrated circuit, it is characterized in that: each described monomer M LSCR device comprises P type substrate, on the P type substrate N extension or N-Tub layer, be well region on N extension or the N-Tub layer, well region comprises N trap and P trap, be equipped with two injection regions on N trap and the P trap, be respectively N+ injection region and P+ injection region.
8. as claimed in claim 7ly be applied to power supply clamper structure in the high-pressure process integrated circuit, it is characterized in that: the N+ injection region of each described N trap is arranged on the end away from the P trap, and the P+ injection region is arranged on the end near the P trap; The P+ injection region of P trap is arranged on the end away from the N trap, and the N+ injection region is arranged on the end near the N trap; Isolate by FOX between N+ injection region and the P+ injection region.
9. as claimed in claim 5ly be applied to power supply clamper structure in the high-pressure process integrated circuit, it is characterized in that: each described monomer M LSCR device comprises P type substrate, is buried regions on the P type substrate, is well region on the buried regions, and well region comprises dark N trap and dark P trap.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103872038A (en) * | 2012-12-10 | 2014-06-18 | 旺宏电子股份有限公司 | TRIAC device, manufacturing method thereof and circuit comprising the device |
| CN104269401A (en) * | 2014-08-30 | 2015-01-07 | 电子科技大学 | Novel ESD protection device based on SCR structure |
| CN107275324A (en) * | 2016-04-08 | 2017-10-20 | 旺宏电子股份有限公司 | Electrostatic discharge protective equipment and method |
| CN109616509A (en) * | 2018-08-30 | 2019-04-12 | 晶焱科技股份有限公司 | Reversible thyristor |
| CN113437063A (en) * | 2021-06-28 | 2021-09-24 | 吉安砺芯半导体有限责任公司 | MOS triggers SCR device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050151160A1 (en) * | 2004-01-13 | 2005-07-14 | Intersil Americas Inc. | On-chip structure for electrostatic discharge (ESD) protection |
-
2011
- 2011-02-14 CN CN 201110037055 patent/CN102169881B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050151160A1 (en) * | 2004-01-13 | 2005-07-14 | Intersil Americas Inc. | On-chip structure for electrostatic discharge (ESD) protection |
Non-Patent Citations (1)
| Title |
|---|
| 《Journal of Electrostatics》 19991231 Ker M.D. et al How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on "5. Design of the stacked LVTSCR's"，图11 5-9 , 第47期 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103872038A (en) * | 2012-12-10 | 2014-06-18 | 旺宏电子股份有限公司 | TRIAC device, manufacturing method thereof and circuit comprising the device |
| CN103872038B (en) * | 2012-12-10 | 2016-05-18 | 旺宏电子股份有限公司 | Two-way three utmost point grid current body devices and manufacture method thereof and the circuit that comprises this device |
| CN104269401A (en) * | 2014-08-30 | 2015-01-07 | 电子科技大学 | Novel ESD protection device based on SCR structure |
| CN104269401B (en) * | 2014-08-30 | 2017-03-29 | 电子科技大学 | A kind of new E SD protection device based on SCR structure |
| CN107275324A (en) * | 2016-04-08 | 2017-10-20 | 旺宏电子股份有限公司 | Electrostatic discharge protective equipment and method |
| CN109616509A (en) * | 2018-08-30 | 2019-04-12 | 晶焱科技股份有限公司 | Reversible thyristor |
| CN109616509B (en) * | 2018-08-30 | 2022-04-01 | 晶焱科技股份有限公司 | Bidirectional silicon controlled rectifier |
| CN113437063A (en) * | 2021-06-28 | 2021-09-24 | 吉安砺芯半导体有限责任公司 | MOS triggers SCR device |
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