CN101017819A - A protection circuit for constructing ESD release channel with the polycrystalline silicon - Google Patents
A protection circuit for constructing ESD release channel with the polycrystalline silicon Download PDFInfo
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- CN101017819A CN101017819A CN 200710067517 CN200710067517A CN101017819A CN 101017819 A CN101017819 A CN 101017819A CN 200710067517 CN200710067517 CN 200710067517 CN 200710067517 A CN200710067517 A CN 200710067517A CN 101017819 A CN101017819 A CN 101017819A
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Abstract
The related static discharge protection circuit comprises: based on current SCR, setting a multicrysta silicon layer and a SiO2 layer between the last layer and trap area, a P+ and N+ multicrystal injection area on sides of the silicon layer, and an intrinsic multicrystal silicon area on midst. This invention sets throughole on two layers and STI on trap area corresponding to the throughhole, arranges a N+ injection area in the STI, equal to the parallel connection of a P-I-N or N-I-P mutlicrystal silicon and a SCR, improves protection capacity, and convenient to adjust the trigger voltage of this protection circuit.
Description
Technical field
The invention belongs to technical field of integrated circuits, particularly a kind of electrostatic storage deflection (ESD) protection circuit of utilizing polysilicon domain schichtenaufbau electrostatic induced current leakage path.
Background technology
Static discharge is under the situation of an integrated circuit suspension joint, and a large amount of electric charges pours into the instantaneous process of integrated circuit from outside to inside, the about 100ns consuming time of whole process.In addition, can produce the high pressure of hundreds if not thousands of volts when integrated circuit discharges, this can punch the gate oxide of the input stage in the integrated circuit.Along with the size of the metal-oxide-semiconductor in the integrated circuit is more and more littler, the thickness of gate oxide is also more and more thinner, and under this trend, to be without prejudice be very essential with the protection grid oxic horizon for the electric charge of static discharge to use high performance electrostatic discharge protection circuit to release.
The pattern of static discharge phenomenon mainly contains four kinds: human body discharge mode (HBM), mechanical discharge mode (MM), part charging mode (CDM) and electric field induction pattern (FIM).Concerning general integrated circuit (IC) products, generally to pass through human body discharge mode, the test of mechanical discharge mode and part charging mode.In order to bear so high static discharge voltage, integrated circuit (IC) products must be used the electrostatic discharge protector with high-performance, high tolerance usually.
Resist the purpose that static attacks in order to reach the protection chip; at present existing multiple electrostatic protection device is suggested; such as diode, the metal-oxide-semiconductor of grounded-grid generally acknowledges that wherein the reasonable protective device of effect is controllable silicon SCR (silicon controlled rectifier).The concrete structure of this protective device is a well region on the P type substrate 11 as shown in Figure 1, and well region comprises N trap 12 and P trap 16, and two injection regions are all arranged on N trap 12 and the P trap 16, is respectively N+ injection region 14 and P+ injection region 15.Wherein the N+ injection region of N trap 12 is arranged on the end away from P trap 16, and the P+ injection region is arranged on the end near P trap 16; The P+ injection region of P trap 16 is arranged on the end away from N trap 12, and the N+ injection region is arranged on the end near N trap 12.One N+ injection region is arranged on N trap 12 and top, P trap 16 junctions and is connected across between N trap 12 and the P trap 16, is to isolate with shallow trench isolation STI 13 between all injection regions.The N+ injection region and the P+ injection region of N trap 12 meet electrical anode Anode, and the N+ injection region and the P+ injection region of P trap 16 meet electrical cathode Cathode.Fig. 2 is and the corresponding electrical schematic diagram of this SCR structure.Under the normal running of integrated circuit, electrostatic discharge protector is to be in closing state, can not influence the current potential on the integrated circuit input output joint sheet.And static externally pours into integrated circuit and when producing moment high-tension, this device can be opened conducting, promptly emits electrostatic induced current.But the effect of this controllable silicon SCR antistatic under abominable static environment is not very desirable, and this controllable silicon SCR trigger point voltage value can not be adjusted neatly simultaneously.
Summary of the invention
Purpose of the present invention is exactly at the deficiencies in the prior art, provides a kind of and can adjust the trigger point voltage value flexibly, and can effectively improve the protection circuit of protection electrostatic capacity.
Electrostatic storage deflection (ESD) protection circuit of the present invention comprises P type substrate, is well region on the P type substrate, and well region comprises N trap and P trap.Being equipped with two injection regions on N trap and the P trap, is respectively N+ injection region and P+ injection region.Wherein the N+ injection region of N trap is arranged on the end away from the P trap, and the P+ injection region is arranged on the end near the P trap; The P+ injection region of P trap is arranged on the end away from the N trap, and the N+ injection region is arranged on the end near the N trap; N+ injection region on N trap and the P trap and P+ injection region isolate with shallow trench isolation STI.The position is provided with polysilicon layer between the N+ injection region of the P+ injection region of corresponding N trap above the well region and P trap, between polysilicon layer and the well region SiO is set
2Oxide layer, one side the p type impurity that mixes of polysilicon layer forms P+ polysilicon injection region, another side mixes N type impurity and forms N+ polysilicon injection region, the centre is the intrinsic polysilicon district.Intrinsic polysilicon district and SiO
2Be equipped with through hole on the oxide layer, the position of corresponding through hole is provided with shallow annular trench isolation STI on the well region, the inwall of through hole is corresponding with the outer of shallow annular trench isolation STI, in the shallow annular trench isolation STI N+ injection region is set, shallow annular trench isolation STI and N+ injection region are connected across between N trap and the P trap.
P type substrate, N trap and P trap among the present invention adopts the structure and the technology of existing controllable silicon SCR correspondence, SiO
2Oxide layer adopts existing general technologies such as deposit to realize.
The present invention has utilized the polysilicon domain schichtenaufbau electrostatic induced current path of releasing on the architecture basics of traditional SCR.If the polysilicon outer end doping p type impurity on the N trap constitutes P+ polysilicon injection region, the polysilicon outer end doped N-type impurity on the P trap constitutes N+ polysilicon injection region.Be equivalent to the polysilicon of a P-I-N structure and traditional controllable silicon SCR parallel connection like this.Therefore, under the situation that does not increase layout area, the passage of the leakage current of electrostatic induced current has increased, and the performance of electrostatic defending has improved.We can adjust the trigger voltage value of P-I-N structure by the length (spacing distance of P+ polysilicon injection region and N+ polysilicon injection region) that changes intrinsic polysilicon simultaneously, and then adjust the trigger voltage value of this protection circuit flexibly.
If the polysilicon outer end doped N-type impurity on the N trap constitutes N+ polysilicon injection region, the polysilicon outer end doping p type impurity on the P trap constitutes P+ polysilicon injection region.Be equivalent to the polysilicon of a N-I-P structure and traditional controllable silicon SCR parallel connection like this.Therefore, under the situation that does not increase layout area, the passage of the leakage current of electrostatic induced current has increased, and the performance of electrostatic defending has improved.We can adjust the trigger voltage value of N-I-P structure by the length (spacing distance of P+ polysilicon injection region and N+ polysilicon injection region) that changes intrinsic polysilicon simultaneously, and then adjust the trigger voltage value of this protection circuit flexibly.
Description of drawings
Fig. 1 is the profile of the controllable silicon SCR electrostatic discharge protection component of prior art;
Fig. 2 is the equivalent electric schematic diagram of Fig. 1;
Fig. 3 is the profile of the embodiment of the invention;
Fig. 4 is the vertical view of Fig. 3;
Fig. 5 is the equivalent electric schematic diagram of Fig. 3.
Embodiment
The present invention will be further described in conjunction with Figure of description and embodiment.
As shown in Figure 3 and Figure 4, a kind of protection circuit that utilizes polysilicon to make up the ESD leakage path comprises P type substrate 30, is well region on the P type substrate 30, and well region comprises N trap 31 and P trap 39.Being equipped with two injection regions on N trap 31 and the P trap 39, is respectively N+ injection region 32a and P+ injection region 34.Wherein the N+ injection region 32a of N trap 31 is arranged on the end away from P trap 39, and P+ injection region 34 is arranged on the end near P trap 39; The P+ injection region 34 of P trap 39 is arranged on the end away from N trap 31, and N+ injection region 32a is arranged on the end near N trap 31; N+ injection region 32a on N trap 31 and the P trap 39 and the shallow trench isolation STI of P+ injection region 34 usefulness 33a isolate.The position is provided with polysilicon layer between the N+ injection region 32a of the P+ injection region 34 of corresponding N trap 31 above the well region and P trap 39, between polysilicon layer and the well region SiO is set
2 Oxide layer 38, one side the p type impurity that mixes of polysilicon layer forms P+ polysilicon injection region 35, another side mixes N type impurity and forms N+ polysilicon injection region 37, the centre is intrinsic polysilicon district 36.Intrinsic polysilicon district 36 and SiO
2Be equipped with through hole 41 on the oxide layer 38, the position of corresponding through hole 41 is provided with shallow annular trench isolation STI 33b on the well region, the inwall of through hole 41 is corresponding with the outer of shallow annular trench isolation STI 33b, in the shallow annular trench isolation STI 33b N+ injection region 32b is set, shallow annular trench isolation STI 33b and N+ injection region 32b are connected across between N trap 31 and the P trap 39.
In the work, if the polysilicon outer end doping p type impurity on the N trap constitutes P+ polysilicon injection region, the polysilicon outer end doped N-type impurity on the P trap constitutes N+ polysilicon injection region.Be equivalent to the polysilicon of a P-I-N structure and traditional controllable silicon SCR parallel connection (as shown in Figure 5) like this.When electrical anode input normal signal level, this protective device can conducting disturb the operate as normal of chip internal circuit.And when the electrostatic signal of danger arrives, thereby the intrinsic polysilicon forward connects the electrostatic induced current of releasing, thus make input buffer 51 can resist extraneous electrostatic impact.
Claims (1)
1, a kind of protection circuit that utilizes polysilicon to make up the ESD leakage path, comprise P type substrate (30), P type substrate (30) is gone up and is well region, well region comprises N trap (31) and P trap (39), it is characterized in that being equipped with two injection regions on N trap (31) and the P trap (39), is respectively N+ injection region (32a) and P+ injection region (34); Wherein the N+ injection region (32a) of N trap (31) is arranged on the end away from P trap (39), and P+ injection region (34) are arranged on the end near P trap (39); The P+ injection region (34) of P trap (39) is arranged on the end away from N trap (31), and N+ injection region (32a) is arranged on the end near N trap (31); N+ injection region (32a) and P+ injection region (34) on N trap (31) and the P trap (39) isolate with shallow trench isolation STI (33a);
The position is provided with polysilicon layer between the N+ injection region (32a) of the P+ injection region (34) of corresponding N trap (31) above the well region and P trap (39), between polysilicon layer and the well region SiO is set
2Oxide layer (38), one side the p type impurity that mixes of polysilicon layer forms P+ polysilicon injection region (35), another side mixes N type impurity and forms N+ polysilicon injection region (37), the centre is intrinsic polysilicon district (36);
Intrinsic polysilicon district (36) and SiO
2Be equipped with through hole (41) on the oxide layer (38), the position of corresponding through hole (41) is provided with shallow annular trench isolation STI (33b) on the well region, and the inwall of through hole (41) is corresponding with the outer of shallow annular trench isolation STI (33b); N+ injection region (32b) is set in the shallow annular trench isolation STI (33b), and shallow annular trench isolation STI (33b) and N+ injection region (32b) are connected across between N trap (31) and the P trap (39).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100675172A CN100470804C (en) | 2007-03-05 | 2007-03-05 | A protection circuit for constructing ESD release channel with the polycrystalline silicon |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100675172A CN100470804C (en) | 2007-03-05 | 2007-03-05 | A protection circuit for constructing ESD release channel with the polycrystalline silicon |
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| CN101017819A true CN101017819A (en) | 2007-08-15 |
| CN100470804C CN100470804C (en) | 2009-03-18 |
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| CNB2007100675172A Expired - Fee Related CN100470804C (en) | 2007-03-05 | 2007-03-05 | A protection circuit for constructing ESD release channel with the polycrystalline silicon |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102244105A (en) * | 2011-06-20 | 2011-11-16 | 北京大学 | Thyristor with high hold voltage and low triggering voltage ESD (electronstatic discharge) characteristic |
| CN101236967B (en) * | 2008-03-05 | 2012-04-11 | 浙江大学 | A built-in controllable silicon for reverse phase part |
| CN102623450A (en) * | 2012-03-30 | 2012-08-01 | 浙江大学 | Transient voltage suppressor based on field limiting ring silicon controlled structure |
| CN106876369A (en) * | 2017-03-01 | 2017-06-20 | 中国电子科技集团公司第五十八研究所 | For the silicon controlled rectifier (SCR) and preparation method of thin epitaxy technique electrostatic discharge (ESD) protection |
| WO2020114409A1 (en) * | 2018-12-05 | 2020-06-11 | 无锡华润上华科技有限公司 | Preparation method for semiconductor device |
| CN112466938A (en) * | 2020-11-26 | 2021-03-09 | 中国科学院微电子研究所 | Silicon controlled rectifier device applied to electrostatic protection of deep submicron circuit |
-
2007
- 2007-03-05 CN CNB2007100675172A patent/CN100470804C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101236967B (en) * | 2008-03-05 | 2012-04-11 | 浙江大学 | A built-in controllable silicon for reverse phase part |
| CN102244105A (en) * | 2011-06-20 | 2011-11-16 | 北京大学 | Thyristor with high hold voltage and low triggering voltage ESD (electronstatic discharge) characteristic |
| CN102244105B (en) * | 2011-06-20 | 2013-07-03 | 北京大学 | Thyristor with high hold voltage and low triggering voltage ESD (electronstatic discharge) characteristic |
| CN102623450A (en) * | 2012-03-30 | 2012-08-01 | 浙江大学 | Transient voltage suppressor based on field limiting ring silicon controlled structure |
| CN102623450B (en) * | 2012-03-30 | 2014-12-03 | 浙江大学 | Transient voltage suppressor based on field limiting ring silicon controlled structure |
| CN106876369A (en) * | 2017-03-01 | 2017-06-20 | 中国电子科技集团公司第五十八研究所 | For the silicon controlled rectifier (SCR) and preparation method of thin epitaxy technique electrostatic discharge (ESD) protection |
| WO2020114409A1 (en) * | 2018-12-05 | 2020-06-11 | 无锡华润上华科技有限公司 | Preparation method for semiconductor device |
| CN112466938A (en) * | 2020-11-26 | 2021-03-09 | 中国科学院微电子研究所 | Silicon controlled rectifier device applied to electrostatic protection of deep submicron circuit |
| CN112466938B (en) * | 2020-11-26 | 2023-11-14 | 中国科学院微电子研究所 | Silicon controlled device applied to deep submicron-level circuit electrostatic protection |
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| CN100470804C (en) | 2009-03-18 |
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