CN201041806Y - An ESD protection part for enlarging valid pass area of static current - Google Patents
An ESD protection part for enlarging valid pass area of static current Download PDFInfo
- Publication number
- CN201041806Y CN201041806Y CNU2007201069461U CN200720106946U CN201041806Y CN 201041806 Y CN201041806 Y CN 201041806Y CN U2007201069461 U CNU2007201069461 U CN U2007201069461U CN 200720106946 U CN200720106946 U CN 200720106946U CN 201041806 Y CN201041806 Y CN 201041806Y
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- trap
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- 230000003068 static effect Effects 0.000 title abstract description 16
- 238000002347 injection Methods 0.000 claims abstract description 120
- 239000007924 injection Substances 0.000 claims abstract description 120
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- 229920005591 polysilicon Polymers 0.000 claims description 32
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 14
- 230000001681 protective effect Effects 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 230000005611 electricity Effects 0.000 abstract 5
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 238000005516 engineering process Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000001012 protector Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
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Abstract
The utility model relates to a static electricity discharge safeguard device. The static electricity safeguarding effect of the prior silicon controlled rectifier (SCR) is unideal. A polycrystalline silicon layer and a SiO2 oxidized layer are arranged on the upside of a trap area of the utility model. The lengths of the polycrystalline silicon layer and a SiO2 oxidized layer are more than or equal to the distance between the side face of a P plus injection area of a N trap near a P trap and the side face of a N plus injection area of the P trap near the N trap. Through holes corresponding to the injection areas are arranged on the polycrystalline silicon layer and the SiO2 oxidized layer. The utility model can ensure that a center N plus injection area, the N plus injection area, and the P plus injection area can pass through the through holes to be injected into corresponding trap areas; can improve the effective static current discharge area greatly; can discharge the static current more evenly, more dispersedly, and more quickly; can improve the static electricity tolerance of the static electricity discharge safeguarding circuit; and can improve the static electricity discharge safeguarding capability.
Description
Technical field
The utility model belongs to technical field of integrated circuits, and is particularly a kind of under the condition that does not change technology, saves layout, increases the release electrostatic discharge protection component of effective area of electrostatic induced current.
Background technology
Static discharge is under the situation of an integrated circuit suspension joint, and a large amount of electric charges pours into the instantaneous process of integrated circuit from outside to inside, the about 100ns consuming time of whole process.In addition, can produce the high pressure of hundreds if not thousands of volts when integrated circuit discharges, this can punch the gate oxide of the input stage in the integrated circuit.Along with the size of the metal-oxide-semiconductor in the integrated circuit is more and more littler, the thickness of gate oxide is also more and more thinner, and under this trend, to be without prejudice be very essential with the protection grid oxic horizon for the electric charge of static discharge to use high performance electrostatic protection device to release.
The pattern of static discharge phenomenon mainly contains four kinds: human body discharge mode (HBM), mechanical discharge mode (MM), part charging mode (CDM) and electric field induction pattern (FIM).Concerning general integrated circuit (IC) products, generally to pass through human body discharge mode, the test of mechanical discharge mode and part charging mode.In order to bear so high static discharge voltage, integrated circuit (IC) products must be used the electrostatic discharge protector with high-performance, high tolerance usually.
Resist the purpose that static attacks in order to reach the protection chip; at present existing multiple electrostatic protection device is suggested; such as diode, the metal-oxide-semiconductor of grounded-grid generally acknowledges that wherein the reasonable protective device of effect is controllable silicon SCR (silicon controlled rectifier).The concrete structure of this protective device is a well region on the P type substrate 11 as shown in Figure 1, and well region comprises N trap 12 and P trap 16, and two injection regions are all arranged on N trap 12 and the P trap 16, is respectively N+ injection region 14 and P+ injection region 15.Wherein the N+ injection region of N trap 12 is arranged on the end away from P trap 16, and the P+ injection region is arranged on the end near P trap 16; The P+ injection region of P trap 16 is arranged on the end away from N trap 12, and the N+ injection region is arranged on the end near N trap 12.One N+ injection region is arranged on N trap 12 and top, P trap 16 junctions and is connected across between N trap 12 and the P trap 16, is to isolate with shallow trench isolation STI 13 between all injection regions.The N+ injection region and the P+ injection region of N trap 12 meet electrical anode Anode, and the N+ injection region and the P+ injection region of P trap 16 meet electrical cathode Cathode.Fig. 2 is and the corresponding electrical schematic diagram of this SCR structure.Under the normal running of integrated circuit, electrostatic discharge protector is to be in closing state, can not influence the current potential on the integrated circuit input output joint sheet.And static externally pours into integrated circuit and when producing moment high-tension, this device can be opened conducting, promptly emits electrostatic induced current.But the effect of this controllable silicon SCR antistatic under abominable static environment is not very desirable.
Summary of the invention
The purpose of this utility model is exactly at the deficiencies in the prior art, provides a kind of under the prerequisite that does not increase the chip layout area, increases the effective area of current drain in the SCR substrate and effectively improves the electrostatic discharge protection component of protection electrostatic capacity.
Electrostatic discharge protection component of the present utility model comprises P type substrate, is well region on the P type substrate, and well region comprises N trap and P trap, is equipped with two injection regions on N trap and the P trap, is respectively N+ injection region and P+ injection region.Wherein the N+ injection region of N trap is arranged on the end away from the P trap, and the P+ injection region is arranged on the end near the P trap; The P+ injection region of P trap is arranged on the end away from the N trap, and the N+ injection region is arranged on the end near the N trap; N+ injection region, center is arranged on N trap and top, P trap junction and is connected across between N trap and the P trap.The well region top is provided with polysilicon layer, between polysilicon layer and the well region SiO is set
2Oxide layer.Described polysilicon layer and SiO
2The length of oxide layer is more than or equal to the distance between the close side of N trap in side and P trap N+ injection region of the close P trap in P+ injection region of N trap; Polysilicon layer and SiO
2Oxide layer has the through hole corresponding with the injection region.
Polysilicon layer and SiO
2The P+ injection region that the length of oxide layer equals the N trap near between the side of P trap and the close side of N trap, P trap N+ injection region apart from the time, polysilicon layer and SiO
2Have on the oxide layer and the corresponding through hole in N+ injection region, center, the position of through hole is identical with N+ injection region, center with shape.
Polysilicon layer and SiO
2The length of oxide layer greater than the P+ injection region of N trap near between the side of P trap and the close side of N trap, P trap N+ injection region apart from the time, the polysilicon layer and the SiO of all N+ injection regions, corresponding center, N+ injection region and position, P+ injection region
2Have through hole on the oxide layer, N+ injection region, center, N+ injection region and P+ injection region are identical with the position and the shape of corresponding through hole.
P type substrate, N trap and P trap in the utility model adopts the structure and the technology of existing controllable silicon SCR correspondence, SiO
2Oxide layer adopts existing general technologies such as deposit to realize.
Polysilicon domain layer of the present utility model is a hollow out, can not only make N+ injection region, center can pass through the through hole of polysilicon like this, is connected across between N type trap and the P type trap, at polysilicon layer and SiO
2The length of oxide layer greater than the P+ injection region of N trap near between the side of P trap and the close side of N trap, P trap N+ injection region apart from the time, the through hole that polysilicon can be passed through in corresponding N+injection region in N trap and the P trap and P+ injection region is injected into corresponding well region, so just can improve the effective area that electrostatic induced current is released significantly.So just can additionally not increase under the situation of chip area, the effective area that utilizes the existing processes condition to increase in the SCR substrate makes at electrostatic induced current by in this SCR device, can be more even, more disperse, release quickly, thereby improved the static tolerance of electrostatic discharge protection component, effectively improved the protection electrostatic capacity.
Description of drawings
Fig. 1 is the profile of the controllable silicon SCR electrostatic discharge protection component of prior art;
Fig. 2 is the equivalent electric schematic diagram of Fig. 1;
Fig. 3 is the profile of the utility model one embodiment;
Fig. 4 is the vertical view of Fig. 3;
Fig. 5 is the profile of another embodiment of the utility model;
Fig. 6 is the vertical view of Fig. 5;
Fig. 7 is the profile of the another embodiment of the utility model;
Fig. 8 is the vertical view of Fig. 7.
Embodiment
Below in conjunction with Figure of description and embodiment the utility model is described further.
Embodiment 1:
As shown in Figure 3 and Figure 4, the ESD protective device that increases the electrostatic induced current valid circulation area comprises P type substrate 31, be well region on the P type substrate 31, well region comprises N trap 32 and P trap 39, be equipped with two injection regions on N trap 32 and the P trap 39, be respectively that 35, two injection regions in N+ injection region 33 and P+ injection region isolate by shallow trench isolation STI 34.Wherein the N+ injection region of N trap 32 is arranged on the end away from P trap 39, and the P+ injection region is arranged on the end near P trap 39; The P+ injection region of P trap 39 is arranged on the end away from N trap 32, and the N+ injection region is arranged on the end near N trap 32; N+ injection region, center 36 is arranged on N trap 32 and top, P trap 39 junctions and is connected across between N trap 32 and the P trap 39.The well region top is provided with polysilicon layer 37, between polysilicon layer 37 and the well region SiO is set
2Oxide layer 38.Polysilicon layer 37 and SiO
2The P+ injection region that the length of oxide layer 38 equals N trap 32 is near the distance between the side of P trap 39 and the close side of N trap 32, the N+ injection region of P trap 39.Polysilicon layer 37 and SiO
2Have the through hole 41 corresponding with N+ injection region, center 36 on the oxide layer 38, the position of through hole 41 is identical with N+ injection region 36, center with shape.
Embodiment 2:
As shown in Figure 5 and Figure 6, the ESD protective device that increases the electrostatic induced current valid circulation area comprises P type substrate 51, be well region on the P type substrate 51, well region comprises N trap 52 and P trap 59, be equipped with two injection regions on N trap 52 and the P trap 59, be respectively that 55, two injection regions in N+ injection region 53 and P+ injection region isolate by shallow trench isolation STI 54.Wherein the N+ injection region of N trap 52 is arranged on the end away from P trap 59, and the P+ injection region is arranged on the end near P trap 59; The P+ injection region of P trap 59 is arranged on the end away from N trap 52, and the N+ injection region is arranged on the end near N trap 52; N+ injection region, center 56 is arranged on N trap 52 and top, P trap 59 junctions and is connected across between N trap 52 and the P trap 59.The well region top is provided with polysilicon layer 57, between polysilicon layer 57 and the well region SiO is set
2Oxide layer 58.Polysilicon layer 57 and SiO
2The P+ injection region that the length of oxide layer 58 equals N trap 52 away from the N+ injection region of the side of P trap 59 and P trap 59 away from the distance between the side of N trap 52.Polysilicon layer 57 and SiO
2Have the through hole 61 corresponding on the oxide layer 58 with N+ injection region, center 56, and with N trap 52 in N+ injection region corresponding groove 62 in P+ injection region and the P trap 59, the position of through hole 61 is identical with N+ injection region 56, center with shape, and the position of groove 62 is identical with the P+ injection region with corresponding N+ injection region with shape.
Embodiment 3:
As shown in Figure 7 and Figure 8, the ESD protective device that increases the electrostatic induced current valid circulation area comprises P type substrate 71, is well region on the P type substrate 71, and well region comprises N trap 72 and P trap 78, being equipped with two injection regions on N trap 72 and the P trap 78, is respectively N+ injection region 73 and P+ injection region 74.Wherein the N+ injection region of N trap 72 is arranged on the end away from P trap 78, and the P+ injection region is arranged on the end near P trap 78; The P+ injection region of P trap 78 is arranged on the end away from N trap 72, and the N+ injection region is arranged on the end near N trap 72; N+ injection region, center 75 is arranged on N trap 72 and top, P trap 78 junctions and is connected across between N trap 72 and the P trap 78.The well region top is provided with polysilicon layer 76, between polysilicon layer 76 and the well region SiO is set
2Oxide layer 77.Polysilicon layer 76 and SiO
2The N+ injection region that the length of oxide layer 77 equals N trap 72 away from the P+ injection region of the side of P trap 78 and P trap 78 away from the distance between the side of N trap 72.Polysilicon layer 76 and SiO
2Have on the oxide layer 77 and the P+ injection region of N+ injection region, center 75, N trap 72 and the corresponding through hole 81 in N+ injection region of P trap 78, and with N trap 72 in P+ injection region corresponding groove 82 in N+ injection region and the P trap 78.The P+ injection region of the position of through hole 81 and shape and N+ injection region, center, N trap is identical with the N+ injection region of P trap, and the position of groove 82 is identical with the P+ injection region with corresponding N+ injection region with shape.
Claims (3)
1. ESD protective device that increases the electrostatic induced current valid circulation area, comprise P type substrate, be well region on the P type substrate, well region comprises N trap and P trap, be equipped with two injection regions on N trap and the P trap, be respectively N+ injection region and P+ injection region, wherein the N+ injection region of N trap is arranged on the end away from the P trap, the P+ injection region is arranged on the end near the P trap, the P+ injection region of P trap is arranged on the end away from the N trap, and the N+ injection region is arranged on the end near the N trap, and N+ injection region, center is arranged on N trap and top, P trap junction and is connected across between N trap and the P trap, it is characterized in that described well region top is provided with polysilicon layer, is provided with SiO between polysilicon layer and the well region
2Oxide layer; Described polysilicon layer and SiO
2The length of oxide layer is more than or equal to the distance between the close side of N trap in side and P trap N+ injection region of the close P trap in P+ injection region of N trap; Polysilicon layer and SiO
2Oxide layer has the through hole corresponding with the injection region.
2. a kind of ESD protective device that increases the electrostatic induced current valid circulation area as claimed in claim 1 is characterized in that polysilicon layer and SiO
2The length of oxide layer is identical near the distance between the side of N trap near the side and the P trap N+ injection region of P trap with the P+ injection region of N trap, polysilicon layer and SiO
2Have on the oxide layer and the corresponding through hole in N+ injection region, center, the position of through hole is identical with N+ injection region, center with shape.
3. a kind of ESD protective device that increases the electrostatic induced current valid circulation area as claimed in claim 1 is characterized in that polysilicon layer and SiO
2The length of oxide layer is greater than the distance between the close side of N trap in side and P trap N+ injection region of the close P trap in P+ injection region of N trap, the polysilicon layer and the SiO of all N+ injection regions, corresponding center, N+ injection region and position, P+ injection region
2Have through hole on the oxide layer, N+ injection region, center, N+ injection region and P+ injection region are identical with the position and the shape of corresponding through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2007201069461U CN201041806Y (en) | 2007-03-05 | 2007-03-05 | An ESD protection part for enlarging valid pass area of static current |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2007201069461U CN201041806Y (en) | 2007-03-05 | 2007-03-05 | An ESD protection part for enlarging valid pass area of static current |
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| Publication Number | Publication Date |
|---|---|
| CN201041806Y true CN201041806Y (en) | 2008-03-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNU2007201069461U Expired - Fee Related CN201041806Y (en) | 2007-03-05 | 2007-03-05 | An ESD protection part for enlarging valid pass area of static current |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185777A (en) * | 2015-07-30 | 2015-12-23 | 上海华虹宏力半导体制造有限公司 | LVTSCR used for SOI process electrostatic protection, and manufacturing method thereof |
| CN105609488A (en) * | 2015-12-23 | 2016-05-25 | 电子科技大学 | Low-trigger-voltage SCR (semiconductor control rectifier) device used for ESD (electro-static discharge) protection |
| CN106449604A (en) * | 2016-11-23 | 2017-02-22 | 电子科技大学 | SCR (Semiconductor Control Rectifier) with high maintaining voltage for ESD (Electro-Static Discharge) protection |
| CN109698194A (en) * | 2018-12-28 | 2019-04-30 | 电子科技大学 | A kind of Schottky clamper SCR device for ESD protection |
| CN113571513A (en) * | 2021-09-23 | 2021-10-29 | 四川上特科技有限公司 | Low-trigger high-robustness SCR device and protection circuit for transient suppressor |
-
2007
- 2007-03-05 CN CNU2007201069461U patent/CN201041806Y/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185777A (en) * | 2015-07-30 | 2015-12-23 | 上海华虹宏力半导体制造有限公司 | LVTSCR used for SOI process electrostatic protection, and manufacturing method thereof |
| CN105185777B (en) * | 2015-07-30 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | LVTSCR and its manufacture method for SOI technology electrostatic protection |
| CN105609488A (en) * | 2015-12-23 | 2016-05-25 | 电子科技大学 | Low-trigger-voltage SCR (semiconductor control rectifier) device used for ESD (electro-static discharge) protection |
| CN105609488B (en) * | 2015-12-23 | 2018-07-27 | 电子科技大学 | A kind of low trigger voltage SCR device for ESD protections |
| CN106449604A (en) * | 2016-11-23 | 2017-02-22 | 电子科技大学 | SCR (Semiconductor Control Rectifier) with high maintaining voltage for ESD (Electro-Static Discharge) protection |
| CN106449604B (en) * | 2016-11-23 | 2018-08-31 | 电子科技大学 | A kind of SCR with high maintenance voltage for ESD protection |
| CN109698194A (en) * | 2018-12-28 | 2019-04-30 | 电子科技大学 | A kind of Schottky clamper SCR device for ESD protection |
| CN113571513A (en) * | 2021-09-23 | 2021-10-29 | 四川上特科技有限公司 | Low-trigger high-robustness SCR device and protection circuit for transient suppressor |
| CN113571513B (en) * | 2021-09-23 | 2022-01-04 | 四川上特科技有限公司 | Low-trigger high-robustness SCR device and protection circuit for transient suppressor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080326 |