CN103390618A - Embedded gate-grounded N-channel metal oxide semiconductor (NMOS)-triggered silicon-controlled transient voltage suppressor - Google Patents
Embedded gate-grounded N-channel metal oxide semiconductor (NMOS)-triggered silicon-controlled transient voltage suppressor Download PDFInfo
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Abstract
The invention discloses an embedded gate-grounded NMOS-triggered silicon-controlled transient voltage suppressor. The suppressor comprises a P-type substrate, wherein an N trap is transversely arranged on the P-type substrate, a first N+ injection region, a first P+ injection region, a third N+ injection region, a polysilicon gate, a second N+ injection region and a second P+ injection region are transversely and sequentially arranged on the N trap and in an area of the P-type substrate, which is free of the N trap, the first N+ injection region and the first P+ injection region are arranged on the N trap, two ends of the third N+ injection region are arranged on the N trap and the area of the P-type substrate, which is free of the N trap, in a straddling mode respectively, the polysilicon gate, the second N+ injection region and the second P+ injection region are arranged in the area of the P-type substrate, which is free of the N trap, the polysilicon gate, the second N+ injection region and the third N+ injection region constitute an NMOS structure on the P-type substrate, the first N+ injection region, the first P+ injection region and the third N+ injection region are connected with an electrical anode, and the polysilicon gate, the second N+ injection region and the second P+ injection region are connected with an electrical cathode.
Description
Technical field
The present invention relates to the controllable silicon Transient Voltage Suppressor that a kind of embedded gate grounding NMOS triggers, especially relate to a kind ofly for electrostatic defending and have the controllable silicon Transient Voltage Suppressor that the embedded gate grounding NMOS of high maintenance voltage triggers, belong to technical field of integrated circuits.
Background technology
Natural Electrostatic Discharge phenomenon forms serious threat to the reliability of integrated circuit.In industrial quarters, the inefficacy 30% of integrated circuit (IC) products is all owing to suffering static discharge phenomenon caused.And along with the density of integrated circuit is increasing, due to the thickness more and more thinner (from the micron to the nanometer) of silicon dioxide film, the electrostatic pressure that device bears is more and more lower on the one hand; On the other hand, easy material such as the plastics that produce, accumulate static, rubber etc. are a large amount of to be used, and the probability that makes integrated circuit be subject to static discharge destruction increases greatly.
The pattern of static discharge phenomenon is divided into four kinds usually: the HBM(human-body model), MM(machine discharge mode), CDM(assembly charging and discharging pattern) and electric field induction pattern (FIM).And the most common two kinds of static discharge patterns that are also the industrial quarters product must pass through are HBM and MM.When static discharge occurred, electric charge usually flowed into and from the another pin, flows out from a pin of chip, and the electric current that this moment, electrostatic charge produced is usually up to several amperes, and the voltage that produces at the electric charge input pin is up to even tens volts of several volts.Can cause the damage of inside chip if larger ESD electric current flows into inside chip, simultaneously, the high pressure that produces at input pin also can cause internal components generation grid oxygen punch-through, thereby causes circuit malfunction.Therefore, in order to prevent inside chip, damaged by ESD, to each pin of chip, will carry out effective ESD protection, the ESD electric current is released.
Under the normal operating conditions of integrated circuit, electrostatic discharge protector is to be in the state of closing, and can not affect the current potential on input and output pin.And externally static pours into integrated circuit and when producing moment high-tension, this device can be opened conducting, emits rapidly electrostatic induced current.
Yet the continuous progress along with the CMOS manufacturing process; device size constantly reduces; core circuit bears the ESD ability to be reduced greatly; for low pressure IC(integrated circuit) ESD protection for; effective electrostatic discharge protective device must be able to guarantee relatively low trigger voltage (can not higher than the grid oxygen puncture voltage of protected circuit); relatively high keeps voltage (for power supply; will be higher than supply voltage to avoid latch-up); stronger esd protection ability (ESD robustness) is provided, and takies limited layout area.For fear of the breech lock risk, can keep electric current by raising, raising is kept voltage and is solved.Therefore in the advantage that guarantees low trigger voltage, further improve it and keep voltage and seem very necessary.
As a kind of ESD safeguard structure commonly used, controllable silicon is widely used in the protection of integrated circuit die I/O port and power domain.Controllable silicon has the advantages such as high robust, manufacturing process be simple.But controllable silicon also has out speed slow, and cut-in voltage is high, keeps the shortcomings such as voltage is low, to the grid oxic horizon protection of integrated circuit input output metal-oxide-semiconductor, can not play good effect.
Summary of the invention
Purpose:, in order to overcome the deficiencies in the prior art, the invention provides the controllable silicon Transient Voltage Suppressor that a kind of embedded gate grounding NMOS triggers, can improve and keep voltage under the prerequisite that does not affect the protective device trigger voltage, avoid latch-up.
Technical scheme: for solving the problems of the technologies described above, the technical solution used in the present invention is:
The controllable silicon Transient Voltage Suppressor that a kind of embedded gate grounding NMOS triggers, comprise P type substrate, be horizontally arranged with the N trap on described P type substrate, do not establish the zone of N trap on described N trap and P type substrate in, along laterally being provided with successively a N+ injection region, a P+ injection region, the 3rd N+ injection region, polysilicon gate, the 2nd N+ injection region and the 2nd P+ injection region;
Wherein, a described N+ injection region and a P+ injection region are arranged on the N trap, the two ends of described the 3rd N+ injection region are crossed on respectively the N trap and P type substrate is not established on the zone of N trap, and described polysilicon gate, the 2nd N+ injection region and the 2nd P+ injection region are arranged on the zone of not establishing the N trap on P type substrate;
Described polysilicon gate, the 2nd N+ injection region and the 3rd N+ injection region form the NMOS structure on P type substrate;
Electrical anode is all accessed in a described N+ injection region, a P+ injection region and the 3rd N+ injection region, and electrical cathode is all accessed in described polysilicon gate, the 2nd N+ injection region and the 2nd P+ injection region.
the controllable silicon Transient Voltage Suppressor that described embedded gate grounding NMOS triggers, it is characterized in that: isolate by the first shallow-trench isolation between the external structure of a described N+ injection region and P type substrate, isolate by the second shallow-trench isolation between a described N+ injection region and a P+ injection region, isolate by the 3rd shallow-trench isolation between a described P+ injection region and the 3rd N+ injection region, isolate by the 4th shallow-trench isolation between described the 2nd N+ injection region and the 2nd P+ injection region, isolate by the 5th shallow-trench isolation between the external structure of described the 2nd P+ injection region and P type substrate.
Beneficial effect: the controllable silicon Transient Voltage Suppressor that embedded gate grounding NMOS provided by the invention triggers, adopt embedded gate grounding NMOS in controllable silicon, trigger controllable silicon by gate grounding NMOS, have simple in structure, reliable and stable, the advantage such as trigger voltage is low; Can improve and keep voltage under the prerequisite that does not affect the protective device trigger voltage, avoid latch-up.
Description of drawings
Fig. 1 and Fig. 2 are the structural representation of the controllable silicon Transient Voltage Suppressor of the embedded gate grounding NMOS triggering of the present invention;
In figure, P type substrate 1, N trap 2, a N+ injection region 3, a P+ injection region 4, the 3rd N+ injection region 5, the 2nd N+ injection region 6, the 2nd P+ injection region 7, polysilicon gate 8, the first shallow-trench isolation 9a, the second shallow-trench isolation 9b, the 3rd shallow-trench isolation 9c, the 4th shallow-trench isolation 9d, the 5th shallow-trench isolation 9e, contact hole 10.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further described.
P type substrate in the present invention, the N trap, polysilicon gate, N+, P+ injection region structure and shallow-trench isolation, adopt existing standard CMOS integrated circuit fabrication process all can realize.
As depicted in figs. 1 and 2, the controllable silicon TVS that is used for electrostatic defending that a kind of embedded gate grounding NMOS triggers, comprise P type substrate 1, be horizontally arranged with N trap 2 on described P type substrate 1, do not establish the zone of N trap on described N trap 2 and P type substrate 1 in, along laterally being provided with successively a N+ injection region 3, a P+ injection region 4, the 3rd N+ injection region 5, polysilicon gate 8, the 2nd N+ injection region 6 and the 2nd P+ injection region 7;
Wherein, a described N+ injection region 3 and a P+ injection region 4 are arranged on N trap 2, the two ends of described the 3rd N+ injection region 5 are crossed on respectively N trap 2 and P type substrate 1 is not established on the zone of N trap, and described polysilicon gate 8, the 2nd N+ injection region 6 and the 2nd P+ injection region 7 are arranged on the zone of not establishing the N trap on P type substrate 1;
Described polysilicon gate 8, the 2nd N+ injection region 6 and the 3rd N+ injection region 5 form the NMOS structure on P type substrate 1, electrical anode is all accessed in a described N+ injection region 3, a P+ injection region 4 and the 3rd N+ injection region 5, and electrical cathode is all accessed in described polysilicon gate 8, the 2nd N+ injection region 6 and the 2nd P+ injection region 7;
Isolate by the first shallow-trench isolation 9a between the external structure of a described N+ injection region 3 and P type substrate 1, isolate by the second shallow-trench isolation 9b between a described N+ injection region 3 and a P+ injection region 4, isolate by the 3rd shallow-trench isolation 9c between a described P+ injection region 4 and the 3rd N+ injection region 5, isolate by the 4th shallow-trench isolation 9d between described the 2nd N+ injection region 6 and the 2nd P+ injection region 7, isolate by the 5th shallow-trench isolation 9e between the external structure of described the 2nd P+ injection region 7 and P type substrate 1.
After producing the ESD signal, at first the drain electrode PN junction place of the gate grounding NMOS that consists of polysilicon gate 8, the 2nd N+ injection region 6 and the 3rd N+ injection region 5 produces avalanche breakdown.Electronics will flow into the 3rd N+ injection region 5 from the 2nd N+ injection region 6, the one part of current of releasing this moment.Due to the concentration difference of electronics between the 3rd N+ injection region 5 and N trap 2, the electronics in the 3rd N+ injection region 5 will, to diffusion in N trap 2, cause the dead resistance on N trap 2 to have pressure drop so simultaneously.Along with pressure drop reaches certain numerical value, SCR structure is opened, the most electric current of releasing.
, because gate grounding NMOS is different with the silicon controlled trigger voltage, will cause producing the stagnant phenomenon of double back.Keeping voltage can increase along with the increase of distance between N trap 2 and polysilicon gate 8, and simultaneously the robustness of protective device will improve along with the increase of the distance of the contact hole 10 on the 3rd N+ injection region 5 and polysilicon gate 8.Therefore can regulate and keep voltage and robustness by regulating these two distances.
The controllable silicon Transient Voltage Suppressor that embedded gate grounding NMOS provided by the invention triggers, adopt embedded gate grounding NMOS in controllable silicon, by gate grounding NMOS, triggers controllable silicon, have simple in structure, reliable and stable, the advantage such as trigger voltage is low; Can improve and keep voltage under the prerequisite that does not affect the protective device trigger voltage, avoid latch-up.
The above is only the preferred embodiment of the present invention; be noted that for those skilled in the art; under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (2)
1. controllable silicon Transient Voltage Suppressor that embedded gate grounding NMOS triggers, comprise P type substrate, be horizontally arranged with the N trap on described P type substrate, it is characterized in that: do not establish the zone of N trap on described N trap and P type substrate in, along laterally being provided with successively a N+ injection region, a P+ injection region, the 3rd N+ injection region, polysilicon gate, the 2nd N+ injection region and the 2nd P+ injection region;
Wherein, a described N+ injection region and a P+ injection region are arranged on the N trap, the two ends of described the 3rd N+ injection region are crossed on respectively the N trap and P type substrate is not established on the zone of N trap, and described polysilicon gate, the 2nd N+ injection region and the 2nd P+ injection region are arranged on the zone of not establishing the N trap on P type substrate;
Described polysilicon gate, the 2nd N+ injection region and the 3rd N+ injection region form the NMOS structure on P type substrate;
Electrical anode is all accessed in a described N+ injection region, a P+ injection region and the 3rd N+ injection region, and electrical cathode is all accessed in described polysilicon gate, the 2nd N+ injection region and the 2nd P+ injection region.
2. the controllable silicon Transient Voltage Suppressor that triggers of embedded gate grounding NMOS according to claim 1, it is characterized in that: isolate by the first shallow-trench isolation between the external structure of a described N+ injection region and P type substrate, isolate by the second shallow-trench isolation between a described N+ injection region and a P+ injection region, isolate by the 3rd shallow-trench isolation between a described P+ injection region and the 3rd N+ injection region, isolate by the 4th shallow-trench isolation between described the 2nd N+ injection region and the 2nd P+ injection region, isolate by the 5th shallow-trench isolation between the external structure of described the 2nd P+ injection region and P type substrate.
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Cited By (5)
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| CN104810393A (en) * | 2015-04-16 | 2015-07-29 | 江苏艾伦摩尔微电子科技有限公司 | Controllable silicon with double hysteresis characteristics for electrostatic protection |
| CN104810367A (en) * | 2015-04-16 | 2015-07-29 | 江苏艾伦摩尔微电子科技有限公司 | Novel high-area-efficiency and low-triggering silicon controlled |
| CN107393915A (en) * | 2016-05-17 | 2017-11-24 | 无锡华润微电子有限公司 | Transient Voltage Suppressor and its manufacture method |
| WO2021068462A1 (en) * | 2019-07-01 | 2021-04-15 | 上海维安半导体有限公司 | Tvs device using vertical triode to trigger surface silicon controlled rectifier structure |
| CN115863443A (en) * | 2022-12-16 | 2023-03-28 | 扬州国宇电子有限公司 | Transient voltage suppression diode and preparation method thereof |
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| CN103094278A (en) * | 2012-12-09 | 2013-05-08 | 辽宁大学 | Positive channel metal oxide semiconductor (PMOS) embedded low-voltage trigger silicon controlled rectifier (SCR) device for electro-static discharge (ESD) protection |
| CN203351598U (en) * | 2013-07-12 | 2013-12-18 | 江苏艾伦摩尔微电子科技有限公司 | Embedded gate grounded NMOS triggered silicon controlled rectifier transient voltage inhibitor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104810393A (en) * | 2015-04-16 | 2015-07-29 | 江苏艾伦摩尔微电子科技有限公司 | Controllable silicon with double hysteresis characteristics for electrostatic protection |
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| CN107393915B (en) * | 2016-05-17 | 2020-06-12 | 无锡华润微电子有限公司 | Transient voltage suppressor and method of manufacturing the same |
| WO2021068462A1 (en) * | 2019-07-01 | 2021-04-15 | 上海维安半导体有限公司 | Tvs device using vertical triode to trigger surface silicon controlled rectifier structure |
| CN115863443A (en) * | 2022-12-16 | 2023-03-28 | 扬州国宇电子有限公司 | Transient voltage suppression diode and preparation method thereof |
| CN115863443B (en) * | 2022-12-16 | 2023-11-24 | 扬州国宇电子有限公司 | Transient voltage suppression diode and preparation method thereof |
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Effective date of registration: 20210415 Address after: Room 295, block B, science and technology innovation center, 128 Shuanglian Road, Haining Economic Development Zone, Haining City, Jiaxing City, Zhejiang Province Patentee after: Heining Bernstein Biotechnology Co.,Ltd. Address before: 215300 11 / f-1109, No. 1699, Weicheng South Road, Yushan Town, Kunshan City, Suzhou City, Jiangsu Province Patentee before: JIANGSU ALLENMOORE MICROELECTRONICS Co.,Ltd. |
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