CN115863443B - Transient voltage suppression diode and preparation method thereof - Google Patents
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- 238000002955 isolation Methods 0.000 claims description 47
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Abstract
The application discloses a transient voltage suppression diode and a preparation method thereof in the technical field of semiconductor power devices. The diode includes an N-type substrate; the first P type doped region and the second P type doped region are arranged on the upper portion of the N type substrate, the first N type doped region and the third P type doped region are arranged on the upper portion of the first P type doped region, the second N type doped region is arranged on the upper portion of the second P type doped region, an oxide layer I is arranged on the upper portion of the N type substrate, the first metal layer and the second metal layer are arranged above the oxide layer I in a spaced mode, the first metal layer penetrates through the oxide layer I to be in contact with the first N type doped region and the third P type doped region, and the second metal layer penetrates through the oxide layer I to be in contact with the second N type doped region. The anode and the cathode of the diode are both positioned on the front surface of the chip, so that the diode and other protected modules can be integrated on the same chip, and meanwhile, a common anode structure is formed in the diode, so that the surge current and antistatic capacity of the device can be effectively improved.
Description
Technical Field
The application relates to the technical field of semiconductor power devices, in particular to a transient voltage suppression diode and a preparation method thereof.
Background
The transient voltage suppression diode (Transient Voltage Suppressor, TVS) is a diode-form high-efficiency transient voltage protection device that is currently in common use. When the two ends of the TVS device are impacted by reverse transient high voltage, the high impedance of the two ends of the TVS device can be changed into low impedance in a very short time, the surge power reaching thousands of watts is absorbed, and the voltage clamp between the two poles is positioned at a preset value, so that the precise electronic components behind the TVS device can be effectively protected from being damaged by various surge pulses and static electricity.
With the continuous development of integrated circuits, the integration level of various integrated circuits is continuously improved, so that the TVS chip and the protected electronic circuit are required to be integrated on the same chip, the distance between the TVS device and the protected module can be reduced, better protection performance is realized, parasitic influence can be greatly reduced, and packaging cost is reduced. However, most TVS devices commonly used in the market at present are single independent packaging devices, which is difficult to meet the actual demands.
Disclosure of Invention
The application solves the problem that the TVS chip is difficult to integrate with other electronic circuits in the prior art by providing the transient voltage suppression diode and the preparation method thereof, and can be integrated with other electronic circuits on the same chip on the basis of ensuring the performance of the chip.
The embodiment of the application provides a transient voltage suppression diode, which comprises the following components: the semiconductor device comprises an N-type substrate, a first P-type doped region, a second P-type doped region, a first N-type doped region, a second N-type doped region, a third P-type doped region, a first metal layer and a second metal layer;
the first P-type doped region and the second P-type doped region are arranged at the upper part of the N-type substrate, the first N-type doped region and the third P-type doped region are arranged at the upper part of the first P-type doped region, the second N-type doped region is arranged at the upper part of the second P-type doped region, an oxide layer I is arranged above the N-type substrate, the first metal layer and the second metal layer are arranged above the oxide layer I in a spaced manner, the first metal layer penetrates through the oxide layer I and is in contact with the first N-type doped region and the third P-type doped region, and the second metal layer penetrates through the oxide layer I and is in contact with the second N-type doped region;
isolation grooves are formed in two sides of the first P-type doped region and the second P-type doped region respectively, and the depth of the isolation grooves is larger than the junction depth of the first P-type doped region and the second P-type doped region.
The beneficial effects of the above embodiment are that: the first metal layer of the transient voltage suppression diode is used as an anode, the second metal layer is used as a cathode, and the first metal layer and the second metal layer are both positioned on the front surface of the chip, so that the transient voltage suppression diode and other protected modules can be integrated on the same chip, the processing technology of the transient voltage suppression diode can be compatible with the CMOS technology, and the manufacturing technology is simple and easy to implement. The transient voltage suppression diode adopts a trench isolation technology, reduces the occupied area, can greatly reduce the size of the device, thereby reducing the capacitance of the device, and meanwhile, the isolation groove can separate the active areas to prevent the interference of a transverse electric field between the active areas. The first N-type doped region and the third P-type doped region are connected with the first metal layer on the upper surface through an opening penetrating through the first oxide layer to form a common anode structure, so that the surge current and antistatic capacity of the device can be effectively improved.
On the basis of the above embodiments, the present application can be further improved, and specifically, the following steps are provided:
in one embodiment of the present application, an oxide layer two is disposed on an inner wall of the isolation trench, and polysilicon is filled in the isolation trench.
In one embodiment of the present application, the aspect ratio of the isolation trench is 1:10 to 1:20.
In one embodiment of the present application, the third P-type doped region has a concentration less than the first P-type doped region.
The embodiment of the application also provides a preparation method of the transient voltage suppression diode, which comprises the following steps:
s1: growing the first oxide layer on the N-type substrate;
s2: photoetching and developing the first oxide layer and etching four isolation trenches;
s3: growing a second oxide layer on the inner wall surface of the isolation groove, filling the isolation groove with polysilicon, and depositing a TEOS oxide layer above the isolation groove as an interlayer dielectric layer;
s4: photoetching a first window of the first P type doped region and a second P type doped region between adjacent isolation trenches, and performing B impurity implantation and annealing along the first window to form the first P type doped region and the second P type doped region;
s5: photoetching a second window of the first N-type doped region and the second N-type doped region on the front side, and performing Ph impurity implantation and annealing along the second window to form the first N-type doped region and the second N-type doped region;
s6: photoetching a window III of the third P-type doped region on the front side, and carrying out B impurity injection and annealing along the window III to form the third P-type doped region;
s7: and photoetching contact holes on the first N-type doped region, the third P-type doped region and the second N-type doped region, evaporating or depositing AL on the upper surfaces of the first N-type doped region and the third P-type doped region to form a first metal layer, and evaporating or depositing AL on the upper surface of the opening of the second N-type doped region to form a second metal layer.
In one embodiment of the present application, before the second oxide layer is grown in the step S3, a sacrificial oxidation treatment is further performed on the inner wall surface of the isolation trench. And removing lattice damage to the silicon surface caused by the groove etching, and then removing the sacrificial oxidation.
In one embodiment of the present application, in the step S4, the annealing temperature is 1100 ℃ to 1200 ℃ and the annealing time is 2 to 4 hours.
In one embodiment of the present application, in the step S5, the annealing temperature is 950 ℃ to 1050 ℃ and the annealing time is 40 min to 80min.
One or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:
1. the first metal layer of the transient voltage suppression diode is used as an anode, the second metal layer is used as a cathode, and the first metal layer and the second metal layer are both positioned on the front surface of the chip, so that the transient voltage suppression diode and other protected modules can be integrated on the same chip, the processing technology of the transient voltage suppression diode can be compatible with the CMOS technology, and the manufacturing technology is simple and easy to implement.
2. The transient voltage suppression diode adopts a trench isolation technology, reduces the occupied area, can greatly reduce the size of the device, thereby reducing the capacitance of the device, and meanwhile, the isolation groove can separate the active areas to prevent the interference of a transverse electric field between the active areas.
3. The first N-type doped region and the third P-type doped region of the transient voltage suppression diode are connected with the first metal layer on the upper surface through the opening penetrating through the first oxide layer to form a common anode structure, and two carriers of electrons and holes participate in the conducting process during operation, so that the current density is remarkably improved, and the surge current and antistatic capacity of the device can be effectively improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. Like elements or portions are generally identified by like reference numerals throughout the several figures. In the drawings, elements or portions thereof are not necessarily drawn to scale.
FIG. 1 is a schematic diagram of a TVS diode according to the present application;
the semiconductor device comprises a 1N-type substrate, a 2 first P-type doped region, a 3 second P-type doped region, a 4 first N-type doped region, a 5 second N-type doped region, a 6 third P-type doped region, a 7 first metal layer, a 8 second metal layer, a 9 first oxide layer, a 10 second oxide layer and a 11 polysilicon.
Detailed Description
The present application is further illustrated below in conjunction with the specific embodiments, it being understood that these embodiments are meant to be illustrative of the application only and not limiting the scope of the application, and that modifications of the application, which are equivalent to those skilled in the art to which the application pertains, will fall within the scope of the application as defined in the appended claims.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present application, it should be noted that the azimuth or positional relationship indicated by the terms "vertical", "peripheral surface", etc. are based on the azimuth or positional relationship shown in the drawings, or the azimuth or positional relationship that the inventive product is conventionally put in use, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In the description of the present application, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples of the application described and the features of the various embodiments or examples may be combined and combined by those skilled in the art without contradiction.
The embodiment of the application solves the problem that a TVS chip is difficult to integrate with other electronic circuits in the prior art by providing the transient voltage suppression diode and the preparation method thereof, and can be integrated with other electronic circuits on the same chip on the basis of ensuring the performance of the chip.
The technical scheme in the embodiment of the application aims to solve the problems, and the overall thought is as follows:
example 1:
as shown in fig. 1, a transient voltage suppression diode, comprising: the semiconductor device comprises an N-type substrate 1, a first P-type doped region 2, a second P-type doped region 3, a first N-type doped region 4, a second N-type doped region 5, a third P-type doped region 6, a first metal layer 7 and a second metal layer 8;
the first P-type doped region 2 and the second P-type doped region 3 are arranged at the upper part of the N-type substrate 1 at intervals, the first N-type doped region 4 and the third P-type doped region 6 are arranged at the upper part of the first P-type doped region 2 at intervals, the second N-type doped region 5 is arranged at the upper part of the second P-type doped region 3, an oxide layer I9 is arranged above the N-type substrate 1, the concentration of the third P-type doped region 6 is smaller than that of the first P-type doped region 2, the first metal layer 7 and the second metal layer 8 are arranged above the oxide layer I9 at intervals, the first metal layer 7 penetrates through the oxide layer I9 to be in contact with the first N-type doped region 4 and the third P-type doped region 6, and the second metal layer 8 penetrates through the oxide layer I9 to be in contact with the second N-type doped region 5;
isolation trenches are respectively arranged at two sides of the first P-type doped region 2 and the second P-type doped region 3, the depth of each isolation trench is larger than the junction depth of the first P-type doped region 2 and the second P-type doped region 3, an oxide layer II 10 is arranged on the inner wall of each isolation trench, polysilicon 11 is filled in each isolation trench, and the width-depth ratio of each isolation trench is 1:10-1:20.
Example 2:
a method for preparing a transient voltage suppressing diode as described in example 1, as shown in fig. 1, comprising the steps of:
s1: an oxide layer 9 is grown on the N-type substrate 1.
As or Ph is adopted As doping impurity of the N-type substrate 1, and the resistivity is 0.03-0.08 omega cm.
S2: four isolation trenches are lithographically developed and etched in oxide layer one 9.
The method comprises the following steps: and (3) coating photoresist on the oxide layer, determining the position of the isolation groove by photoetching development, etching the isolation groove by adopting a Reactive Ion Etching (RIE) technology with good anisotropism, wherein the depth of the isolation groove is 6-10 mu m, and the width-depth ratio of the isolation groove is generally 1:10-1:20. And removing the photoresist, then carrying out sacrificial oxidation on the surface of the isolation groove, removing lattice damage on the silicon surface caused by the isolation groove etching, and then removing the sacrificial oxidation.
S3: and growing a second oxide layer 10 on the inner wall surface of the isolation groove, filling the isolation groove by using polysilicon 11, and depositing a TEOS oxide layer above the isolation groove as an interlayer dielectric layer.
The method comprises the following steps: and growing a second oxide layer 10 on the surface of the isolation groove, filling the isolation groove with polysilicon 11 to ensure the top of the isolation groove to be closed, removing the polysilicon 11 on the surface by a dry method, and depositing a TEOS oxide layer as a dielectric layer between a subsequent metal layer and the polysilicon to prevent the metal from directly contacting the polysilicon to cause short circuit. .
S4: and photoetching windows I of the first P type doped region 2 and the second P type doped region 3 on the front surface between adjacent isolation trenches, and carrying out B impurity implantation and annealing along the windows I to form the first P type doped region 2 and the second P type doped region 3.
Wherein: the implantation energy is 80-100 KeV, the implantation dosage is 5E 14-1E 15cm < -2 >, the implantation angle is 7 degrees, the annealing temperature is 1100-1200 ℃, the time is 2-4 h, and the junction depth is 3-5 mu m. Annealing is accompanied by a thin oxide layer.
S5: and photoetching a second window of the first N-type doped region 4 and the second N-type doped region 5 on the front surface, and performing Ph impurity implantation and annealing along the second window to form the first N-type doped region 4 and the second N-type doped region 5.
Wherein the implantation energy is 60-80 KeV, the implantation dosage is 1E 15-1E 16cm < -2 >, the implantation angle is 7 degrees, the annealing temperature is 950-1050 ℃, the time is 40-80 min, and the junction depth is 1-3 mu m. Annealing is accompanied by a thin oxide layer.
S6: and photoetching a window III of the third P-type doped region 6 on the front surface, and carrying out B impurity implantation and annealing along the window III to form the third P-type doped region 6.
Wherein the implantation energy is 60KeV, the implantation dosage is 5E 13-1E 14cm < -2 >, the implantation angle is 7 degrees, the annealing temperature is 900 ℃, and the time is 30min.
S7: contact holes are formed in the first N-type doped region 4, the third P-type doped region 6 and the second N-type doped region 5 in a photoetching mode, an AL is evaporated or deposited on the upper surfaces of the first N-type doped region 4 and the third P-type doped region 6 to form a first metal layer 7, and an AL is evaporated or deposited on the upper surface of the opening of the second N-type doped region 5 to form a second metal layer 8.
Wherein the first metal layer 7 serves as an anode and the second metal layer 8 serves as a cathode.
The technical scheme provided by the embodiment of the application at least has the following technical effects or advantages:
1. the first metal layer of the transient voltage suppression diode is used as an anode, the second metal layer is used as a cathode, and the first metal layer and the second metal layer are both positioned on the front surface of the chip, so that the transient voltage suppression diode and other protected modules can be integrated on the same chip, the processing technology of the transient voltage suppression diode can be compatible with the CMOS technology, and the manufacturing technology is simple and easy to implement.
2. The transient voltage suppression diode adopts a trench isolation technology, reduces the occupied area, can greatly reduce the size of the device, thereby reducing the capacitance of the device, and meanwhile, the isolation groove can separate the active areas to prevent the interference of a transverse electric field between the active areas.
3. The first N-type doped region and the third P-type doped region of the transient voltage suppression diode are connected with the first metal layer through the opening penetrating through the first oxide layer on the upper surface to form a common anode structure, so that the surge current and antistatic capacity of the device can be effectively improved.
While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.
Claims (6)
1. A transient voltage suppression diode, comprising: the semiconductor device comprises an N-type substrate, a first P-type doped region, a second P-type doped region, a first N-type doped region, a second N-type doped region, a third P-type doped region, a first metal layer and a second metal layer; the first P-type doped region and the second P-type doped region are arranged at the upper part of the N-type substrate, the first N-type doped region and the third P-type doped region are arranged at the upper part of the first P-type doped region, the concentration of the third P-type doped region is smaller than that of the first P-type doped region, the second N-type doped region is arranged at the upper part of the second P-type doped region, an oxide layer I is arranged above the N-type substrate, the first metal layer and the second metal layer are arranged above the oxide layer I in a spaced manner, the first metal layer penetrates through the oxide layer I and is in contact with the first N-type doped region and the third P-type doped region, and the second metal layer penetrates through the oxide layer I and is in contact with the second N-type doped region; isolation grooves are formed in two sides of the first P-type doped region and two sides of the second P-type doped region respectively, an oxide layer II is arranged on the inner wall of the isolation groove, polysilicon is filled in the isolation groove, and the depth of the isolation groove is larger than the junction depth of the first P-type doped region and the second P-type doped region.
2. The transient voltage suppression diode of claim 1, wherein: the width-depth ratio of the isolation trench is 1:10-1:20.
3. A method of manufacturing a tvs diode according to any one of claims 1-2, comprising the steps of:
s1: growing the first oxide layer on the N-type substrate;
s2: photoetching and developing the first oxide layer and etching four isolation trenches;
s3: growing a second oxide layer on the inner wall surface of the isolation groove, filling the isolation groove with polysilicon, and depositing a TEOS oxide layer above the isolation groove as an interlayer dielectric layer;
s4: photoetching a first window of the first P type doped region and a second P type doped region between adjacent isolation trenches, and performing B impurity implantation and annealing along the first window to form the first P type doped region and the second P type doped region;
s5: photoetching a second window of the first N-type doped region and the second N-type doped region on the front side, and performing Ph impurity implantation and annealing along the second window to form the first N-type doped region and the second N-type doped region;
s6: photoetching a window III of the third P-type doped region on the front side, and carrying out B impurity injection and annealing along the window III to form the third P-type doped region;
s7: and photoetching contact holes on the first N-type doped region, the third P-type doped region and the second N-type doped region, evaporating or depositing AL on the upper surfaces of the first N-type doped region and the third P-type doped region to form a first metal layer, and evaporating or depositing AL on the upper surface of the opening of the second N-type doped region to form a second metal layer.
4. A method of preparation according to claim 3, characterized in that: and the step S3 is to perform sacrificial oxidation treatment on the inner wall surface of the isolation groove before the second oxide layer is grown.
5. A method of preparation according to claim 3, characterized in that: in the step S4, the annealing temperature is 1100-1200 ℃ and the annealing time is 2-4 hours.
6. A method of preparation according to claim 3, characterized in that: in the step S5, the annealing temperature is 950-1050 ℃, and the annealing time is 40-80 min.
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