CN115117151B - IGBT chip with composite cellular structure and manufacturing method thereof - Google Patents
IGBT chip with composite cellular structure and manufacturing method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 claims abstract description 40
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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Abstract
The invention provides an IGBT chip with a composite cellular structure and a manufacturing method thereof. According to the invention, two kinds of cells with different threshold voltages are designed in the cell area of the chip, in the process of turning off the chip, the channel of the high-threshold cell is firstly closed, but the channel of the low-threshold cell is still kept open for a period of time, so that the electron current component is reduced in a step manner, the partial current ratio of the space charge area is born, the increase of hole current is effectively inhibited, the increase of the effective doping concentration Neff of the area is relieved, and the dynamic avalanche breakdown voltage of the chip is improved.
Description
Technical Field
The invention relates to the technical field of IGBT chip preparation, in particular to an IGBT chip with a composite cellular structure and a manufacturing method thereof.
Background
The IGBT is a high-power semiconductor discrete device, combines the advantages of high switching frequency and easy control of an MOS device and the high-current processing capacity of a BJT device, and has wide application in the fields of industrial frequency conversion, consumer electronics, rail transit, new energy, aerospace, and the like.
In the IGBT chip of the trench gate, under the blocking state, a PN junction composed of a front P well and an N drift region bears bus voltage, the bus voltage under the normal condition is only 50% -70% of the nominal voltage of the IGBT chip, namely, the PN junction can completely bear a peak electric field generated by the bus voltage, and the PN junction is rarely subjected to avalanche breakdown under the static blocking state.
However, in the dynamic process of turning on the IGBT chip to the off state, carriers in the drift region of the device near the front cathode side are swept out first, the current component of the carriers in the region begins to change, and since the channel of the IGBT device is turned off first in the off process, electron current is no longer injected into the drift region from the cathode side, but due to the presence of load inductance in an external circuit, the current cannot suddenly change, so that the hole current component rises sharply, and further the effective doping concentration Neff = ND + p-n in the region is greater than the fixed charge density ND, and the slope of the electric field rises, so that the electric field spike at the PN junction is raised, and the dynamic avalanche voltage that the device can bear is much lower than the static avalanche voltage. When the turn-on voltages of all trench cells in the active region are consistent, the channel is almost simultaneously closed, no electron current is injected any more in the process of expanding the space charge region, and almost all the region is hole current, so that the risk of dynamic avalanche is increased.
Disclosure of Invention
In view of this, the invention provides a method for manufacturing an IGBT chip with a composite cell structure, which solves the technical problem in the prior art that when the turn-on voltages of all trench cells in an active region of an IGBT chip with a trench gate are consistent, the risk of occurrence of dynamic avalanche is easily increased.
In order to achieve the above object, the present invention provides an IGBT chip with a composite cell structure, including a cell region and a terminal region; the cell region comprises a monocrystalline silicon substrate, a gate oxide layer, a polycrystalline silicon gate region, a first P well region, a second P well region, an N-type doped region, a P + contact region, an insulating dielectric layer, a front metal layer, a passivation layer, a back buffer layer, a back anode region and a back metal layer, wherein the first P well region is located in a first region of the monocrystalline silicon substrate, the second P well region is located in a second region of the monocrystalline silicon substrate, the depth of the first P well region is larger than that of the second P well region, a first part of the polycrystalline silicon gate region is located in the first P well region, and a second part of the crystalline silicon gate region is located in the second P well region.
In order to achieve the above object, the present invention further provides a method for manufacturing an IGBT chip with a composite cell structure, including the steps of:
s1, growing a field oxide layer and doping a field limiting ring region of a terminal region;
s2, selectively corroding the field oxide layer in the cell area, photoetching, opening a part of area graph of the cell area, injecting P-type ions into the cell area for the first time, and pushing impurities after removing photoresist;
s3, injecting P-type ions into the cell area for the second time to form a first P well region and a second P well region, wherein the depth of the first P well region is larger than that of the second P well region;
s4, growing a gate oxide layer and filling polycrystalline silicon;
s5, doping an N-type source region;
s6, depositing an isolation medium layer and etching a contact hole;
s7, forming a front metallization layer and a passivation layer;
and S8, thinning and metalizing the back of the wafer.
Preferably, the step S1 specifically includes:
selecting an N-type monocrystalline silicon substrate, and growing a field oxide layer by adopting a wet oxygen process;
selectively corroding the field oxide layer in the field limiting ring region of the terminal region, injecting B + ions, and pushing impurities after photoresist removal.
Preferably, in the step S2;
the first P-type ion implantation in the cell region is B + ion with implantation dosage of 1E13-5E14 and implantation energy of 120-300keV;
the temperature of impurity propulsion after photoresist stripping is 1050-1150 ℃ and the time is 200-350min.
Preferably, the step S3 specifically includes:
injecting P-type ions into the cellular region for the second time, wherein the injection dosage is 5E12-1E14, and the injection energy is 80-140keV;
the impurities are pushed in at 900-1150 deg.C for 90-150min.
Preferably, the step S4 specifically includes:
depositing and growing a silicon dioxide etching hard mask layer based on a PECVD (plasma enhanced chemical vapor deposition) process, and etching a cell area groove;
growing a sacrificial oxide layer, and removing the sacrificial oxide layer;
and growing a gate oxide layer, performing polysilicon filling growth based on an LPCVD (low pressure chemical vapor deposition) process, etching the polysilicon layer, and forming a gate electrode and a Busbar wire.
Preferably, the step S5 specifically includes:
turning the wafer, removing polysilicon on the back, turning the wafer and cleaning;
etching the oxide layer in the cellular area, and reducing the thickness of the oxide layer;
and (3) source region N-type ion implantation: injecting P + ions for the first time, injecting As + ions for the second time, and annealing in a furnace tube after photoresist removal.
Preferably, the step S6 specifically includes:
depositing an isolation dielectric layer to form a USG + BPSG double-layer structure, and etching a contact hole;
and (3) injecting a contact hole region: injecting BF2 ions for the first time, injecting B + ions for the second time, and performing furnace tube annealing after photoresist stripping.
Preferably, the step S7 specifically includes:
depositing a metal layer on the front surface, carrying out dry etching patterning, forming a passivation layer by using PI glue Coating, and carrying out photoetching patterning.
Preferably, the step S8 specifically includes:
grinding the back of the wafer, removing silicon oxide, reducing the thickness, and injecting P + ions into the back to form a buffer layer;
injecting B + ions into the anode on the back, annealing the furnace tube to activate impurities, and depositing a metal layer on the back.
The beneficial effects of adopting the above embodiment are:
the channel length of the first P well region unit cell is larger than that of the second P well region, so that the threshold voltage of the first P well region unit cell is higher than that of the second P well region, the channel of the first P well region unit cell is firstly closed in the process of turning off a chip, but the channel of the second P well region unit cell is still kept on for a period of time, so that the electronic current component is in a step-shaped reduction, partial current proportion of a space charge region is born, the increase of hole current is effectively inhibited, the increase of effective doping concentration Neff of the region is relieved, and the dynamic avalanche breakdown voltage of the chip is improved.
Furthermore, the invention designs two kinds of unit cells with different threshold voltages in the unit cell area of the chip, in the process of turning off the chip, the channel of the high-threshold unit cell is firstly closed, but the channel of the low-threshold unit cell is still kept to be opened for a period of time, so that the electron current component is reduced in a step shape, the partial current ratio of the space charge area is born, the increase of the hole current is effectively inhibited, the increase of the effective doping concentration Neff of the area is relieved, and the dynamic avalanche breakdown voltage of the chip is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural change diagram of an embodiment of an IGBT chip after step S1 is executed in the method for manufacturing an IGBT chip with a composite cell structure according to the present invention;
fig. 2 is a schematic diagram illustrating a structural change of an embodiment of the IGBT chip after step S2 is performed in the method for manufacturing an IGBT chip with a composite cell structure according to the present invention;
fig. 3 is a schematic structural change diagram of an embodiment of an IGBT chip after step S3 is executed in the method for manufacturing an IGBT chip with a composite cell structure according to the present invention;
fig. 4 is a schematic diagram illustrating a structural change of an embodiment of the IGBT chip after step S4 is performed in the method for manufacturing an IGBT chip with a composite cell structure according to the present invention;
fig. 5 is a schematic diagram illustrating a structural change of an embodiment of the IGBT chip after step S5 is performed in the method for manufacturing an IGBT chip with a composite cell structure according to the present invention;
fig. 6 is a schematic diagram illustrating a structural change of an embodiment of the IGBT chip after step S6 is performed in the method for manufacturing an IGBT chip with a composite cell structure according to the present invention;
fig. 7 is a schematic structural change diagram of an embodiment of an IGBT chip after step S7 is executed in the method for manufacturing an IGBT chip with a composite cell structure according to the present invention;
fig. 8 is a schematic diagram illustrating a structural change of an embodiment of the IGBT chip after step S8 is performed in the method for manufacturing an IGBT chip with a composite cell structure according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It should be apparent that the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Before describing embodiments of the present invention, a brief description of related terms or general knowledge is provided:
the IGBT structure: the IGBT generally includes a cell region and a terminal region, and the cell region structures are all structures whose central axes are symmetric, so that each structure is not labeled in the drawings in this specification, and if not labeled, it is determined according to the symmetric labeling.
For an accurate description of the reference numerals, they are first presented in table 1.
Table 1: reference numeral correspondence table
The invention provides an IGBT chip with a composite cellular structure and a manufacturing method thereof.A cell area of the chip is designed by two cells with different threshold voltages, and in the process of turning off the chip, a channel of a high-threshold-value cell is firstly turned off, but a channel of a low-threshold-value cell is still turned on for a period of time, so that the electron current component is reduced in a step manner, the proportion of partial current in a space charge area is born, the increase of hole current is effectively inhibited, the increase of effective doping concentration Neff in the area is relieved, and the dynamic avalanche breakdown voltage of the chip is improved.
In an embodiment of the present invention, referring to fig. 1 to 8, the present invention provides a method for manufacturing an IGBT chip having a composite cell structure, including the following steps:
s1, growing a field oxide layer and doping a field limiting ring region of a terminal region; referring to fig. 1, the step S1 specifically includes:
selecting an N-type FZ monocrystalline silicon substrate 101/201, wherein the surface of a monocrystalline silicon wafer is a (100) crystal face, the resistivity is 30-90 omega-cm, and growing a field oxide layer by adopting a wet oxygen process to form a field oxide layer 102/202, wherein the temperature of the wet oxygen process is 800-1050 ℃, and the thickness of the oxide layer is 1-3 mu m;
selectively etching the field oxide layer in the field limiting ring region of the terminal region, implanting B + ions to form a P-type doped region 203, wherein the implantation dosage is 8E13-5E14, the implantation energy is 80-140keV, and the impurity is driven after photoresist is removed at the temperature of 1000-1200 ℃ for 300-600min.
S2, doping the P well region for the first time; referring to fig. 2, the step S2 specifically includes:
selectively corroding the field oxide layer in the cell area, photoetching, and opening partial area patterns in the cell area;
p-type doping regions 103 are formed by first P-well region P-type ion implantation (B + ions) in the cellular region, the implantation dosage is 1E13-5E14, and the implantation energy is 120-300keV;
after removing the photoresist, the impurities are pushed forward at 1050-1150 ℃ for 200-350min.
S3, doping the P well region for the second time; referring to fig. 3, the step S3 specifically includes:
performing second P-type ion implantation (B + ion) in the P-well region in the cellular region, wherein the implantation dose of the B + ion is 5E12-1E14, and the implantation energy is 80-140keV;
and after impurity propulsion, forming a first P well region 1031 and a second P well region 1032, wherein the depth of the first P well region 1031 is greater than that of the second P well region 1032, the impurity propulsion temperature is 900-1150 ℃, and the time is 90-150min.
It should be noted that, steps S2 to S3 are one of the core innovations of the present invention, and a first P-well region and a second P-well region with different depths are formed through two P-well region P-type ion implantations, and the channel length of the first P-well region cellular cell is greater than that of the second P-well region, so that the threshold voltage thereof is also higher than that of the second P-well region, and in the process of turning off the chip, the channel of the first P-well region cellular cell is turned off first, but the channel of the second P-well region cellular cell still remains on for a while, so that the electron current component is reduced in a stepwise manner, and bears a part of the current occupancy of the space charge region, thereby effectively inhibiting the increase of the hole current, alleviating the increase of the effective doping concentration Neff of the region, and thus increasing the dynamic avalanche breakdown voltage of the chip.
S4, growing a gate oxide layer and filling polycrystalline silicon; referring to fig. 4, the step S4 specifically includes:
depositing and growing a silicon dioxide etching hard mask layer based on a PECVD process, wherein the thickness is 5000-10000A, and the depth is 4-7 mu m;
growing a sacrificial oxide layer with the thickness of 800-1200A, and removing the sacrificial oxide layer;
and growing a gate oxide layer with the thickness of 1000-1200A, performing polysilicon filling growth based on an LPCVD process with the thickness of 8000-12000A, and etching the polysilicon to form a gate electrode (namely the polysilicon gate region 104/204) and a Busbar wiring.
S5, doping an N-type source region; referring to fig. 5, the step S5 specifically includes:
turning the wafer, removing polysilicon on the back, turning the wafer and cleaning;
etching the oxide layer in the cellular region, and reducing the thickness of the oxide layer to 100-500A;
and (3) forming an N-type doped region 105 by source region N-type ion implantation: injecting P + ions for the first time, wherein the injection dosage is 1E15-8E15, and the injection energy is 40-80keV; implanting As + ions for the second time, wherein the implantation dose is 1E15-8E15, the implantation energy is 40-100keV, and the furnace tube annealing (simultaneously carrying out polysilicon oxidation) is carried out after photoresist is removed, and the temperature is 800-1000 ℃ and the time is 30-60min.
S6, depositing an isolation medium layer and etching a contact hole; referring to fig. 6, the step S6 specifically includes:
depositing an isolation medium layer 106/206 to form a USG + BPSG double-layer structure with the total thickness of 9000-12000A, and etching a contact hole, wherein the over-etching depth of the lower layer Si is 0.2-0.5 mu m;
and (3) injecting a contact hole region: implanting BF2 ions for the first time, wherein the implantation dose is 5E14-8E15, and the implantation energy is 20-80keV; implanting B + ions for the second time at the implantation dose of 1E14-5E15 and the implantation energy of 40-100keV, and performing furnace tube annealing after photoresist removal at the temperature of 700-1000 ℃ for 30-60min.
S7, forming a front metallization layer and a passivation layer; referring to fig. 7, the step S7 specifically includes:
depositing a metal layer 107/207 on the front surface with the thickness of 4-8 μm, performing dry etching patterning, forming a passivation layer 108/208 by using PI glue Coating, and performing photoetching patterning with the thickness of 8-12 μm.
S8, thinning and metalizing the back of the wafer; referring to fig. 8, the step S8 specifically includes:
grinding the back of the wafer, removing silicon oxide, reducing the thickness to 60-150 μm, implanting P + ions to the back to form a buffer layer, wherein the implantation dose is 2E11-1E13, and the implantation energy is 200-900keV;
injecting B + ions into the anode on the back side, wherein the injection dosage is 1E12-8E13, the injection energy is 20-50keV, annealing in a furnace tube to activate impurities at the temperature of 300-500 ℃ for 20-80min, and depositing a metal layer on the back side with the thickness of 1-2 mu m.
It should be noted that, in fig. 8, the two P well regions with different depths formed through steps S2 and S3 are a first P well region 1031 and a second P well region 1032, respectively, and it can be seen that the first P well region 1031 is located in a first region of the single-crystal silicon substrate 101, the second P well region 1032 is located in a second region of the single-crystal silicon substrate 101, the depth of the first P well region 1031 is greater than that of the second P well region 1032, the channel length of the first P well region 1031 is greater than that of the second P well region 1032, a first portion (i.e., close to the first region) of the polysilicon gate region is located in the first P well region 1031, and a second portion (i.e., close to the second region) of the polysilicon gate region is located in the second P well region 1032.
The IGBT chip with the composite cellular structure provided by the invention is obtained through the preparation process of the steps S1-S8.
In an embodiment of the present invention, the IGBT chip having a composite cell structure provided in the above embodiments includes a cell region and a terminal region.
The cell region comprises a monocrystalline silicon substrate 101, a gate oxide layer 102, a polycrystalline silicon gate region 104, a first P well region 1031, a second P well region 1032, an N-type doped region 105, a P + contact region (not shown), an isolation dielectric layer 106, a front metal layer 107, a passivation layer 108, a back buffer layer (not shown), a back anode region and a back metal layer 110, wherein the first P well region 1031 is located in a first region of the monocrystalline silicon substrate 101, the second P well region 1032 is located in a second region of the monocrystalline silicon substrate 101, the depth of the first P well region 1031 is larger than that of the second P well region 1032, the channel length of the first P well region 1031 is larger than that of the second P well region 1032, a first part (close to the first region) of the polycrystalline silicon gate region is located in the first P well region 1031, and a second part (close to the second region) of the polycrystalline silicon gate region is located in the second P well region 1032. Specifically, the length of the channel of the first P-well cellular is greater than that of the second P-well cellular, so that the threshold voltage of the first P-well cellular is also greater than that of the second P-well cellular, and in the process of turning off the chip, the channel of the first P-well cellular is firstly closed, but the channel of the second P-well cellular is still kept on for a period of time, so that the electron current component is reduced in a step manner, the proportion of partial current in the space charge region is born, the increase of hole current is effectively inhibited, the increase of the effective doping concentration Neff in the region is alleviated, and the dynamic avalanche breakdown voltage of the chip is increased.
The basic structure of the terminal area comprises a monocrystalline silicon substrate 201, a terminal P-type main junction and a field limiting ring, a Busbar wiring (Poly) of a groove-type polycrystalline silicon grid 203, a USG/BPSG dielectric layer 206, a grid metal 207, a source metal, a PI glue passivation layer 208, a back Buffer layer (N-doping), a back anode, a back metal layer 210 and the like.
In summary, the length of the channel of the first P-well cellular is greater than that of the second P-well, so that the threshold voltage is higher than that of the second P-well, and in the process of turning off the chip, the channel of the first P-well cellular is firstly turned off, but the channel of the second P-well cellular is still turned on for a while, so that the electron current component is reduced in a step manner, and bears the proportion of partial current in the space charge region, thereby effectively inhibiting the increase of the hole current, alleviating the increase of the effective doping concentration Neff in the region, and further improving the dynamic avalanche breakdown voltage of the chip.
Furthermore, the invention designs two kinds of unit cells with different threshold voltages in the unit cell area of the chip, in the process of turning off the chip, the channel of the high-threshold unit cell is firstly closed, but the channel of the low-threshold unit cell is still kept to be opened for a period of time, so that the electron current component is reduced in a step shape, the partial current ratio of the space charge area is born, the increase of the hole current is effectively inhibited, the increase of the effective doping concentration Neff of the area is relieved, and the dynamic avalanche breakdown voltage of the chip is improved.
The method for manufacturing the IGBT chip with the composite cell structure provided by the present invention is described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (7)
1. The manufacturing method of the IGBT chip with the composite cellular structure is characterized in that the IGBT chip with the composite cellular structure comprises a cellular area and a terminal area; the cell region comprises a monocrystalline silicon substrate, a gate oxide layer, a polycrystalline silicon gate region, a first P well region, a second P well region, an N-type doped region, a P + contact region, an insulating dielectric layer, a front metal layer, a passivation layer, a back buffer layer, a back anode region and a back metal layer, wherein the first P well region is positioned in a first region of the monocrystalline silicon substrate, the second P well region is positioned in a second region of the monocrystalline silicon substrate, the depth of the first P well region is greater than that of the second P well region, the channel length of the first P well region is greater than that of the second P well region, a first part of the polycrystalline silicon gate region is positioned in the first P well region, and a second part of the polycrystalline silicon gate region is positioned in the second P well region;
the manufacturing method comprises the following steps:
s1, growing a field oxide layer and doping a field limiting ring region of a terminal region;
s2, selectively corroding the field oxide layer in the cell area, photoetching, opening a part of area patterns in the cell area, injecting P-type ions into the cell area for the first time, and pushing impurities after removing photoresist;
s3, injecting P-type ions into the cellular region for the second time to form a first P well region and a second P well region, wherein the depth of the first P well region is larger than that of the second P well region, and the channel length of the cellular region of the first P well region is larger than that of the second P well region;
s4, growing a gate oxide layer and filling polycrystalline silicon;
s5, doping an N-type source region;
s6, depositing an isolation medium layer and etching a contact hole;
s7, forming a front metallization layer and a passivation layer;
s8, thinning and metalizing the back of the wafer;
wherein, in the step S2;
the ions of the first injection P-type ions in the cellular area are B + ions, the injection dosage is 1E13-5E14, and the injection energy is 120-300keV;
the temperature of impurity propulsion after photoresist removal is 1050-1150 ℃ and the time is 200-350min;
the step S3 specifically includes:
injecting P-type ions into the cellular region for the second time, wherein the injection dosage is 5E12-1E14, and the injection energy is 80-140keV;
pushing impurities at 900-1150 deg.C for 90-150min.
2. The method for manufacturing the IGBT chip with the composite cell structure according to claim 1, wherein the step S1 specifically includes:
selecting an N-type monocrystalline silicon substrate, and growing a field oxide layer by adopting a wet oxygen process;
selectively corroding the field oxide layer in the field limiting ring area of the terminal area, injecting B + ions, and pushing impurities after photoresist removal.
3. The method for manufacturing the IGBT chip with the composite cell structure according to claim 1, wherein the step S4 specifically includes:
depositing and growing a silicon dioxide etching hard mask layer based on a PECVD process, and etching a groove in a cellular area;
growing a sacrificial oxide layer, and removing the sacrificial oxide layer;
and growing a gate oxide layer, performing polysilicon filling growth based on an LPCVD (low pressure chemical vapor deposition) process, etching the polysilicon layer, and forming a gate electrode and a Busbar wire.
4. The method for manufacturing the IGBT chip with the composite cell structure according to claim 1, wherein the step S5 specifically includes:
turning the wafer, removing polysilicon on the back, turning the wafer again, and cleaning;
etching the oxide layer in the cellular area, and reducing the thickness of the oxide layer;
and (3) source region N-type ion implantation: injecting P + ions for the first time, injecting As + ions for the second time, and annealing in a furnace tube after photoresist removal.
5. The method for manufacturing the IGBT chip with the composite cell structure according to claim 1, wherein the step S6 specifically includes:
depositing an isolation dielectric layer to form a USG + BPSG double-layer structure, and etching a contact hole;
and (3) injecting a contact hole region: injecting BF2 ions for the first time, injecting B + ions for the second time, and performing furnace tube annealing after photoresist removal.
6. The method for manufacturing the IGBT chip with the composite cell structure according to claim 1, wherein the step S7 specifically includes:
depositing a metal layer on the front surface, carrying out dry etching patterning, forming a passivation layer by using PI glue Coating, and carrying out photoetching patterning.
7. The method for manufacturing the IGBT chip with the composite cell structure according to claim 1, wherein the step S8 specifically includes:
grinding the back of the wafer, removing silicon oxide, reducing the thickness, and injecting P + ions into the back to form a buffer layer;
injecting B + ions into the anode on the back, annealing the furnace tube to activate impurities, and depositing a metal layer on the back.
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