CN115425079A - Groove type double-layer gate power device and manufacturing method thereof - Google Patents
Groove type double-layer gate power device and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Abstract
The invention discloses a groove type double-layer gate power device which comprises an N + substrate, an N-epitaxial layer, a P well and a dielectric layer, wherein the N + substrate is provided with a plurality of grooves; a source region groove and a terminal region groove are arranged between the N-epitaxial layer and the dielectric layer; a trench field oxide layer is arranged outside the trench of the source region, an N-type shielding gate, an isolation oxide layer, a gate oxide layer and a control gate are arranged inside the trench of the source region, an N + source region is arranged between a P well and a dielectric layer, and a contact hole of the source region is arranged between the trenches of the source region and is connected with a metal layer on the front surface of the source region through the dielectric layer; and a terminal region trench field oxide layer is arranged outside the terminal region trench, terminal region trench polysilicon is arranged in the terminal region trench and is wrapped by the terminal region trench field oxide layer and the dielectric layer, and an avalanche tolerance enhancement structure consisting of the last terminal region trench ring of the terminal region and an auxiliary structure thereof is arranged in front of the terminal region trench cut-off ring. The invention can increase the forward conduction current density, reduce the conduction resistance, increase the avalanche resistance EAS and improve the product performance under the condition of ensuring that the area and the cost of a chip are not increased.
Description
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a groove type double-layer gate power device and a manufacturing method thereof.
Background
Among power devices, a trench type double-layer gate power MOS (MOSFET field effect transistor) device has characteristics of high breakdown voltage, low on-resistance, fast switching speed, and high conversion efficiency. In general, the bottom polysilicon electrode in the trench is used as a shielding electrode to be shorted with the source electrode, and the upper polysilicon electrode is used as a gate electrode. The main research direction of the trench-type double-layer gate power MOS is to continuously reduce power consumption (including conduction loss and switching loss) and improve robustness of dynamic performance of the device.
The method for increasing the avalanche tolerance of the conventional groove type double-layer gate power MOS comprises the following steps: some areas (i.e. dummy structures) with only P-well regions and no N + source regions are arranged in the source region to provide a path for avalanche hole current, so as to reduce the magnitude and current density of cellular avalanche hole current. However, the problem of the method for increasing the avalanche tolerance of the existing trench type double-layer gate power MOS is that: 1) In the source region of the prior art, the avalanche tolerance enhancement structure only has a P well region and does not have an N + source region, namely, a dummy structure, and because the avalanche tolerance enhancement structure in the source region does not have an N + source region and cannot generate forward current, the existence of the structures can increase the chip area and improve the chip cost. 2) In the existing trench type double-layer gate power MOS, a source electrode is possibly connected with an anode electrode (the difference between a gate voltage and a source electrode voltage is larger than a threshold voltage) in a practical application circuit, so that the difference VDS between drain and source voltages is reduced, an electric field in an electric field of a reverse bias PN junction PWELL-N-junction is reduced, the extraction effect of an avalanche tolerance enhancement structure on avalanche hole current is weakened, the extraction speed of the avalanche hole current is weakened, and the avalanche tolerance enhancement structure does not fully play a role in improving the avalanche tolerance. 3) In a practical circuit, the source of the trench-type double-layer gate power MOS is connected with the positive electrode, so that the difference between the gate voltage and the source voltage is larger than the threshold voltage. 4) When the existing trench type double-layer gate power MOS device is turned off, the extraction time of avalanche hole current caused by the non-clamping inductive switch is long, so that the heat generated by the avalanche hole current is large when the device is turned off, and large temperature rise can be caused.
It is to be noted that the information disclosed in the above background section is only for understanding the background of the present application and thus may include information that does not constitute prior art known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to solve the technical problems of reducing the on-resistance, increasing the avalanche capability (EAS) and improving the product performance under the condition of ensuring that the chip area and the chip cost are not increased, and provides a trench type double-layer gate power device and a manufacturing method thereof.
The technical problem of the invention is solved by the following technical scheme:
the invention discloses a trench type double-layer gate power device which sequentially comprises an N + substrate, an N-epitaxial layer, a P well and a dielectric layer from bottom to top; a plurality of adjacent source region grooves and a plurality of adjacent terminal region grooves are respectively arranged between the N-epitaxial layer and the dielectric layer; a trench field oxide layer is arranged on the outer side of the trench of the source region, an N-type shielding gate, an isolation oxide layer, a gate oxide layer and a control gate are sequentially arranged in the trench from bottom to top, an N + source region is arranged between the P well and the dielectric layer, and a contact hole of the source region is arranged between the trenches of the source region and is connected with a metal layer on the front surface of the source region through the dielectric layer; the outer side of the terminal region groove is provided with a terminal region groove field oxide layer, terminal region groove polycrystalline silicon is arranged in the terminal region groove and is wrapped by the terminal region groove field oxide layer and a dielectric layer, and an avalanche tolerance enhancement structure consisting of the last terminal region groove ring of the terminal region and an accessory structure thereof is arranged in front of the terminal region groove stopping ring.
In some embodiments, the avalanche resistance enhancement structure includes the dielectric layer, the avalanche resistance enhancement structure metal layer, the avalanche resistance enhancement structure body region, the body region contact hole and the avalanche resistance enhancement structure polysilicon contact hole, the avalanche resistance enhancement structure trench field oxide layer and the avalanche resistance enhancement structure polysilicon.
Further, the width of the contact hole of the avalanche capability enhancement structure body region is larger than that of the contact hole of the source region.
Furthermore, the potential of the avalanche resistance enhanced structure polysilicon and the front metal layer of the avalanche resistance enhanced structure is zero.
In some embodiments, the front metal layer of the avalanche capability enhancement structure is separated from the source region front metal layer, and the potential of the front metal layer of the avalanche capability enhancement structure is set to be zero volt.
In some embodiments, the above-mentioned regions where the N + source regions are all present in the source region pwell, i.e., the regions without the N + source regions are not present in the source region pwell.
In some embodiments, the N + substrate is provided with a back metal on the back side.
The invention also discloses a manufacturing method of the groove type double-layer gate power device, which comprises the following steps:
s1, forming an N-epitaxial layer on an N + substrate;
s2, performing groove photoetching and etching on the N-epitaxial layer to synchronously form a source region groove, a terminal region groove and an avalanche tolerance enhancement structure groove;
s3, synchronously growing and forming a trench field oxide layer and a terminal region avalanche tolerance enhancement structure trench field oxide layer on the side wall of the trench;
s4, depositing polycrystalline silicon, performing polycrystalline phosphorus diffusion, photoetching and etching, and synchronously forming a source region N-type shielding gate, terminal region groove polycrystalline silicon and avalanche tolerance enhancement structure polycrystalline silicon;
s5, depositing a high-density oxide film by using a chemical vapor deposition method, and then etching the oxide film back to a specified depth to keep enough thickness of the isolation oxide film to form an isolation oxide layer, wherein no oxide layer exists above the isolation oxide layer;
s6, forming a gate oxide layer above the isolation oxide layer in the source region trench by using a thermal oxidation method;
s7, depositing N-type polycrystalline silicon, carrying out chemical mechanical polishing until the N-type polycrystalline silicon is flush with the surface of the chip, and removing the polycrystalline silicon and the oxide layer on the surface of the chip to form a control gate;
s8, carrying out boron injection and diffusion to form a P well, and then carrying out N + photoetching, arsenic injection and diffusion to form an N + source region;
s9, forming a dielectric layer;
s10, forming a contact hole by contact hole photoetching and etching, performing contact hole P-type high doping injection, and synchronously forming a source region contact hole, an avalanche resistance enhanced structure body region contact hole and avalanche resistance enhanced structure polycrystalline silicon;
s11, front metal sputtering, photoetching and etching are carried out, and a source region front metal layer, a terminal region front metal layer and an avalanche tolerance enhancement structure front metal layer are synchronously formed;
s12, depositing, photoetching and etching a passivation layer to form a passivation layer lead window;
and S13, evaporating the metal to form back metal.
In some embodiments, in step S5, the termination region trench polysilicon and the avalanche capability enhancement structure polysilicon are both integral.
In some embodiments, in step S9, the dielectric layer has a double-layer structure of a non-phosphorus-doped silicate glass layer and a phosphorus-doped silicate glass layer.
Compared with the prior art, the invention has the advantages that:
the trench type double-layer gate power device has the equivalent effect that an avalanche tolerance enhancement structure of a source region in a traditional structure is moved to a terminal. Because the total length of the terminal is not increased, the invention can save the chip area occupied by the avalanche capability enhancement structure of the traditional structure, namely under the condition that the chip areas are the same, the invention can increase the forward conducting current density, reduce the on-resistance and improve the product performance. Under the same chip area condition, the invention increases the current density of the conducting current because the source region does not have the region without the N + source region, thereby reducing the conducting resistance, increasing the avalanche resistance EAS and further improving the performance of the product.
Drawings
FIG. 1 is a top view of a prior art trench-type double-layer gate power device;
FIG. 2 is a schematic cross-sectional view of a trench-type double-layer gate power device along the A1A2 direction in the prior art;
fig. 3 is a top view of a trench-type double-layer gate power device in an embodiment of the invention;
fig. 4 is a schematic cross-sectional structure view of the trench-type double-layer gate power device along the direction A1A2 in the embodiment of the present invention;
fig. 5 is a schematic cross-sectional structure view of a trench-type double-layer gate power device along the direction B1B2 in the embodiment of the present invention;
fig. 6 is a schematic diagram illustrating the flow direction of avalanche hole current of the trench-type double-layer gate power device in the embodiment of the present invention;
fig. 7 is a flow chart of a manufacturing process of the trench-type double-layer gate power device according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It should be further noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings, not all of them.
Referring to fig. 1, a trench-type double-layer gate power device in the prior art includes the following parts: the device is along the front metal 13A, the gate metal 13B, and the source metal layer 13C, and the trench structure is an array of trench structures extending along the Y-axis direction and arranged along the X-axis direction, which is not shown in the figure.
Referring to fig. 2, a schematic cross-sectional structure of the prior art trench type double-layer gate power device along a direction A1A2, where a dashed box is an avalanche tolerance enhancement structure, the prior art trench type double-layer gate power device further includes the following parts: the field-effect transistor comprises an N + substrate 1, an N-epitaxial layer 2, a source region groove field oxide layer 3, a source region isolation oxide layer 4 between a source region N-type shielding gate 6 and a source region control gate 11, a source region gate oxide layer 5, a source region N-type shielding gate 6, a source region P well 7, a source region N + source region 8, a source region dielectric layer 9, back metal 10, a source region control gate 11, a source region groove 12, device edge front metal 13A, a source region front metal layer 13C, terminal region groove polycrystalline silicon 14, a source region contact hole 15 and source metal in the contact hole. The left side of the dashed line indicates the source region and the right side of the dashed line indicates the termination region.
The structure of the trench type double-layer gate power device in the prior art is characterized in that: in the source region, some regions with only P well 7 region and no N + source region 8, i.e. dummy structure, are provided to provide a path for avalanche hole current, so as to reduce the magnitude and current density of avalanche hole current of the cell. Two source region trenches 12 in a dotted frame in the drawing are avalanche resistance enhancement structures.
The existing method for increasing the avalanche tolerance of the groove type double-layer gate power MOS has the following problems: 1) In the source region of the prior art, the avalanche tolerance enhancement structure only has a P well region and does not have an N + source region, namely a dummy structure, and because the avalanche tolerance enhancement structure in the source region does not have the N + source region and cannot generate forward current, the chip area can be increased due to the existence of the structures, and the chip cost is increased. 2) In the existing trench type double-layer gate power MOS, a source electrode is possibly connected with an anode electrode (the difference between a gate voltage and a source electrode voltage is larger than a threshold voltage) in a practical application circuit, so that the difference VDS between drain and source voltages is reduced, an electric field in an electric field of a reverse bias PN junction PWELL-N-junction is reduced, the extraction effect of an avalanche tolerance enhancement structure on avalanche hole current is weakened, the extraction speed of the avalanche hole current is weakened, and the avalanche tolerance enhancement structure does not fully play a role in improving the avalanche tolerance. 3) Because the source electrode of the groove type double-layer grid power MOS is possibly connected with the anode electrode in a practical application circuit (the difference between the grid voltage and the source electrode voltage is larger than the threshold voltage), the groove type double-layer grid power device structure in the embodiment of the invention increases the difference VDS between the drain voltage and the source voltage by placing the electric potential of the front metal of the avalanche tolerance enhancement structure at zero volt, so that the avalanche tolerance enhancement structure further increases the avalanche tolerance EAS compared with the existing structure. 4) When the existing trench type double-layer gate power MOS device is turned off, the extraction time of avalanche hole current caused by the non-clamping inductive switch is long, so that the heat generated by the avalanche hole current is large when the device is turned off, and large temperature rise can be caused.
Referring to fig. 3, the trench type double-layer gate power device of the embodiment includes the following parts: the device edge front metal 13A, the gate region metal 13B, the source region front metal layer 13C, the avalanche resistance enhancement structure front metal layer 13D, and the avalanche resistance enhancement structure front metal layer 13D are separated from the source region front metal layer 13C and are not connected into a whole. The trench structure is an array of trench structures extending in the Y-axis direction and arranged in the X-axis direction, which are not shown in the figure.
Referring to fig. 4, the trench-type double-layer gate power device of the embodiment further includes the following parts: the field-effect transistor comprises an N + substrate 1, an N-epitaxial layer 2, a source region groove field oxide layer 3, a source region isolation oxide layer 4 between a source region N-type shielding gate 6 and a source region control gate 11, a source region gate oxide layer 5, a source region N-type shielding gate 6, a source region P well 7, a source region N + source region 8, a source region dielectric layer 9, back metal 10, a source region control gate 11, a source region groove 12, a terminal region groove 12A, device edge front metal 13A, a source region front metal layer 13C, terminal region groove polycrystalline silicon 14, a source region contact hole 15 and source region contact holes 15, wherein source metal is arranged in the source region contact holes 15. The left side of the dashed line represents the source region and the right side of the dashed line represents the termination region.
The difference between the shielded gate power MOSFET in the embodiment of the present invention and the cross-sectional structure schematic diagram of the shielded gate power MOSFET in the prior art along the A1A2 direction is that: the source region of the shielded gate power MOSFET in the embodiment of the invention has no avalanche tolerance enhancement structure, namely, no region without an N + source region exists in the source region P trap.
Referring to fig. 5, the cross-sectional structure of the trench-type double-layer gate power device of the embodiment along the B1B2 direction further includes the following parts: the avalanche resistance enhancement structure comprises a front metal layer 13D of the avalanche resistance enhancement structure, terminal region groove polycrystalline silicon 14, a source region contact hole 15, and source metal in the source region contact hole 15. In the figure, a dashed line frame represents an avalanche capability enhancement structure of the trench type double-layer gate power device in the embodiment, which is composed of a terminal last trench ring and an auxiliary structure thereof and is positioned in front of a trench stop ring. The avalanche tolerance enhancement structure includes the following portions: the avalanche resistance enhanced structure comprises an avalanche resistance enhanced structure groove field oxide layer 3A, an avalanche resistance enhanced structure dielectric layer 9A, an avalanche resistance enhanced structure groove 12B, an avalanche resistance enhanced structure front metal layer 13D, avalanche resistance enhanced structure polycrystalline silicon 14A, an avalanche resistance enhanced structure body area 7A, an avalanche resistance enhanced structure body area contact hole 15A and an avalanche resistance enhanced structure polycrystalline silicon contact hole 15B. The avalanche tolerance enhancement structure is characterized in that: the width of the contact hole 15A of the avalanche capability enhancement structure body region is larger than that of the contact hole 15 of the source region. The left side of the dashed line indicates the source region and the right side of the dashed line indicates the termination region. The terminal region trench field oxide layer 3A is arranged on the outer side of the terminal region trench 12A, and the avalanche tolerance enhancement structure polysilicon 14A is arranged in the terminal region trench 12A and is wrapped by the terminal region trench field oxide layer 3A and the avalanche tolerance enhancement structure dielectric layer 9A. The avalanche resistance enhanced structure body region contact hole 15A and the avalanche resistance enhanced structure polycrystalline silicon contact hole 15B are connected with the avalanche resistance enhanced structure front metal layer 13D through the avalanche resistance enhanced structure dielectric layer 9A, wherein the avalanche resistance enhanced structure polycrystalline silicon 14A is connected with the avalanche resistance enhanced structure front metal layer 13D.
The hole current flowing direction of the trench-type double-layer gate power device of the embodiment is shown in fig. 6, where a is the total avalanche hole current of the device, A1 is the avalanche hole current flowing into the source region, and A2 is the avalanche hole current flowing into the terminal avalanche resistance enhancement structure.
The principle and the beneficial effects of the avalanche tolerance enhancement structure of the trench type double-layer gate power device provided by the embodiment of the invention are as follows:
when the device is subjected to avalanche after being turned off, after avalanche hole current A2 flowing into the terminal avalanche resistance enhancement structure enters a P well of the avalanche resistance enhancement structure, the avalanche hole current can easily enter the front metal of the avalanche resistance enhancement structure through the metal in the contact hole of the avalanche resistance enhancement structure due to the fact that the width of the contact hole of the body region of the avalanche resistance enhancement structure is larger than that of the contact hole of the source region and due to the fact that the N + source region does not block the avalanche resistance enhancement structure. Therefore, the current intensity of the total avalanche hole current of the device entering the terminal avalanche resistance enhancement structure is increased, and the avalanche hole current entering the source region is weakened, so that the avalanche resistance enhancement structure of the embodiment of the invention increases the avalanche resistance EAS compared with the avalanche resistance enhancement structure in the prior art.
Meanwhile, the polysilicon in the avalanche resistance enhancement structure of the embodiment of the invention is zero potential, compared with the N-type shielding gate of the source region in the avalanche resistance enhancement structure in the prior art, the metal layer on the front side of the source region may be positive potential. The attraction effect of electrons in the avalanche tolerance enhancement structure polycrystalline silicon of the embodiment of the invention on avalanche hole current is stronger than that of electrons in the source region N-type shielding grid polycrystalline silicon, so that more avalanche hole current is released through the avalanche tolerance enhancement structure of the embodiment of the invention, and the avalanche tolerance enhancement structure of the embodiment of the invention further increases the avalanche tolerance EAS compared with the avalanche tolerance enhancement structure in the prior art.
Because the source electrode of the trench type double-layer gate power device is possibly connected with the anode electrode in an actual application circuit, namely the difference between the gate voltage and the source electrode voltage is larger than the threshold voltage, the trench type double-layer gate power device structure in the embodiment of the invention increases the difference VDS between the drain voltage and the source voltage by setting the potential of the front metal layer of the avalanche tolerance enhancement structure at zero volt, and avoids the problems of reduction of the internal electric field of a reverse biased PN junction PWELL-N-junction, weaker extraction action of the avalanche tolerance enhancement structure on avalanche hole current, slower extraction speed and insufficient improvement action on avalanche tolerance caused by reduction of the difference VDS between the drain voltage and the source voltage in the existing avalanche tolerance enhancement structure. Therefore, the avalanche capability enhancement structure further increases the avalanche capability EAS than the conventional structure. When the groove type double-layer gate power MOS device is turned off, the extraction time of avalanche hole current caused by the non-clamping inductive switch is short, so that the heat generated by the avalanche hole current is small when the device is turned off, and the temperature rise is reduced.
Under the same chip area condition, the trench type double-layer gate power device provided by the embodiment of the invention has the advantages that the current density of the conducting current is increased, the conducting resistance is reduced and the performance of the product is improved because no region without the N + source region exists in the source region P well.
The avalanche tolerance enhancement structure of the embodiment of the invention has the same effect as the traditional avalanche tolerance enhancement structure, reduces the current density of avalanche hole current flowing through an effective cellular structure, and has equivalent effect of moving the avalanche tolerance enhancement structure of a source region in the traditional structure to a terminal. The total length of the terminal is not increased, so that the trench type double-layer gate power device can save the chip area occupied by the traditional avalanche tolerance enhancement structure, namely under the condition that the chip areas are the same, the forward conducting current density is increased, the conducting resistance is reduced, and the product performance is improved.
In addition, a flowchart of a manufacturing method of the trench type double-layer gate power device in the embodiment of the present invention is shown in fig. 7, and the specific steps are as follows:
s1, forming an N-epitaxial layer 2 on an N + substrate 1;
s2, performing groove photoetching and etching on the N-epitaxial layer 2 to synchronously form a source region groove 12, a terminal region groove 12A and an avalanche capability enhancement structure groove 12B;
s3, synchronously growing and forming a trench field oxide layer 3 and a trench field oxide layer 3A of the terminal region avalanche tolerance enhancement structure on the side wall of the trench;
s4, depositing polycrystalline silicon, performing polycrystalline phosphorus diffusion, photoetching and etching, and synchronously forming a source region N-type shielding gate 6, a terminal region groove polycrystalline silicon 14 and an avalanche tolerance enhancement structure polycrystalline silicon 14A; the terminal region trench polysilicon 14 and the avalanche capability enhancement structure polysilicon 14A are both an integral body;
s5, depositing a high-density oxide film by using a chemical vapor deposition method, and then etching the oxide film back to a specified depth to reserve a sufficient isolation oxide film thickness to form an isolation oxide layer 4; wherein the isolation oxide film is also called an intermediate oxide film, and no oxide layer is arranged above the isolation oxide layer;
s6, forming a gate oxide layer 5 above the isolation oxide layer 4 in the source region trench 12 by using a thermal oxidation method;
s7, depositing N-type polycrystalline silicon, carrying out chemical mechanical polishing until the N-type polycrystalline silicon is flush with the surface of the chip, and removing the polycrystalline silicon and the oxide layer on the surface of the chip to form a control gate 11;
s8, performing boron injection and diffusion to form a P well 7, and then performing N + photoetching, arsenic injection and diffusion to form an N + source region 8;
s9, forming a dielectric layer 9,9A; the material is USG (silicon glass without phosphorus doping) layer and PSG (silicon glass with phosphorus doping) layer;
s10, forming a contact hole by contact hole photoetching and etching, performing contact hole P-type high doping injection, and synchronously forming a source region contact hole 15, an avalanche resistance enhancement structure body region contact hole 15A and an avalanche resistance enhancement structure polycrystalline silicon contact hole 15B;
s11, front metal sputtering, photoetching and etching are carried out, and a source region front metal layer 13C, a terminal region front metal layer 13A and an avalanche capability enhancement structure front metal layer 13D are synchronously formed;
s12, depositing, photoetching and etching a passivation layer to form a passivation layer lead window;
and S13, evaporating the metal to form the back metal 10.
The foregoing is a further detailed description of the invention in connection with specific/preferred embodiments and it is not intended to limit the invention to the specific embodiments described. It will be apparent to those skilled in the art that various substitutions and modifications can be made to the described embodiments without departing from the spirit of the invention, and these substitutions and modifications should be considered to fall within the scope of the invention. In the description of the present specification, reference to the description of "one embodiment," "some embodiments," "preferred embodiments," "example," "specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Those skilled in the art will be able to combine and combine features of different embodiments or examples and features of different embodiments or examples described in this specification without contradiction. Although embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope of the claims.
Claims (10)
1. The groove type double-layer gate power device is characterized in that: the trench type double-layer gate power device sequentially comprises an N + substrate (1), an N-epitaxial layer (2), a P well (7) and a dielectric layer (9, 9A) from bottom to top; a plurality of adjacent source region trenches (12) and a plurality of adjacent terminal region trenches (12A) are respectively arranged between the N-epitaxial layer (2) and the dielectric layers (9, 9A); a trench field oxide layer (3) is arranged on the outer side of the source region trench (12), an N-type shielding gate (6), an isolation oxide layer (4), a gate oxide layer (5) and a control gate (11) are sequentially arranged in the source region trench from bottom to top, an N + source region (8) is arranged between the P well (7) and the dielectric layer (9), and a source region contact hole (15) is arranged between the source region trenches (12) and is connected with a source region front metal layer (13C) through the dielectric layer (9); the terminal region trench field oxide layer (3A) is arranged on the outer side of the terminal region trench (12A), terminal region trench polysilicon (14) is arranged in the terminal region trench (12A) and is wrapped by the terminal region trench field oxide layer (3A) and a dielectric layer (9A), and an avalanche tolerance enhancement structure consisting of a terminal region last terminal region trench ring (12B) and an auxiliary structure thereof is arranged in front of the terminal region trench stop ring (12A).
2. The trench-type double-layer gate power device of claim 1, wherein: the avalanche resistance enhancement structure comprises the dielectric layer (9A), the front metal layer (13D) of the avalanche resistance enhancement structure, an avalanche resistance enhancement structure body area (7A), a body area contact hole (15A), an avalanche resistance enhancement structure polycrystalline silicon contact hole (15B), an avalanche resistance enhancement structure groove field oxide layer (3A) and avalanche resistance enhancement structure polycrystalline silicon (14A).
3. The trench-type double-layer gate power device of claim 2, wherein: the width of the contact hole (15A) of the avalanche capability enhancement structure body region is larger than that of the contact hole (15) of the source region.
4. The trench-type double-layer gate power device of claim 1 or 2, wherein: the avalanche resistance enhancement structure polysilicon (14A) and the avalanche resistance enhancement structure front metal layer (13D) have zero potential.
5. The trench-type double-layer gate power device of claim 4, wherein: the avalanche capability enhancement structure front metal layer (13D) is separated from the source region front metal layer (13C), and the potential of the avalanche capability enhancement structure front metal layer is set to be zero volt.
6. The trench-type double-layer gate power device of claim 1, wherein: the regions of the N + source regions (8) are all arranged in the source region P trap (7).
7. The trench-type double-layer gate power device of claim 1, wherein: and a back metal (10) is arranged on the back surface of the N + substrate (1).
8. A method for manufacturing the trench-type double-layer gate power device according to any one of claims 1 to 7, comprising the steps of:
s1, forming an N-epitaxial layer (2) on an N + substrate (1);
s2, performing groove photoetching and etching on the N-epitaxial layer (2) to synchronously form a source region groove (12), a terminal region groove (12A) and an avalanche capability enhancement structure groove (12B);
s3, synchronously growing and forming a trench field oxide layer (3) and a trench field oxide layer (3A) of a terminal region avalanche tolerance enhancement structure on the side wall of the trench;
s4, depositing polycrystalline silicon, performing polycrystalline phosphorus diffusion, photoetching and etching, and synchronously forming a source region N-type shielding gate (6), a terminal region groove polycrystalline silicon (14) and an avalanche capability enhancement structure polycrystalline silicon (14A);
s5, depositing a high-density oxide film by using a chemical vapor deposition method, and then etching the oxide film back to a specified depth to keep enough thickness of the isolation oxide film to form an isolation oxide layer (4), wherein no oxide layer exists above the isolation oxide layer;
s6, forming a gate oxide layer (5) above the isolation oxide layer (4) in the source region trench (12) by using a thermal oxidation method;
s7, depositing N-type polycrystalline silicon, carrying out chemical mechanical polishing until the N-type polycrystalline silicon is flush with the surface of the chip, and removing the polycrystalline silicon and the oxide layer on the surface of the chip to form a control gate (11);
s8, carrying out boron implantation and diffusion to form a P well (7), and then carrying out N + photoetching, arsenic implantation and diffusion to form an N + source region (8);
s9, forming a dielectric layer (9, 9A);
s10, forming a contact hole by contact hole photoetching and etching, performing contact hole P-type high doping injection, and synchronously forming a source region contact hole (15), an avalanche resistance enhanced structure body region contact hole (15A) and an avalanche resistance enhanced structure polycrystalline silicon contact hole (15B);
s11, front metal sputtering, photoetching and etching are carried out, and a source region front metal layer (13C), a terminal region front metal layer (13A) and an avalanche capability enhancement structure front metal layer (13D) are synchronously formed;
s12, depositing, photoetching and etching a passivation layer to form a passivation layer lead window;
s13, evaporating the metal to form the back metal (10).
9. The method of manufacturing a trench-type double-layer gate power device according to claim 8, wherein in step S5, the termination region trench polysilicon (14) and the avalanche capability enhancement structure polysilicon (14A) are both integrated.
10. The method for manufacturing a trench-type double-layer gate power device according to claim 8, wherein in step S9, the structure of the dielectric layer (9, 9a) is a double-layer structure of a non-phosphorus-doped silicon glass layer and a phosphorus-doped silicon glass layer.
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