CN114220844A - Silicon carbide MOSFET device integrated with SBD and preparation method thereof - Google Patents

Silicon carbide MOSFET device integrated with SBD and preparation method thereof Download PDF

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CN114220844A
CN114220844A CN202111539417.1A CN202111539417A CN114220844A CN 114220844 A CN114220844 A CN 114220844A CN 202111539417 A CN202111539417 A CN 202111539417A CN 114220844 A CN114220844 A CN 114220844A
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contact metal
metal layer
layer
field effect
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罗烨辉
王亚飞
郑昌伟
王志成
刘启军
刘小东
李诚瞻
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Zhuzhou CRRC Times Semiconductor Co Ltd
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Abstract

The invention discloses a silicon carbide MOSFET device integrated with an SBD and a preparation method thereof, wherein the silicon carbide MOSFET device comprises a substrate, an N-epitaxial layer, a P well region, a P + region of a junction field effect region, a P + region and an N + region of a source groove region, a first ohmic contact metal layer, a first Schottky contact metal layer, a second ohmic contact metal layer and a second Schottky contact metal layer; the P + region of the junction field effect region is positioned on one side of the P well region far away from the N + region; the second ohmic contact metal layer covers one surface of the P + region of the junction field effect region, which is far away from the N-epitaxial layer; the first Schottky contact metal layer is positioned on one side, far away from the P well region, of the second ohmic contact metal layer; the second Schottky contact metal layer is arranged on one side, away from the P + region of the junction field effect region, of the second ohmic contact metal layer and is parallel to the P + region of the junction field effect region. The invention can reduce the source contact resistance, improve the through-current capability of the silicon carbide device and improve the reliability of the silicon carbide device.

Description

Silicon carbide MOSFET device integrated with SBD and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a silicon carbide MOSFET device integrated with SBD and a preparation method thereof.
Background
The silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) has the characteristics of low on resistance, high switching speed, high temperature resistance and the like, and has great application advantages in the fields of high-voltage frequency conversion, new energy automobiles, rail transit and the like. In order to improve the current capability of the SiC MOSFET, the flow area is increased by compressing the size of the unit cell, so that the flow capability is improved. When the cell size is continuously compressed, the contact area of the source hole is reduced, the contact resistance of the source electrode is increased, and the reduction of the overall resistance of the device is not facilitated.
Meanwhile, in application scenes of motor driving, traction inversion and the like, a schottky diode is connected in parallel outside a SiC MOSFET, and the reverse follow current capacity is realized by utilizing the low conduction voltage drop of an external anti-parallel diode. But for the module, the packaging area is increased, and the current capacity of the whole device module is reduced. The other method is to utilize a body diode integrated in the SiC MOSFET to perform a freewheeling function when the SiC MOSFET is in reverse conduction. But because the body diode is a PIN structure device, higher turn-on voltage drop and reverse recovery loss are generated. Meanwhile, the conduction of the SiC bipolar device can induce electron-hole recombination, so that stacked layers in the body are expanded, the voltage drop of the device is increased, the reverse bias leakage current is increased, and the reliability of the silicon carbide device is not facilitated.
Therefore, the technical problem to be solved by those skilled in the art is how to increase the source contact area, reduce the source contact resistance, improve the current capacity of the silicon carbide device, and improve the reliability of the silicon carbide device without changing the cell size.
Disclosure of Invention
The invention mainly aims to provide a silicon carbide MOSFET device integrated with an SBD and a preparation method thereof, so as to increase the source contact area, reduce the source contact resistance, improve the through-current capacity of the silicon carbide device and improve the reliability of the silicon carbide device on the premise of not changing the cell size.
In order to solve the problems, the invention provides a silicon carbide MOSFET device integrated with an SBD, which comprises a plurality of cellular structures, wherein each cellular structure comprises a substrate and an N-epitaxial layer formed on the substrate; the P well region, the P + region of the junction field effect region, the P + region of the source electrode groove region and the N + region are positioned in the N-epitaxial layer; a first ohmic contact metal layer, a first Schottky contact metal layer, a second ohmic contact metal layer and a second Schottky contact metal layer which are positioned on the N-epitaxial layer;
the P well region is adjacent to a P + region of the source electrode groove region, the N + region is positioned in the P well region, and the P + region of the source electrode groove region is adjacent to the N + region;
the first part of the first ohmic contact metal layer covers a partial region of one surface, facing away from the N-epitaxial layer, of the N + region, the first part of the first ohmic contact metal layer covers a partial region of one surface, facing towards the P + region of the source groove region, of the N + region, and the first part of the first ohmic contact metal layer covers one surface, facing away from the N-epitaxial layer, of the P + region of the source groove region;
the P + area of the junction field effect area is positioned on one side of the P well area far away from the N + area; the second ohmic contact metal layer covers one surface, deviating from the N-epitaxial layer, of the P + region of the junction field effect region; the first Schottky contact metal layer and the second ohmic contact metal layer are arranged side by side, and the first Schottky contact metal layer is positioned on one side, far away from the P well region, of the second ohmic contact metal layer; the second Schottky contact metal layer is arranged on one side, away from the P + region of the junction field effect region, of the second ohmic contact metal layer and is parallel to the P + region of the junction field effect region.
Further, in the above SBD integrated silicon carbide MOSFET device, the cell structure further includes a gate oxide layer on the N-epitaxial layer;
the gate oxide layer is positioned between the first part of the first ohmic contact metal layer and the second Schottky contact metal layer;
a polycrystalline silicon gate electrode is formed on the gate oxide layer, and an interlayer medium is coated on the periphery of the polycrystalline silicon gate electrode;
the gate oxide layer covers the surface of the P well region, and two sides of the gate oxide layer respectively cover the partial surface of the N + region and the partial surface of the junction field effect region.
Further, in the above SBD integrated silicon carbide MOSFET device, the cell structure further includes a source and a drain;
the source electrode covers the interlayer dielectric, the first ohmic contact metal layer, the first Schottky contact metal layer, the second ohmic contact metal layer and the second Schottky contact metal layer;
the drain electrode is positioned on one side of the substrate, which is far away from the N-epitaxial layer.
Further, in the silicon carbide MOSFET device integrated with the SBD, a depth of the junction field effect groove corresponding to the junction field effect region is 0.25 μm to 0.35 μm.
Furthermore, in the silicon carbide MOSFET device integrated with the SBD, the trench depth of the source trench corresponding to the source trench region is 0.25 μm to 0.35 μm.
Furthermore, in the silicon carbide MOSFET device integrated with the SBD, the depth of the N + region is 0.3-0.4 μm;
the depth of the P well region is 1.0-1.5 μm.
Furthermore, in the silicon carbide MOSFET device integrated with the SBD, the depth of the P + region of the junction field effect region is 1.0-1.6 μm.
Further, in the silicon carbide MOSFET device of the integrated SBD,
the depth of the P + region of the source electrode groove region is 1.0-1.6 mu m.
The invention also provides a preparation method of the silicon carbide MOSFET device integrated with the SBD, which comprises the following steps:
forming an N-epitaxial layer on a substrate;
depositing an oxide layer on one side of the N-epitaxial layer far away from the substrate, forming a P well injection window through photoetching-etching, and forming a P well region through Al ion injection by using the oxide layer as an ion injection mask;
depositing an oxide layer again on one side of the N-epitaxial layer far away from the substrate, and performing reverse etching to form an oxide layer side wall; using the oxide layer side wall as an ion implantation mask, and implanting N ions to form an N + region;
depositing an oxide layer again on one side of the N-epitaxial layer far away from the substrate, forming etching windows of a source groove and a junction field effect groove by photoetching-etching, etching the SiC medium by using the oxide layer as a barrier layer, and forming the source groove and the junction field effect groove on the surface of the N-epitaxial layer;
performing oxide layer deposition, photoetching and etching on the junction field effect groove, wherein the middle area of the junction field effect groove is covered by the oxide layer to form an injection barrier layer; performing Al ion implantation on the source electrode groove to form a P + region of a source electrode groove region, and performing Al ion implantation on the junction field effect groove to form a P + region of the junction field effect region;
removing all oxide layers on the N-epitaxial layer, and performing an activation annealing process under the environment of a first preset temperature to activate the injected Al ions and N ions;
forming a gate oxide layer on the P well region, forming a polysilicon gate electrode on the gate oxide layer, depositing an interlayer dielectric on the polysilicon gate electrode, and forming ohmic contact holes exposing a P + region of the junction field effect region, a P + region of the source groove region and the N + region by etching;
depositing a nitride layer, and performing covering protection on a non-ohmic alloy area in the junction type field effect groove by photoetching-etching;
depositing metal on one side of the N-epitaxial layer, which is far away from the substrate, performing an annealing process at a second preset temperature, forming a first ohmic contact metal layer in a P + region of the source groove region, and forming a second ohmic contact metal layer in the P + region of the junction field effect region;
and corroding and removing the nitride layer, depositing metal again, annealing in a third preset temperature environment, and performing an annealing process to form a first Schottky contact metal layer and a second Schottky contact metal layer in the P + region of the junction field effect region.
Further, the method for manufacturing the SBD integrated silicon carbide MOSFET device further includes:
and depositing metal on one side of the N-epitaxial layer far away from the substrate to form a source electrode, and depositing metal on one side of the substrate far away from the N-epitaxial layer to form a drain electrode.
Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:
according to the silicon carbide MOSFET device integrated with the SBD and the preparation method thereof, the SiC SBD is integrated in the SiC MOSFET cellular structure, and the SiC SBD is used as a freewheeling diode during reverse bias, so that the starting of a body diode is inhibited, and the reliability of long-term working of a chip is improved; when the SBD structure is integrated in the MOSFET cellular structure, the SBD part and the MOSFET part can share part of the areas of the active region and the terminal region, so that the overall power density of the chip is greatly improved, and the module packaging cost is reduced; by utilizing the structure of the groove type source electrode groove area, the contact area of the source electrode hole is increased in a three-dimensional space, the influence of source contact resistance on the whole resistance of the device is reduced, and the output of larger current capacity is facilitated.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a top view of an integrated SBD silicon carbide MOSFET device of the present invention;
FIG. 2 is a cross-sectional view taken along the X-Y direction in FIG. 1;
FIG. 3 is a flow chart of an embodiment of a method of fabricating an integrated SBD silicon carbide MOSFET device of the present invention;
FIG. 4 is a first state diagram formed through steps 300 and 301;
FIG. 5 is a second state diagram formed via step 302;
FIG. 6 is a third state diagram formed via step 303;
FIG. 7 is a fourth state diagram formed via step 304;
FIG. 8 is a fifth state diagram formed via step 305;
FIG. 9 is a sixth state diagram formed via step 306;
FIG. 10 is a seventh state diagram formed via step 307;
fig. 11 is an eighth state diagram formed through step 308 and step 309.
Detailed Description
The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
Fig. 1 is a top view of an integrated SBD silicon carbide MOSFET device of the present invention, and fig. 2 is a cross-sectional view taken in the X-Y direction of fig. 1. As shown in fig. 1-2, the SBD integrated silicon carbide MOSFET device of the present embodiment may include several cell structures. The cellular structure comprises a substrate 10 and an N-epitaxial layer 11 formed on the substrate 10; a P well region 12, a P + region 13 of a junction field effect region (hereinafter referred to as a JFET region), a P + region 14 of a source groove region and an N + region 15 which are positioned in the N-epitaxial layer 11; a first ohmic contact metal layer 16, a first schottky contact metal layer 17, a second ohmic contact metal layer 18 and a second schottky contact metal layer 19 on the N-epitaxial layer 11;
the P well region 12 is adjacent to the P + region 14 of the source trench region, the N + region 15 is located in the P well region 12, and the P + region 14 of the source trench region is adjacent to the N + region 15;
a first part of the first ohmic contact metal layer 16 covers a partial area of one surface of the N + region 15 facing away from the N-epitaxial layer 11, a first part of the first ohmic contact metal layer 16 covers a partial area of one surface of the N + region 15 facing the P + region 14 of the source groove region, and a first part of the first ohmic contact metal layer 16 covers one surface of the P + region 14 of the source groove region facing away from the N-epitaxial layer 11;
the P + region 13 of the JFET region is positioned on one side of the P well region 12 away from the N + region 15; the second ohmic contact metal layer 18 covers one surface of the P + region 13 of the JFET region, which is far away from the N-epitaxial layer 11; the first schottky contact metal layer 17 and the second ohmic contact metal layer 18 are arranged side by side, and the first schottky contact metal layer 17 is located on one side of the second ohmic contact metal layer 18 away from the P-well region 12; the second schottky contact metal layer 19 is disposed on a side of the second ohmic contact metal layer 18 facing away from the P + region 13 of the JFET region and parallel to the P + region 13 of the JFET region.
In a specific implementation process, the integrated SiC SBD is arranged in the JFET area, the area of the JFET area is effectively utilized, the integration level of a cellular structure is higher, and the volume of the cellular structure is reduced.
In a specific implementation process, the integrated SiC SBD is of a groove type structure, so that an electric field of a JFET (junction field effect transistor) area of the SiC MOSFET and a Schottky contact electric field of the SiC SBD are effectively protected, and the blocking capability of the SiC MOSFET device is improved. And in the groove type JFET area part, integration in the three-dimensional direction (namely the second Schottky contact metal layer 19) is carried out on the side wall, the flow area of the Schottky contact is enlarged, and the conduction voltage drop of the diode is reduced.
In a specific implementation process, the source 22 of the SiC MOSFET is designed to be of a groove-shaped structure, and the contact surface of the source 22 is increased by using the groove-shaped side wall of the source hole (the design structure of the first ohmic contact metal layer 16 in fig. 1), so that the through-current path of electrons entering and exiting the source 22 is increased, the contact resistance of the source 22 is reduced, and the through-current capability of the silicon carbide device is improved.
In a specific implementation process, the P + region 14 of the source groove region is formed by using the groove structure to perform deep well injection, so that short circuit with the N + region 15 is better realized, and the inhibition effect on a parasitic NPN transistor is enhanced.
In a specific implementation process, the JFET groove in the JFET area, the source groove in the source groove area and each P + deep well are formed by adopting a synchronous process, the depth of the P + deep wells is consistent and adjustable, and synchronous compromise optimization of an internal body diode electric field and an SBD electric field is facilitated.
According to the silicon carbide MOSFET device integrated with the SBD, the SiC SBD is integrated in the SiC MOSFET cell structure, and is used as a freewheeling diode during reverse bias, so that the on-state of a body diode is inhibited, and the reliability of long-term work of a chip is improved; when the SBD structure is integrated in the MOSFET cellular structure, the SBD part and the MOSFET part can share part of the areas of the active region and the terminal region, so that the overall power density of the chip is greatly improved, and the module packaging cost is reduced; by utilizing the structure of the groove type source electrode groove area, the contact area of the source electrode hole is increased in a three-dimensional space, the influence of source contact resistance on the whole resistance of the device is reduced, and the output of larger current capacity is facilitated.
As shown in fig. 1, the cell structure further includes a gate oxide layer (not shown) on the N-epitaxial layer 11; the gate oxide layer is located between the first portion of the first ohmic contact metal layer 16 and the second schottky contact metal layer 19; a polysilicon gate electrode 20 is formed on the gate oxide layer, and an interlayer medium 21 is coated on the periphery of the polysilicon gate electrode 20; the gate oxide layer covers the surface of the P well region 12, and two sides of the gate oxide layer respectively cover part of the surface of the N + region 15 and part of the surface of the JFET region.
In a specific implementation process, the polysilicon gate electrode 20 of the SiC MOSFET adopts a split gate structure mode, which effectively reduces the gate capacitance and the input capacitance and improves the switching characteristics of the device.
As shown in fig. 2, the cell structure further includes a source electrode 22 and a drain electrode 23; the source electrode 22 covers the interlayer dielectric 21, the first ohmic contact metal layer 16, the first schottky contact metal layer 17, the second ohmic contact metal layer 18 and the second schottky contact metal layer 19; the drain 23 is located on a side of the substrate 10 facing away from the N-epitaxial layer 11.
In a specific implementation process, the depth of the JFET groove corresponding to the JFET region is 0.25-0.35 μm. The groove depth of the source groove corresponding to the source groove region is 0.25-0.35 μm. The depth of the N + region 15 is 0.3-0.4 μm; the depth of the P well region 12 is 1.0-1.5 μm. The depth of the P + region 13 of the JFET region is 1.0-1.6 microns. The depth of the P + region 14 of the source groove region is 1.0-1.6 μm.
Fig. 3 is a flow chart of an embodiment of a method of fabricating an integrated SBD silicon carbide MOSFET device according to the present invention, which may include the steps of, as shown in fig. 3:
300. forming an N-epitaxial layer 11 on a substrate 10;
specifically, N-epitaxial layer 11 is prepared, and N-epitaxial layer 11 contains doping concentration 1E18cm-3～1E19cm-3Is provided with an N-epitaxial layer 11 over the N + substrate 10, the N-epitaxial layer 11 having a concentration of about 1E14 cm-3～5E16cm-3Specific needs ofThe chip voltage resistance is optimized.
301. Depositing an oxide layer A on one side of the N-epitaxial layer 11, which is far away from the substrate 10, forming a P-well injection window through photoetching-etching, and forming a P-well region 12 through Al ion injection by using the oxide layer as an ion injection mask;
specifically, the thickness of the oxide layer a in this step may be 1.5 μm to 3.0 μm, and the depth of the P-well region 12 may be 1.0 μm to 1.5 μm.
Fig. 4 is a first state diagram formed through steps 300 and 301. As shown in fig. 4, the silicon carbide MOSFET device in this state may include a substrate 10, an N-epitaxial layer 11, an oxide layer a, and a P-well region 12.
302. Depositing an oxide layer A again on one side of the N-epitaxial layer 11 far away from the substrate 10, and performing reverse etching to form an oxide layer side wall B; using the oxide layer side wall B as an ion implantation mask, and implanting N ions to form an N + region 15;
in one implementation, the depth of the N + region 15 may be 0.3 μm to 0.4 μm. The oxide layer a may be the same as or different from the oxide layer in step 1. For example, it may be silicon oxide.
It should be noted that, the oxide layer sidewall B can be used to implement an accurate and controllable 0.25 μm-0.8 μm self-aligned channel according to actual needs, so that the channel length is greatly reduced, and the current output capability of the device is improved.
Fig. 5 is a second state diagram formed through step 302. As shown in fig. 5, in the sic MOSFET device in this state, oxide spacers B and N + regions 15 are added based on those shown in fig. 4.
303. Depositing an oxide layer A again on one side of the N-epitaxial layer 11, which is far away from the substrate 10, forming etching windows of a source groove C and a junction field effect groove D through photoetching-etching, etching the SiC medium by using the oxide layer as a barrier layer, and forming the source groove C and the junction field effect groove D on the surface of the N-epitaxial layer 11;
in one embodiment, the thickness of the oxide layer A in this step may be 1.0 μm to 2.0 μm. The depth of the JFET groove D corresponding to the JFET area is 0.25-0.35 mu m. The depth of the source electrode groove C corresponding to the source electrode groove region is 0.25-0.35 μm.
Fig. 6 is a third state diagram formed through step 303. As shown in fig. 6, in the silicon carbide MOSFET device in this state, based on the state shown in fig. 5, the source trench C and the jfet trench D are added, the oxide layer sidewall B is reduced, and the position of the oxide layer a is changed.
304. Performing oxide layer deposition, photoetching and etching on the junction field effect groove D, wherein the middle area of the junction field effect groove D is covered by the oxide layer A to form an injection barrier layer; performing Al ion implantation on the source electrode groove to form a P + region 14 of a source electrode groove region, and performing Al ion implantation on the junction field effect groove D to form a P + region 13 of a JFET region;
wherein the depth of the P + region 13 of the JFET region is 1.0-1.6 microns. The depth of the P + region 14 of the source groove region is 1.0-1.6 μm.
Fig. 7 is a fourth state diagram formed via step 304. As shown in fig. 7, in the sic MOSFET device in this state, based on fig. 6, a portion of the oxide layer a, the P + region 14 of the source trench region, and the P + region 13 forming the JFET region are added, and the added oxide layer a may be the same as or different from the original oxide layer a.
305. Removing all oxide layers on the N-epitaxial layer 11, and performing an activation annealing process under a first preset temperature environment to activate the injected Al ions and N ions;
wherein the first preset temperature may be 1700 ℃ to 1800 ℃. The time for activating the annealing process may be 10min to 40 min.
Fig. 8 is a fifth state diagram formed through step 305. As shown in fig. 8, the silicon carbide MOSFET device in this state has all of the oxide layer removed based on that shown in fig. 7.
306. Forming a gate oxide layer on the P well region 12, forming a polysilicon gate electrode 20 on the gate oxide layer, depositing an interlayer medium 21 on the polysilicon gate electrode 20, and forming ohmic contact holes exposing a P + region 13 of the JFET region, a P + region 14 of the source groove region and an N + region 15 by etching;
fig. 9 is a sixth state diagram formed via step 306. As shown in fig. 9, the silicon carbide MOSFET device in this state is added with a gate oxide layer (not shown), a polysilicon gate electrode 20 and an interlayer dielectric 21, based on that shown in fig. 8.
307. Depositing a nitride layer E, and performing covering protection on a non-ohmic alloy area in the junction type field effect groove through photoetching-etching;
the nitride layer E may have a thickness of 0.5 to 1.0 μm, and may be silicon nitride.
Fig. 10 is a seventh state diagram formed through step 307. As shown in fig. 10, the silicon carbide MOSFET device in this state is added with a nitride layer E in addition to that shown in fig. 9.
308. Depositing metal on one side of the N-epitaxial layer 11, which is far away from the substrate 10, performing an annealing process at a second preset temperature to form a first ohmic contact metal layer 16 in a P + region 14 of the source groove region and a second ohmic contact metal layer 18 in a P + region 13 of the JFET region;
wherein the second preset temperature can be 900-1000 ℃. The annealing process time of the step can be 2 min-5 min. The metal of this step may be at least one of Ni, Ti, Al, etc.
309. Corroding and removing the nitride layer, depositing metal again, annealing in a third preset temperature environment, and performing an annealing process to form a first Schottky contact metal layer 17 and a second Schottky contact metal layer 19 in the P + region 13 of the JFET region;
wherein the third preset temperature may be 400-600 ℃. The annealing process time of the step can be 5 min-10 min. The metal of this step may be at least one of Ti, Mo, etc.
Fig. 11 is an eighth state diagram formed through step 308 and step 309. As shown in fig. 11, the silicon carbide MOSFET device in this state has a reduced nitride layer based on that shown in fig. 10. A first schottky contact metal layer 17, a second schottky contact metal layer 19, a first ohmic contact metal layer 16 and a second ohmic contact metal layer 18 are added.
310. And depositing metal on the side of the N-epitaxial layer 11 far away from the substrate 10 to form a source 22, and depositing metal on the side of the substrate 10 far away from the N-epitaxial layer 11 to form a drain 23.
Specifically, Al metal may be deposited on a side of the N-epitaxial layer 11 away from the substrate to form a source, and a source electrode structure electrode and a gate electrode are extracted. Can be annealed for 2min to 5min at the temperature of 900 ℃ to 1000 ℃ to form the electrode. See figure 1 for details.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that the terms "first," "second," and the like in the description of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present invention, the meaning of "a plurality" means at least two unless otherwise specified.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships that the products of the present invention are usually placed in when used, and are only used for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have specific orientations, be constructed in specific orientations, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. The silicon carbide MOSFET device integrated with the SBD is characterized by comprising a plurality of cellular structures, wherein each cellular structure comprises a substrate and an N-epitaxial layer formed on the substrate; the P well region, the P + region of the junction field effect region, the P + region of the source electrode groove region and the N + region are positioned in the N-epitaxial layer; a first ohmic contact metal layer, a first Schottky contact metal layer, a second ohmic contact metal layer and a second Schottky contact metal layer which are positioned on the N-epitaxial layer;
the P well region is adjacent to a P + region of the source electrode groove region, the N + region is positioned in the P well region, and the P + region of the source electrode groove region is adjacent to the N + region;
the first part of the first ohmic contact metal layer covers a partial region of one surface, facing away from the N-epitaxial layer, of the N + region, the first part of the first ohmic contact metal layer covers a partial region of one surface, facing towards the P + region of the source groove region, of the N + region, and the first part of the first ohmic contact metal layer covers one surface, facing away from the N-epitaxial layer, of the P + region of the source groove region;
the P + area of the junction field effect area is positioned on one side of the P well area far away from the N + area; the second ohmic contact metal layer covers one surface, deviating from the N-epitaxial layer, of the P + region of the junction field effect region; the first Schottky contact metal layer and the second ohmic contact metal layer are arranged side by side, and the first Schottky contact metal layer is positioned on one side, far away from the P well region, of the second ohmic contact metal layer; the second Schottky contact metal layer is arranged on one side, away from the P + region of the junction field effect region, of the second ohmic contact metal layer and is parallel to the P + region of the junction field effect region.
2. The integrated SBD silicon carbide MOSFET device of claim 1, wherein said cellular structure further comprises a gate oxide layer on said N-epitaxial layer;
the gate oxide layer is positioned between the first part of the first ohmic contact metal layer and the second Schottky contact metal layer;
a polycrystalline silicon gate electrode is formed on the gate oxide layer, and an interlayer medium is coated on the periphery of the polycrystalline silicon gate electrode;
the gate oxide layer covers the surface of the P well region, and two sides of the gate oxide layer respectively cover the partial surface of the N + region and the partial surface of the junction field effect region.
3. The SBD integrated silicon carbide MOSFET device of claim 2, wherein the cell structure further comprises a source and a drain;
the source electrode covers the interlayer dielectric, the first ohmic contact metal layer, the first Schottky contact metal layer, the second ohmic contact metal layer and the second Schottky contact metal layer;
the drain electrode is positioned on one side of the substrate, which is far away from the N-epitaxial layer.
4. The integrated SBD silicon carbide MOSFET device of claim 1, wherein the junction field effect region corresponds to a junction field effect trench having a trench depth of 0.25 μ ι η to 0.35 μ ι η.
5. The SBD integrated silicon carbide MOSFET device of claim 1, wherein the source trench region has a corresponding source trench depth of 0.25 μm to 0.35 μm.
6. The integrated SBD silicon carbide MOSFET device of claim 1, wherein the depth of the N + region is 0.3 μ ι η to 0.4 μ ι η;
the depth of the P well region is 1.0-1.5 μm.
7. The integrated SBD silicon carbide MOSFET device of claim 1, wherein the P + region of the junction field-effect region has a depth of 1.0 μ ι η to 1.6 μ ι η.
8. The integrated SBD silicon carbide MOSFET device of claim 1,
the depth of the P + region of the source electrode groove region is 1.0-1.6 mu m.
9. A preparation method of a silicon carbide MOSFET device integrated with SBD is characterized by comprising the following steps:
forming an N-epitaxial layer on a substrate;
depositing an oxide layer on one side of the N-epitaxial layer far away from the substrate, forming a P well injection window through photoetching-etching, and forming a P well region through Al ion injection by using the oxide layer as an ion injection mask;
depositing an oxide layer again on one side of the N-epitaxial layer far away from the substrate, and performing reverse etching to form an oxide layer side wall; using the oxide layer side wall as an ion implantation mask, and implanting N ions to form an N + region;
depositing an oxide layer again on one side of the N-epitaxial layer far away from the substrate, forming etching windows of a source groove and a junction field effect groove by photoetching-etching, etching the SiC medium by using the oxide layer as a barrier layer, and forming the source groove and the junction field effect groove on the surface of the N-epitaxial layer;
performing oxide layer deposition, photoetching and etching on the junction field effect groove, wherein the middle area of the junction field effect groove is covered by the oxide layer to form an injection barrier layer; performing Al ion implantation on the source electrode groove to form a P + region of a source electrode groove region, and performing Al ion implantation on the junction field effect groove to form a P + region of the junction field effect region;
removing all oxide layers on the N-epitaxial layer, and performing an activation annealing process under the environment of a first preset temperature to activate the injected Al ions and N ions;
forming a gate oxide layer on the P well region, forming a polysilicon gate electrode on the gate oxide layer, depositing an interlayer dielectric on the polysilicon gate electrode, and forming ohmic contact holes exposing a P + region of the junction field effect region, a P + region of the source groove region and the N + region by etching;
depositing a nitride layer, and performing covering protection on a non-ohmic alloy area in the junction type field effect groove by photoetching-etching;
depositing metal on one side of the N-epitaxial layer, which is far away from the substrate, performing an annealing process at a second preset temperature, forming a first ohmic contact metal layer in a P + region of the source groove region, and forming a second ohmic contact metal layer in the P + region of the junction field effect region;
and corroding and removing the nitride layer, depositing metal again, annealing in a third preset temperature environment, and performing an annealing process to form a first Schottky contact metal layer and a second Schottky contact metal layer in the P + region of the junction field effect region.
10. The method of manufacturing an SBD integrated silicon carbide MOSFET device according to claim 9, further comprising:
and depositing metal on one side of the N-epitaxial layer far away from the substrate to form a source electrode, and depositing metal on one side of the substrate far away from the N-epitaxial layer to form a drain electrode.
CN202111539417.1A 2021-12-15 2021-12-15 Silicon carbide MOSFET device integrated with SBD and preparation method thereof Pending CN114220844A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114927562A (en) * 2022-07-20 2022-08-19 深圳平创半导体有限公司 Silicon carbide JFET device structure and preparation method thereof
CN115020479A (en) * 2022-08-10 2022-09-06 深圳平创半导体有限公司 Depletion type silicon carbide bipolar device structure and manufacturing method
CN115020479B (en) * 2022-08-10 2022-11-11 深圳平创半导体有限公司 Depletion type silicon carbide bipolar device structure and manufacturing method
CN115579399A (en) * 2022-12-12 2023-01-06 深圳平创半导体有限公司 Silicon carbide MOSFET cell layout structure
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