CN117995841A - LVFF silicon carbide field effect transistor and preparation process - Google Patents

Abstract

The invention belongs to the technical field of semiconductors, and discloses a LVFF silicon carbide field effect transistor and a preparation process thereof, wherein the silicon carbide field effect transistor comprises a silicon carbide MOSFET cell and a silicon carbide SBD cell; the silicon carbide MOSFET cell comprises a SiC epitaxial layer, a grid structure is arranged on the first surface of the SiC epitaxial layer, an SBD groove is arranged at a preset position of a non-grid region on the first surface of the SiC epitaxial layer, and the silicon carbide SBD cell is integrated in the SBD groove or the non-grid region on the first surface; because the SBD is directly integrated into the MOSFET chip, the packaging cost is reduced, no additional external devices or pins thereof are needed, the size of the devices can be greatly reduced, and the integration level of the chip is improved; and the current distribution is more uniform when the SBD is reversely conducted, parasitic parameters caused by the interconnection of the diode and the MOSFET are eliminated, the switching loss of the system is reduced, the power conversion efficiency is improved, and the overall performance of the device is improved.

Description

LVFF silicon carbide field effect transistor and preparation process

Technical Field

The invention relates to the technical field of semiconductors, in particular to a LVFF silicon carbide field effect transistor and a preparation process thereof.

Background

Silicon carbide (SiC) has led to a revolutionary revolution in the field of high power electronics as a third generation semiconductor material with its excellent physical properties, namely wide forbidden bandwidth, high breakdown field strength, high thermal conductivity and carrier saturation velocity. Compared with the traditional silicon (Si) semiconductor, the silicon carbide material can stably work in a wider temperature range and bear higher voltage and current, thereby remarkably improving the efficiency and the power density of the power converter and reducing the energy loss. Therefore, the silicon carbide MOSFET is a core technology for high-efficiency conversion of modern energy, and is widely applied to the fields of motor driving of electric automobiles, vehicle-mounted Charging Systems (OBCs), renewable energy sources such as solar inverters, charging piles, high-power industrial power supplies and the like.

In the prior art, a parasitic Pin body diode is embedded in the structure of the silicon carbide MOSFET, the body diode plays a role of a freewheeling diode during the turn-off period of the power MOSFET, in order to solve the performance defect of the silicon carbide MOSFET, an external parallel silicon carbide SBD diode is generally adopted, but an external layout mode introduces additional leads and lines, more parasitic inductance is brought, the performance of the device is disturbed, and in the combined structure of the silicon carbide SBD diode and the silicon carbide MOSFET chip, the overall structural layout size is larger, the occupied area of the chip is larger, and the improvement of the chip integration level is not facilitated.

In view of this, improvements in silicon carbide MOSFETs in the prior art are needed to address the technical problem of parallel SBD diodes affecting device performance.

Disclosure of Invention

The invention aims to provide LVFF silicon carbide field effect transistor and a preparation process thereof, which solve the technical problems.

To achieve the purpose, the invention adopts the following technical scheme:

a LVFF silicon carbide field effect transistor comprises a silicon carbide MOSFET cell and a silicon carbide SBD cell;

The silicon carbide MOSFET cell comprises a SiC epitaxial layer, a grid structure is arranged on the first surface of the SiC epitaxial layer, an SBD groove is arranged at a preset position of a non-grid region on the first surface of the SiC epitaxial layer, and the silicon carbide SBD cell is integrated in the SBD groove or the non-grid region on the first surface.

Alternatively to this, the method may comprise,

The silicon carbide MOSFET cell also comprises a SiC substrate and a source metal layer, wherein the second surface of the SiC substrate is laminated on the SiC epitaxial layer;

The source metal layer is deposited on the first surface of the SiC epitaxial layer, and the source metal layer is deposited to cover the grid structure and the silicon carbide SBD cell;

the first surface of the SiC epitaxial layer is also provided with a PN structure part, and the PN structure part comprises a P-well layer, an N-type heavily doped layer and a source P-type heavily doped layer which are sequentially arranged.

Alternatively to this, the method may comprise,

And two grid structures are arranged on the first surface of the SiC epitaxial layer, and the SBD groove is arranged between the two grid structures.

Optionally, the gate structure includes a gate oxide layer stacked on the first surface of the SiC epitaxial layer, and a gate electrode is stacked on the gate oxide layer;

and a gate dielectric layer is arranged outside the gate oxide layer and the gate electrode.

The invention also provides a preparation process of LVFF silicon carbide field effect transistor, which is used for preparing the LVFF silicon carbide field effect transistor, and comprises the following steps:

Preparing a substrate layer of a silicon carbide MOSFET;

forming a PN structure part on the substrate layer through a high-temperature ion implantation doping process;

sequentially preparing and forming two grid structures which are arranged at intervals on the substrate layer through deposition and photoetching;

and etching an SBD groove on the surface of the substrate layer between the two grid structures, and integrating a silicon carbide SBD cell in the SBD groove through deposition and photoetching.

Optionally, the preparing a substrate layer of the silicon carbide MOSFET; the method specifically comprises the following steps:

And providing a SiC substrate, and epitaxially growing a SiC epitaxial layer on the SiC substrate to obtain the base layer for preparing the silicon carbide MOSFET.

Optionally, forming a PN structure part on the substrate layer through a high-temperature ion implantation doping process; the method specifically comprises the following steps:

depositing a first hard mask masking layer on the substrate layer, and photoetching a first hollow area capable of exposing the surface of the substrate layer on the first hard mask masking layer;

injecting high-temperature ions of a P well into the first hard mask masking layer to prepare a P well layer corresponding to the first hollowed-out area on the surface of the substrate layer;

Removing the first hard mask masking layer;

Depositing a second hard mask masking layer on the substrate layer, and photoetching a second hollow area capable of exposing the surface of the substrate layer on the second hard mask masking layer;

Injecting N+ high-temperature ions into the second hard mask masking layer to prepare an N-type heavily doped layer corresponding to the second hollowed-out area on the surface of the substrate layer; the P-type heavily doped layer is positioned in the middle of the P-well layer;

Removing the second hard mask masking layer;

Depositing a third hard mask masking layer on the substrate layer, and photoetching a third hollow area capable of exposing the surface of the substrate layer on the third hard mask masking layer;

injecting P+ high-temperature ions into the third hard mask masking layer to prepare a P-type heavily doped layer corresponding to the third hollowed-out area on the surface of the substrate layer; the P-type heavily doped layer is positioned at one side part of the P-well layer;

And removing the third hard mask layer.

Optionally, the two gate structures arranged at intervals are sequentially prepared and formed on the substrate layer through deposition and photoetching; the method specifically comprises the following steps:

Forming a gate oxide layer on the surface of the substrate layer through gate oxidation and post annealing;

Forming a gate electrode on the gate oxide layer through a polycrystalline deposition level;

photoetching and etching the gate oxide layer and the gate electrode to form two gate islands which are arranged at intervals;

Forming a grid dielectric structure coated on the two grid islands through dielectric layer deposition on the substrate layer;

and photoetching and etching a grid groove body in the middle of the grid dielectric structure to prepare and form two grid structures which are arranged at intervals.

Optionally, etching an SBD trench on the surface of the substrate layer between the two gate structures, and integrating a silicon carbide SBD cell in the SBD trench by deposition and lithography; the method specifically comprises the following steps:

Etching an SBD groove on the surface of the substrate layer along the position of the grid groove body;

Photoetching a lead hole in the SBD groove;

and integrating the SBD unit cells into the SBD grooves through SBD barrier metal sputtering and photoetching.

Optionally, the integrating the silicon carbide SBD cells in the SBD trenches by deposition and lithography further comprises:

And performing source metal sputtering and photoetching on the substrate layer to deposit and form a source metal layer coated on the gate structure on the surface of the substrate layer.

Compared with the prior art, the invention has the following beneficial effects: the device comprises an SiC epitaxial layer which is the basis of the whole device and comprises a charge transmission channel; a grid structure is configured on the first surface of the SiC epitaxial layer, and silicon carbide SBD cells are integrated in a non-grid region of the SiC epitaxial layer through a preset groove so as to integrate the silicon carbide SBD cells into the same silicon wafer on the premise of not affecting the function of the MOSFET cells; the SBD is directly integrated into the MOSFET chip, so that the packaging cost is reduced, an additional external device and pins thereof are not needed, the size of the device can be greatly reduced, and the integration level of the chip is improved; and the current distribution is more uniform when the SBD is reversely conducted, parasitic parameters caused by the interconnection of the diode and the MOSFET are eliminated, the switching loss of the system is reduced, the power conversion efficiency is improved, and the overall performance of the device is improved.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained from these drawings without inventive faculty for a person skilled in the art.

The structures, proportions, sizes, etc. shown in the drawings are shown only in connection with the present disclosure, and are not intended to limit the scope of the invention, since any modification, variation in proportions, or adjustment of the size, etc. of the structures, proportions, etc. should be considered as falling within the spirit and scope of the invention, without affecting the effect or achievement of the objective.

FIG. 1 is a schematic diagram of a LVFF SiC FET according to one embodiment;

FIG. 2 is a second schematic diagram of a LVFF SiC FET in accordance with one embodiment;

FIG. 3 is a third schematic diagram of a LVFF SiC FET according to the first embodiment;

FIG. 4 is a schematic diagram of LVFF SiC field effect transistor according to one embodiment;

fig. 5 is a schematic view of a preparation flow of a substrate layer in the preparation process of the second embodiment;

fig. 6 is a schematic diagram of a P-well layer preparation flow of the preparation process of the second embodiment;

fig. 7 is a schematic diagram of a preparation flow of an N-type heavily doped layer in the preparation process of the second embodiment;

fig. 8 is a schematic diagram of a preparation flow of a source P-type heavily doped layer in the preparation process of the second embodiment;

fig. 9 is a schematic diagram of a preparation flow of a gate island in the preparation process of the second embodiment;

fig. 10 is a schematic diagram of a manufacturing flow of a gate structure in the manufacturing process of the second embodiment;

Fig. 11 is a schematic diagram of a preparation flow of an integrated silicon carbide SBD cell according to the preparation process of the second embodiment;

fig. 12 is a schematic diagram of a preparation flow of a source metal layer in the preparation process of the second embodiment;

Fig. 13 is a schematic diagram showing a reverse conduction curve of a silicon carbide MOSFET with an integrated SBD structure prepared by the preparation process of the second embodiment.

Reference numerals illustrate:

Detailed Description

In order to make the objects, features and advantages of the present invention more comprehensible, the technical solutions in the embodiments of the present invention are described in detail below with reference to the accompanying drawings, and it is apparent that the embodiments described below are only some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "top", "bottom", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. It is noted that when one component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.

The technical scheme of the invention is further described below by the specific embodiments with reference to the accompanying drawings.

Embodiment one:

Referring to fig. 1-4, embodiments of the present invention provide LVFF silicon carbide field effect transistors (LVFF refers to "low forward conduction voltage drop") comprising silicon carbide MOSFET cell 100 and silicon carbide SBD cell 200; the silicon carbide MOSFET cell 100 includes a SiC epitaxial layer 102, a gate structure 110 is disposed on a first surface of the SiC epitaxial layer 102, an SBD trench 120 is disposed at a predetermined location of a non-gate region on the first surface of the SiC epitaxial layer 102, and the silicon carbide SBD cell 200 is integrated within the SBD trench 120 or in the non-gate region on the first surface.

By incorporating the silicon carbide SBD cell 200 in place of the parasitic body diode, the forward voltage drop of the MOSFET in the off state can be significantly reduced, thereby improving the energy efficiency of the system and reducing heat generation, which is critical for high power and high efficiency applications. To facilitate achieving the LVFF effect mentioned in the subject matter.

Four different layouts of the integrated SBD structure silicon carbide MOSFET of the present solution are shown in connection with fig. 1-4.

The silicon carbide SBD cell 200 shown in FIG. 2 is integrated within the silicon carbide MOSFET cell 100, and the integrated SBD is on the surface of the chip, which is a planar structure;

The structural silicon carbide SBD cell 200 shown in fig. 1 is also integrated in the silicon carbide MOSFET cell 100, unlike fig. 2, the structural silicon carbide SBD cell 200 is integrated in the SBD trench 120, and both the side and bottom of the SBD trench 120 may be SBD structures, and the SBD is in the longitudinal direction, so that the cell size can be further reduced, and the specific on-resistance of the chip can be improved; the requirements of the process are relatively high for both fig. 2 and fig. 1.

Fig. 3 is another structure and method of integrating a silicon carbide SBD cell 200 by using a silicon carbide MOSFET cell 100 and a silicon carbide SBD cell 200, wherein the structure of fig. 3 realizes the integration of the silicon carbide SBD cell 200 by distributing the silicon carbide MOSFET cell 100 and the silicon carbide SBD cell 200 at intervals, which has lower requirements on the process, and the number ratio of the silicon carbide MOSFET cell 100 to the silicon carbide SBD cell 200 can be adjusted according to the requirement of the electrical characteristics as shown in fig. 4 to balance the on-resistance characteristics and the reverse VF characteristics of the integrated SBD and SiCMOSFET.

The description is given with reference to fig. 1: the integrated silicon carbide SBD is placed in the JFET region of the silicon carbide planar MOSFET, and the structure of the groove is adopted, so that the size of a cell is further reduced, the problem that a grid oxide layer of the JFET region bears high field intensity under the condition of high drain-source reverse bias is solved, and the reliability of the device is improved. The depth of the silicon carbide integrated SBD groove is generally smaller than that of a P well, the depth of the P well is generally about 0.5-1.5um, the width of the SBD groove is generally about 0.5-2um, the side edge and the bottom of the groove are all Schottky contacts, and high barrier metals such as titanium, nickel and the like are generally adopted as Schottky contact metals.

Fig. 2 illustrates: the integrated silicon carbide SBD cell 200 is placed in the JFET region of the silicon carbide MOSFET cell 100, adopts a planar structure, reduces the problem that a grid oxide layer of the JFET region bears high field strength under the condition of high drain-source reverse bias, and improves the reliability of the device. The schottky contact metal is usually a high barrier metal such as titanium or nickel.

The explanation is given with reference to fig. 3: the integrated silicon carbide SBD cell 200 of the present invention is placed in the JFET region of the silicon carbide MOSFET cell 100 and adopts a planar structure, and is uniformly arranged and placed in a certain proportion with the silicon carbide MOSFET cell 100, typically a silicon carbide MOSFET cell: the number of silicon carbide SBD cells is 6:1 to 1: 1. The schottky contact metal of the integrated silicon carbide SBD cell is typically a high barrier metal such as titanium, nickel, etc.

It should be noted that the silicon carbide MOSFET cell 100 is included in the SiC epitaxial layer 102, which is a special semiconductor layer with highly controlled doping characteristics for forming the main operating region of the MOSFET, and the core function of the silicon carbide MOSFET cell 100 is to control the flow of current, thereby achieving the functions of switching and regulating power transfer. The gate structure 110 generally includes a gate oxide layer 106 and a gate electrode 107, which are formed by deposition and photolithographic processes. The function of the gate structure 110 is to control the flow of electrons from the source to the drain channel, i.e., to control the switching action of the MOSFET.

Silicon carbide SBD cell 200: the silicon carbide SBD cells 200 are formed by contact of the schottky barrier metal with the SiC epitaxial layer 102, mainly concentrated in the pre-built SBD trench 120, and the SBD trench 120 structure is formed in the non-gate region of the SiC epitaxial layer 102, typically to a depth deeper than the depth of the P-well layer 103. The integrated SBD cell assumes the role of a freewheeling diode when the silicon carbide MOSFET is turned off, but has a lower forward voltage drop than a conventional parasitic body diode, thus achieving lower conduction losses. The schottky contact metal is typically a metal with a high barrier height, such as titanium or nickel, to optimize the SBD performance.

The working principle of the invention is as follows: the device comprises a SiC epitaxial layer 102 which is the basis of the whole device and comprises a charge transmission channel; a gate structure 110 is configured on the first surface of the SiC epitaxial layer 102, and a silicon carbide SBD cell 200 is integrated in a non-gate region of the SiC epitaxial layer 102 through a preset trench, so that the silicon carbide SBD cell 200 is integrated into the same silicon wafer on the premise of not affecting the MOSFET cell function; compared with the silicon carbide MOSFET in the prior art, the SBD is directly integrated into the MOSFET chip, so that the packaging cost is reduced, no additional external device or pins thereof are needed, the size of the device can be greatly reduced, and the integration level of the chip is improved; and the current distribution is more uniform when the SBD is reversely conducted, parasitic parameters caused by the interconnection of the diode and the MOSFET are eliminated, the switching loss of the system is reduced, the power conversion efficiency is improved, and the overall performance of the device is improved.

In this embodiment, the silicon carbide MOSFET cell 100 further includes a SiC substrate 101 and a source metal layer 109, the second surface of the SiC substrate 101 being laminated on the SiC epitaxial layer 102;

SiC substrate 101 is the structural basis of the entire LVFF silicon carbide field effect transistor, and SiC substrate 101 is a thick and strong layer of silicon carbide material carrying all other device cells. On SiC substrate 101, siC epitaxial layer 102 is stacked, siC epitaxial layer 102 typically being thinner than the substrate and having finer doping control, which is a critical part in forming MOSFET channels and other semiconductor device functional structures.

A source metal layer 109 is deposited on the first surface of the SiC epitaxial layer 102, and the source metal layer 109 is deposited to cover the gate structure 110 and the silicon carbide SBD cell 200;

a source metal layer 109 is deposited on the first surface of SiC epitaxial layer 102 and covers gate structure 110 and silicon carbide SBD cell 200. This outer metal is an important ring for current injection and extraction, which is in direct contact with the source P-type heavily doped layer 105, through which current is allowed to flow into the SiC epitaxial layer 102 and channel when the MOSFET device is turned on.

The first surface of the SiC epitaxial layer 102 is further provided with a PN structure portion 130, and the PN structure portion 130 includes a P-well layer 103, an N-type heavily doped layer 104, and a source P-type heavily doped layer 105, which are sequentially provided.

The PN structure portion 130 is necessary for constructing MOSFETp-N junction, and includes a P-well layer 103, an N-type heavily doped layer 104 and a source P-type heavily doped layer 105 which are sequentially arranged; the P-well layer 103 is a lightly doped P-type semiconductor region that forms a P-N junction with the N-type epitaxial layer, which is a critical structure for the operation of the MOSFET cell. An N-type heavily doped layer 104 is located above the P-well layer 103, adjacent to the source P-type heavily doped layer 105, which is used to form a source region and is electrically connected to the source metal layer 109. These layers are designed to optimize the threshold voltage and switching characteristics of the device.

Wherein the depth of the SBD trench 120 is greater than the depth of the P-well layer 103; the depth of the P-well layer 103 is generally about 0.5-1.5um, and the depth of the SBD trench 120 is generally about 0.5-2 um.

The depth of the SBD trench 120 is designed to be greater than the depth of the P-well layer 103, ensuring functional separation of the SBD from the MOSFET and optimizing the performance of the silicon carbide SBD cell 200; the depth of the P-well layer 103 is typically between 0.5-1.5 microns, while the depth of the SBD trench 120 is controlled to be in the range of 0.5-2 microns. This design allows the MOSFET and SBD to be built on the same SiC substrate 101 while the silicon carbide SBD can withstand higher reverse voltages without causing damage to the silicon carbide MOSFET cell 100 because of the control of the depth of the SBD trench 120.

In this embodiment, two gate structures 110 are disposed on the first surface of the SiC epitaxial layer 102, and the sbd trench 120 is disposed between the two gate structures 110.

The present device employs a dual gate configuration for forming a dual gate MOSFET, which provides finer control by varying the voltage distribution across the two gates to regulate current flow.

The SBD trench 120 is formed between the two gate structures 110, and the space between the two gate cells is used to layout the SBD cells; this layout is intended to integrate the SBD into the main active area of the MOSFET, which also means that the location of the SBD cells is optimized in order to reduce the forward voltage drop of the device while ensuring that the switching function of the MOSFET is not affected.

Further illustratively, the gate structure 110 includes a gate oxide layer 106 laminated on the first surface of the SiC epitaxial layer 102, the gate oxide layer 106 having a gate electrode 107 laminated thereon; a gate dielectric layer 108 is provided outside the gate oxide layer 106 and the gate electrode 107.

Gate oxide layer 106: this is an insulating layer that is directly laminated on the first surface of SiC epitaxial layer 102, typically made of silicon dioxide (SiO 2) or similar material. The main function of the gate oxide 106 is to isolate the gate electrode 107 from the SiC channel to avoid direct current flow.

Gate electrode 107: this portion is provided over the gate oxide layer 106 and is typically made of a metal or polysilicon material. As one electrode, it is responsible for providing a control voltage to the SiC channel under the gate oxide 106, thereby controlling the concentration of electrons in the gate region.

Gate dielectric layer 108: this layer is added outside of the gate oxide layer 106 and the gate electrode 107 to protect the gate structure 110, prevent damage or contamination of the electrode layer, and provide additional electrical field effect, thereby improving the electrical characteristics of the device. Meanwhile, the gate dielectric layer 108 also helps to reduce leakage current and improve the performance and reliability of the MOSFET.

Embodiment two:

The present invention also provides a process for preparing an integrated SBD structure silicon carbide MOSFET, as shown in fig. 5 to 12, which is characterized in that the process for preparing an integrated SBD structure silicon carbide MOSFET according to embodiment one comprises:

S1, preparing a basal layer of a silicon carbide MOSFET;

Preparing a substrate layer of the silicon carbide MOSFET is the basis of the whole process flow; this step involves selecting a suitable silicon carbide material and forming a base layer that not only provides physical support for the various cells and structures that follow, but also its chemical purity and crystal structure quality directly affect the performance of the overall device. The preparation of the base layer typically involves high temperature, high purity silicon carbide crystal growth techniques such as Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), etc., to ensure that silicon carbide wafers suitable for high performance MOSFET fabrication are obtained.

S2, forming a PN structure part 130 on the basal layer through a high-temperature ion implantation doping process;

The PN structure 130 is formed on the base layer by a high temperature ion implantation doping process, which is a key to constructing a PN junction that is critical in the MOSFET. The ion implantation technique can precisely control the type and concentration of the dopant in a specific region of the silicon carbide substrate, thereby forming a P region and an N region. This step requires precise control because the doping level and depth will directly affect the threshold voltage, current carrying capability and switching speed of the device. The high temperature ion implantation ensures that the dopant atoms can fully enter the crystal lattice and activate to form a stable PN structure.

S3, sequentially preparing and forming two gate structures 110 which are arranged at intervals on the substrate layer through deposition and photoetching;

The formation of two spaced gate structures 110 on a substrate layer by deposition and lithography in sequence involves complex micromachining techniques. The gate is a critical element in a MOSFET to control the flow of current, so its precise fabrication is critical. A fine gate pattern may be formed on the substrate layer by depositing a gate material (e.g., metal or polysilicon) and subsequent photolithographic processes. The photolithography step involves applying a photoresist to the material surface, transferring the gate pattern by mask exposure and development, and eventually forming a plurality of precisely positioned, spaced gate structures 110 that provide the device with voltage control channels.

S4, etching an SBD trench 120 on the surface of the substrate layer between the two gate structures 110, and integrating the silicon carbide SBD cell 200 in the SBD trench 120 by deposition and lithography.

Etching the SBD trench 120 at the surface of the substrate layer between the two gate structures 110, integrating the silicon carbide SBD cell 200 within the SBD trench 120 by deposition and lithography is a critical step in achieving MOSFET and SBD integration. By means of sophisticated etching techniques, a trench is formed in the region between the two gates, which provides physical space for the integrated SBD cell. Subsequently, SBD structures are formed inside these trenches by deposition and photolithographic techniques, and these SBD cells are tightly integrated with the MOSFETs, achieving a synergistic interaction of the two. By the method, the SBD cell can take the role of a freewheeling diode when the MOSFET is turned off, so that forward voltage drop is effectively reduced, and the performance and efficiency of the whole device are improved.

The working principle of the preparation process is as follows: firstly, preparing a substrate layer of a silicon carbide MOSFET, and forming a PN structure part 130 on the substrate layer through a high-temperature ion implantation doping process; next, two gate structures 110 disposed at intervals are sequentially formed on the base layer by deposition and photolithography, the SBD trench 120 is etched out at the surface of the base layer between the two gate structures 110, and the SBD is functionally integrated into the MOSFET by depositing and lithographically integrating the silicon carbide SBD cells 200 within the SBD trench 120.

The beneficial effects are that: the preparation process ensures the accurate formation of the PN structure part 130 and the grid electrode structure 110 through the ion implantation and photoetching technology with accurate control, thereby ensuring the high performance and the high reliability of the silicon carbide MOSFET, the accurate control capability is provided for the device through the fine preparation of the grid electrode structure 110, the forward voltage drop of the device is reduced, the efficiency is improved, and the switching performance of the device is optimized through the reduction of parasitic capacitance and inductance through the innovative integrated design of the SBD groove 120. Overall, this process flow allows for a high integration of silicon carbide MOSFETs with SBDs, providing an efficient method of making efficient, compact and reliable power electronics.

In addition, as shown in fig. 13, in order to integrate the SBD and MOSFET structure according to the present embodiment, compared with the comparison of the reverse recovery characteristics of the body diode of the conventional silicon carbide MOSFET, the product according to the present embodiment is significantly better than the conventional silicon carbide MOSFET in the reverse recovery characteristics of the body diode.

In this embodiment, it is specifically described that step S1 specifically includes:

A SiC substrate 101 is provided and a SiC epitaxial layer 102 is epitaxially grown on the SiC substrate 101 to produce a base layer for preparing a silicon carbide MOSFET.

A SiC substrate 101 is provided and a SiC epitaxial layer 102 is epitaxially grown on the SiC substrate 101 to produce a base layer for preparing a silicon carbide MOSFET, which is the basis for manufacturing a high quality silicon carbide MOSFET. First, a high purity SiC substrate 101 is selected as a starting point, which provides a stable and reliable basis for subsequent epitaxial growth. Epitaxial growth is a process of adding additional layers of material to a substrate, typically by Chemical Vapor Deposition (CVD) or the like. In this process, the thickness, doping type, and concentration of SiC epitaxial layer 102 can be very precisely controlled, which is critical to tuning and optimizing the electrical performance of the device.

In this embodiment, it is specifically described that step S2 specifically includes:

S21, depositing a first hard mask masking layer 301 on the substrate layer, and photoetching a first hollow area 302 capable of exposing the surface of the substrate layer on the first hard mask masking layer 301;

A first hard mask masking layer 301 is deposited on the substrate layer, and a first hollowed-out area 302 capable of exposing the surface of the substrate layer is formed on the first hard mask masking layer 301 by lithography, wherein the steps mainly involve the preparation and lithography process of the hard mask masking layer.

It should be noted that, the hard mask is generally made of a material with high temperature resistance and stable chemical properties, and can play a role in protecting the subsequent ion implantation process; the location and shape of the future P-well layer 103 can be precisely defined by forming a relief region on the hard mask by photolithographic techniques. The accuracy of this process is critical to the subsequent ion implantation step, which directly determines the boundaries and geometry of the doped regions.

S22, injecting high-temperature ions of the P well into the first hard mask masking layer 301 to prepare a P well layer 103 corresponding to the first hollowed-out area 302 on the surface of the substrate layer;

The first hard mask masking layer 301 is implanted with P-well high-temperature ions to prepare the P-well layer 103 corresponding to the first hollowed-out area 302 on the surface of the substrate layer, which is the core in the preparation process of the PN structure portion 130. High-temperature P type ion implantation is performed on the exposed substrate layer surface of the first hollow area 302 to form a P well layer 103 on the substrate layer surface, and the high-temperature ion implantation can ensure that ions penetrate deep into the SiC material and promote the activation of the ions in the SiC crystal lattice to form an effective doped region. Precise control of this step is critical to achieving high performance MOSFETs because the electrical characteristics of the P-well layer 103 will affect the device's threshold voltage, switching performance, and leakage current parameters.

S23, removing the first hard mask masking layer 301;

The hard mask masking layer used in the previous step is removed in preparation for subsequent processing steps, such as application of a new masking layer or other surface treatment. The removal of the hard mask requires the use of specific chemical or physical methods to ensure that the surface of the substrate layer is not damaged while leaving no residue. This process plays an important role in maintaining the cleanliness and integrity of the substrate layer, which is the basis for the successful performance of subsequent steps.

S24, depositing a second hard mask masking layer 303 on the substrate layer, and photoetching a second hollowed-out area 304 which can expose the surface of the substrate layer on the second hard mask masking layer 303;

This step marks the next stage in the preparation of the PN structure, where a second hard mask masking layer 303 is deposited and a second hollowed-out region 304 is formed thereon by a photolithographic process, the purpose of this step being to prepare for the subsequent formation of N-type or other type doped regions. Similar to the previous steps, the photolithographic accuracy here directly affects the accuracy of the subsequently doped regions and the overall performance of the device. By precisely controlling the position and the size of the hollowed-out area, the doped region can be ensured to be strictly matched with the design requirement.

S25, injecting N+ high-temperature ions into the second hard mask masking layer 303 to prepare an N-type heavily doped layer 104 corresponding to the second hollowed-out area 304 on the surface of the substrate layer; the P-type heavily doped layer is positioned in the middle of the P-well layer 103;

N-type doping is performed on the substrate layer protected by the hard mask. Through high temperature ion implantation, n+ dopant ions can be precisely implanted into the substrate layer exposed by the second hollowed-out region 304, thereby forming the N-type heavily doped layer 104. This layer is typically used to construct high concentration doped regions such as source and drain, which is a key element in MOSFET design for achieving fast switching and low resistance channels.

S26, removing the second hard mask masking layer 303;

the hard mask layer for the N + doping step is intended to be removed. Removal of the hard mask layer is required to ensure that no damage is done to the underlying substrate layer and the newly formed doped regions.

S27, depositing a third hard mask masking layer 305 on the substrate layer, and photoetching a third hollowed-out area 306 which can expose the surface of the substrate layer on the third hard mask masking layer 305;

the following p+ doping process. Depositing and lithographically masking the third hard mask layer 305 to form a new hollowed-out region to be used to form a P-type heavily doped layer; the precise photolithography process is critical to ensure that the size and location of the doped regions meet design requirements.

S28, injecting P+ high-temperature ions into the third hard mask masking layer 305 to prepare a P-type heavily doped layer corresponding to the third hollowed-out area 306 on the surface of the substrate layer; the P-type heavily doped layer is positioned at one side part of the P-well layer 103;

The PN structure is further adjusted and optimized. By implanting p+ ions into the specific hollowed-out region, a P-type heavily doped layer is formed, which is generally to construct a source portion to achieve a lower contact resistance. The p+ region is a highly doped region here, which plays a critical role in the overall MOSFET operating characteristics.

S29, the third hard mask masking layer 305 is removed.

The third hard mask masking layer 305 for the P + doping process is removed. This process requires a clean, planar surface to be provided for subsequent processing steps.

In this embodiment, it is specifically described that step S3 specifically includes:

s31, forming a gate oxide layer 106 on the surface of the substrate layer through gate oxidation and post annealing;

Forming a gate oxide layer 106 on the surface of the SiC substrate layer, typically by exposing the material to an oxidizing environment and annealing; such a gate oxide 106 acts primarily as an insulator, preventing current flow directly from the gate to the silicon substrate, while allowing electron flow in the channel to be controlled by electric field effects. The quality of the gate oxide 106 directly affects the performance of the MOSFET, such as threshold voltage, leakage current, etc.

S32, forming a gate electrode 107 on the gate oxide layer 106 through a polycrystalline deposition level;

A gate electrode 107 is formed on the gate oxide 106 by depositing polysilicon or a metal material, which electrode is responsible for applying a voltage to the gate oxide 106, thereby controlling the electron flow in the underlying silicon channel. The material and structural design of the gate electrode 107 has a significant impact on both the switching characteristics and the power consumption of the MOSFET.

S33, photoetching and etching the gate oxide layer 106 and the gate electrode 107 to form two gate islands arranged at intervals;

A gate structure 110 is formed over the gate oxide 106 and gate electrode 107, during which the shape and size of the gates, and their location on the substrate layer, are precisely defined by using masking and etching techniques. The formed gate islands will be used throughout the MOSFET to control the on and off states of the device.

S34, depositing a dielectric layer on the basal layer to form a grid dielectric structure coated on the two grid islands;

the gate dielectric junction herein refers to forming a dielectric layer around the gate island; this dielectric layer, which is typically comprised of silicon dioxide or other insulating material, is used to protect the gate structure 110 and may help reduce leakage current and parasitic capacitance of the device, the presence of which is important to improve the overall performance and reliability of the MOSFET.

And S35, carrying out photoetching and etching on the middle part of the gate dielectric structure to form a gate groove 307, so as to prepare and form two gate structures 110 which are arranged at intervals.

This process involves further photolithography and etching on the gate dielectric layer 108 to form gate trenches 307, which gate trenches 307 are part of the MOSFET gate structure 110, which is critical to ensure effective control of the gate and accurate operation of the device. By precisely controlling the shape and position of the gate trench 307, the electrical characteristics of the device, such as threshold voltage and switching speed, can be further optimized.

In this embodiment, it is specifically described that step S4 specifically includes:

S41, etching an SBD groove 120 on the surface of the basal layer along the position of the grid groove 307;

this step involves forming SBD trenches 120 in the surface of a silicon carbon (SiC) substrate layer at specific locations, immediately adjacent to the gate trenches 307, by etching techniques. This trench will be used for the subsequent SBD cell integration, and will serve as a key part in the device structure to introduce SBD, which can reduce power consumption and provide good reverse recovery characteristics.

S42, photoetching a lead hole in the SBD groove 120;

The function of the lead holes is to create locations in the SBD structure reserved for electrode soldering or connecting wires, which is critical for subsequent device packaging and connection to external circuitry; this step ensures the control and consistency of the electrical connection, a detailed feature of the device integration.

S43, the silicon carbide SBD cells 200 are integrated in the SBD trenches 120 by SBD barrier metal sputtering and lithography in the SBD trenches 120.

Wherein a barrier metal material of the SBD is deposited inside the SBD trench 120 by a sputtering technique, and then the shape and position of the SBD cell are precisely defined by a photolithography process; these silicon carbide SBD cells 200 combine with the silicon carbide material of the base layer to form a barrier diode. This integrated SBD is responsible for providing a lower forward voltage drop and fast switching behavior when the device is turned off, thereby improving the efficiency of the overall MOSFET.

In this embodiment, it is further explained that step S4 further includes:

and S5, performing source metal sputtering and photoetching on the substrate layer to deposit a source metal layer 109 coated on the gate structure 110 on the surface of the substrate layer.

The pattern and position of the source is then defined by sputtering a metal material, which will directly connect to the previously fabricated P-type and N-type heavily doped layers 104, using photolithographic techniques. The quality and bonding density of the source metal layer 109 are critical to the conductivity and reliability of the device, especially in high power applications, the on-resistance of the device can be reduced and the power conversion efficiency can be improved by the optimized configuration of the source metal layer 109.

The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A LVFF silicon carbide field effect transistor, comprising a silicon carbide MOSFET cell (100) and a silicon carbide SBD cell (200);

the silicon carbide MOSFET cell (100) comprises a SiC epitaxial layer (102), a grid structure (110) is arranged on the first surface of the SiC epitaxial layer (102), an SBD groove (120) is arranged at a preset position of a non-grid region on the first surface of the SiC epitaxial layer (102), and the silicon carbide SBD cell (200) is integrated in the SBD groove (120) or the non-grid region on the first surface.

2. The LVFF silicon carbide field effect tube as claimed in claim 1, wherein,

The silicon carbide MOSFET cell (100) further comprises a SiC substrate (101) and a source metal layer (109), wherein the second surface of the SiC substrate (101) is laminated on the SiC epitaxial layer (102);

The source metal layer (109) is deposited on the first surface of the SiC epitaxial layer (102), and the source metal layer (109) is deposited to cover the gate structure (110) and the silicon carbide SBD cell (200);

The first surface of the SiC epitaxial layer (102) is further provided with a PN structure portion (130), and the PN structure portion (130) comprises a P-well layer (103), an N-type heavily doped layer (104) and a source P-type heavily doped layer (105) which are sequentially arranged.

3. The LVFF silicon carbide field effect tube as claimed in claim 1, wherein,

Two gate structures (110) are arranged on the first surface of the SiC epitaxial layer (102), and the SBD groove (120) is formed between the two gate structures (110).

4. The LVFF silicon carbide field effect tube according to claim 1, wherein the gate structure (110) comprises a gate oxide layer (106) laminated on the first surface of the SiC epitaxial layer (102), the gate oxide layer (106) having a gate electrode (107) laminated thereon;

And a gate dielectric layer (108) is arranged outside the gate oxide layer (106) and the gate electrode (107).

5. A process for preparing a LVFF silicon carbide field effect transistor, which is used for preparing a LVFF silicon carbide field effect transistor according to any one of claims 1 to 4, the process comprising:

Preparing a substrate layer of a silicon carbide MOSFET;

Forming a PN structure part (130) on the substrate layer through a high-temperature ion implantation doping process;

sequentially preparing and forming two grid structures (110) which are arranged at intervals on the substrate layer through deposition and photoetching;

-etching an SBD trench (120) in the surface of the substrate layer between two gate structures (110), -integrating a silicon carbide SBD cell (200) within the SBD trench (120) by deposition and lithography.

6. The process for fabricating a LVFF silicon carbide field effect transistor according to claim 5, wherein the base layer of the silicon carbide MOSFET is fabricated; the method specifically comprises the following steps:

providing a SiC substrate (101), and epitaxially growing a SiC epitaxial layer (102) on the SiC substrate (101) to obtain the base layer for preparing the silicon carbide MOSFET.

7. The process for fabricating a LVFF silicon carbide field effect tube according to claim 5, wherein a PN structure portion (130) is formed on the base layer by a high-temperature ion implantation doping process; the method specifically comprises the following steps:

depositing a first hard mask masking layer (301) on the substrate layer, and photoetching a first hollow area (302) capable of exposing the surface of the substrate layer on the first hard mask masking layer (301);

Implanting high-temperature ions of a P well into the first hard mask masking layer (301) to prepare a P well layer (103) corresponding to the first hollowed-out area (302) on the surface of the substrate layer;

removing the first hard mask masking layer (301);

Depositing a second hard mask masking layer (303) on the substrate layer, and photoetching a second hollow area (304) capable of exposing the surface of the substrate layer on the second hard mask masking layer (303);

Injecting N+ high-temperature ions into the second hard mask masking layer (303) to prepare an N-type heavily doped layer (104) corresponding to the second hollow area (304) on the surface of the basal layer; the P-type heavily doped layer is positioned in the middle of the P-well layer (103);

-removing the second hard mask masking layer (303);

Depositing a third hard mask masking layer (305) on the substrate layer, and photoetching a third hollow area (306) capable of exposing the surface of the substrate layer on the third hard mask masking layer (305);

Injecting P+ high-temperature ions into the third hard mask masking layer (305) to prepare a P-type heavily doped layer corresponding to the third hollow area (306) on the surface of the substrate layer; the P-type heavily doped layer is positioned at one side part of the P-well layer (103);

the third hard mask masking layer (305) is removed.

8. The process for fabricating a LVFF silicon carbide field effect transistor according to claim 5, wherein the forming of two spaced apart gate structures (110) is performed sequentially by deposition and photolithography on the substrate layer; the method specifically comprises the following steps:

Forming a gate oxide layer (106) on the surface of the substrate layer through gate oxidation and post annealing;

forming a gate electrode (107) on the gate oxide layer (106) by a polycrystalline deposition level;

photoetching and etching the gate oxide layer (106) and the gate electrode (107) to form two gate islands which are arranged at intervals;

Forming a grid dielectric structure coated on the two grid islands through dielectric layer deposition on the substrate layer;

and photoetching and etching a grid groove body (307) in the middle of the grid dielectric structure to prepare and form two grid structures (110) which are arranged at intervals.

9. The process for fabricating a LVFF silicon carbide field effect transistor according to claim 8, wherein the surface of the substrate layer between the two gate structures (110) is etched with SBD trenches (120), and the silicon carbide SBD cells (200) are integrated within the SBD trenches (120) by deposition and lithography; the method specifically comprises the following steps:

etching an SBD trench (120) on the surface of the base layer along the location of the gate trench (307);

photoetching a lead hole in the SBD groove (120);

a silicon carbide SBD cell (200) is integrated within the SBD trench (120) by SBD barrier metal sputtering and lithography within the SBD trench (120).

10. The process for fabricating a LVFF silicon carbide field effect transistor according to claim 5, wherein the integration of the silicon carbide SBD cells (200) within the SBD trenches (120) by deposition and lithography is further followed by:

Source metal sputtering and photolithography are performed on the substrate layer to deposit a source metal layer (109) coating the gate structure (110) on the surface of the substrate layer.