CN115579399A - Silicon carbide MOSFET cell layout structure - Google Patents
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Abstract
The application provides a silicon carbide MOSFET cell layout structure. The structure comprises an SBD and four octagonal silicon carbide MOSFET cell structures, the proportion of the bevel edge of each octagonal silicon carbide MOSFET cell structure is changed to adjust the proportion of the middle square cavity area and the cell layout of each octagonal silicon carbide MOSFET cell structure, and the SBD is arranged to be the same as the middle square cavity area. The P + region connected with the source electrode metal can shield a gate oxide electric field of a partial separation gate structure, reliability is improved, SBD is integrated in the central region formed by the octagonal staggered arrangement structure, structure layout is simple, and process is simple.
Description
Technical Field
The application relates to the technical field of semiconductor devices, in particular to a silicon carbide MOSFET cellular layout structure.
Background
Silicon carbide MOSFET devices are gradually replacing silicon-based IGBT devices in many high-power converter application scenarios due to their lower power consumption and higher switching frequency. The conventional silicon carbide power MOSFET cell comprises a drain, a source, a first isolated gate region, a substrate, a first N-type silicon carbide region, a first source region, and a JFET region. The first N-type silicon carbide region has a first N-type doping concentration, is positioned above the substrate and is provided with a first surface; the substrate has a second surface. The JFET area is adjacent to or positioned in the first N-type silicon carbide area; the first source electrode region is positioned above the first N-type silicon carbide region and on two sides of the JFET region, the first source electrode region comprises a second N-type silicon carbide region, a first P-type body region and a second P-type body region, the second N-type silicon carbide region has second N-type doping concentration, the second N-type doping concentration can be larger than the first N-type doping concentration, the first P-type body region has first P-type doping concentration, the second P-type body region has second P-type doping concentration, and the second P-type doping concentration can be larger than the first P-type doping concentration; the first isolation gate region is positioned above the JFET region and the first source electrode region and comprises a gate oxide layer, a gate electrode layer and a passivation layer; the source includes a first metallization layer extending over the first surface and in direct contact with the first source region forming an ohmic contact at an interface location. The drain includes a second metallization layer extending below the second surface and forming an ohmic contact with the substrate at an interface location.
Because the characteristic degradation problem of a body diode of the traditional MOSFET device during the third quadrant operation exists, when the power silicon carbide MOSFET is applied to a high-power converter, a freewheeling diode is required to be connected in parallel to provide a current path when the MOS is switched off. However, the Schottky Barrier Diode SBD (Schottky Barrier Diode) is externally connected in reverse parallel by stacking hardware, which increases the circuit scale and system cost, reduces the integration level, and introduces more parasitic capacitance and inductance.
Disclosure of Invention
In order to solve the technical problem, the invention provides a silicon carbide MOSFET cell layout structure, the SBD is integrated through a central area formed by an octagonal staggered structure, a P + type source area connected with source metal can shield a part of gate oxide electric field of a separation gate structure, the structure layout is simple, and the structure reliability is improved.
The technical scheme adopted by the invention is as follows:
a silicon carbide MOSFET cell layout structure comprises an SBD and four octagonal silicon carbide MOSFET cell structures;
the bevel edges of the four octagonal silicon carbide MOSFET cell structures are arranged in a butt joint array mode to form a middle square hollow area;
the SBD is arranged in the middle square cavity area, and the middle square cavity area where the SBD is located is in contact with the bevel edges of the octagonal silicon carbide MOSFET cell structures.
Furthermore, four connection structure of octagon silicon carbide MOSFET cell structure includes normal grid structure and splits the grid structure, the square cavity region in middle that the SBD belongs to is for splitting the grid structure, the square cavity region in middle that the SBD belongs to and four the hypotenuse area of mutual contact of octagon silicon carbide MOSFET cell structure is normal grid structure.
Further, four of the octagonal silicon carbide MOSFET cell structures each include:
an N-type silicon carbide substrate;
a first source metal in ohmic contact with the N-type silicon carbide substrate;
the N-type drift region is formed by epitaxial growth of the N-type silicon carbide substrate, a first source region, a second source region and a JFET region are arranged in the surface of the N-type drift region at the top of an epitaxial layer along the epitaxial growth direction, the first source region comprises a P-Body region, a first P + type source region and an N + type source region, the P-Body region, the first P + type source region and the N + type source region are adjacent and located on the P-Body region, and the N + type source region is closer to the JFET region than the first P + type source region; the second source electrode region is a second P + type source region, and the JFET region is positioned between the first source electrode region and the second source electrode region;
preparing an isolation gate region on the N-type drift region, wherein the isolation gate region is in ohmic contact with the N-type drift region and comprises a POLY region, and a gate oxide layer wraps the surface of the POLY region;
and growing a second source metal on the N-type drift region and the isolation gate region, wherein the second source metal is in ohmic contact with the N-type drift region.
Further, each of the four octagonal silicon carbide MOSFET cell structures shares one of the N-type drift region and junction termination with the SBD.
Further, the substrate concentration of the N-type silicon carbide substrate is 1e19 to 1e21cm -3 The substrate thickness of the N-type silicon carbide substrate is 100 to 500 mu m.
Further, the ion implantation dosage of the P-Body region is 1e13 to 1e15cm -2 The injection energy is 50 to 400KeV, the junction depth is 0.6 to 1.2 mu m, and the concentration range of the formed P-Body area is 5e16 to 5e18cm -3 。
Further, the ion implantation dosage of the P + type source region is 1e14 to 1e116cm -2 The injection energy is 50 to 300KeV, the junction depth is 0.2 to 0.8 mu m, and the doping concentration range of the formed P + type source region is 5e18 to 1e20cm -3 。
Furthermore, the ion implantation dosage of the N + type source region is 1e14 to 1e116cm -2 The implantation energy is 50-300KeV, the junction depth is 0.2-0.8 mu m, and the doping concentration range of the formed N + type source region is 5 e18-1e20cm -3 。
Furthermore, the ion implantation dosage of the JFET region is 1e11-1e14cm -2 The injection energy is 20 to 300KeV, the junction depth is 0.1 to 0.8 mu m, and the doping concentration range of the formed JFET area is 1e16 to 1e18cm -3 。
A manufacturing method of the silicon carbide MOSFET cellular layout structure is characterized by comprising the following steps:
and 5, growing drain metal below the N-type silicon carbide substrate.
Through the embodiment of the application, the following technical effects can be obtained:
the central area formed by the octagonal staggered structure is used for integrating the SBD, the structural layout is simple, and the process is simple. The partial split gate structure can reduce gate leakage capacitance, but can also lead to the gate oxide electric field of the device split position to be too high, and the P + type source region connected with the source metal in the application can shield the gate oxide electric field of the partial split gate structure, so that the reliability is improved. The reason for selecting the octagon is that only the octagon is arranged in a staggered manner to form a square area for integrating the SBD in the middle, and the optimal SBD intracellular integration can be realized without additional complex layout.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to the drawings without inventive labor.
FIG. 1 is a schematic diagram of a silicon carbide MOSFET cell layout;
FIG. 2 is another schematic diagram of a silicon carbide MOSFET cell layout;
FIG. 3 is a cross-sectional view of a chip structure;
fig. 4 (a) to 4 (n) are schematic structural diagrams of intermediate products of the steps of the method of the present application.
Reference numerals:
1P + type source region, 2N + type source region, 3P-Body region, 4 contact window.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making creative efforts shall fall within the protection scope of the present application.
Fig. 1 and 2 respectively show overall schematic diagrams of layout structures of two SBD-integrated octagonal silicon carbide MOSFET cells. As shown in fig. 1, the layout structure of the integrated SBD octagonal silicon carbide MOSFET cell structure comprises an SBD and four octagonal silicon carbide MOSFET cell structures, wherein the oblique sides of the four octagonal silicon carbide MOSFET cell structures are arranged in a butt-joint array manner to form a middle square hollow area, the SBD is arranged in the middle square hollow area, and the SBD and the oblique sides of the octagonal silicon carbide MOSFET cell structures are in contact with each other.
The connection structure of the four octagonal silicon carbide MOSFET cell structures comprises a normal grid structure and a split grid structure, a square hollow area in the middle of the SBD is of the split grid structure, and the oblique side mutual contact area of the SBD and the four octagonal silicon carbide MOSFET cell structures is of the normal grid structure. The four octagonal silicon carbide MOSFET cell structures each include:
an N-type silicon carbide substrate;
a first source metal in ohmic contact with the N-type silicon carbide substrate;
the N-type drift region is formed by epitaxial growth of an N-type silicon carbide substrate, a first source region, a second source region and a JFET region are arranged in the surface of the N-type drift region at one end along the epitaxial growth direction, the first source region comprises a P-Body region, a first P + type source region and an N + type source region, the P-Body region, the first P + type source region and the N + type source region are adjacent and located on the P-Body region, and the N + type source region is closer to the JFET region than the first P + type source region; the second source region is a second P + type source region, and the JFET region is located between the first source region and the second source region.
Preparing an isolation gate region on the N-type drift region, wherein the isolation gate region is in ohmic contact with the N-type drift region and comprises a POLY region, and a gate oxide layer wraps the surface of the POLY region; and growing a second source metal on the N-type drift region and the isolation gate region, wherein the second source metal is in ohmic contact with the N-type drift region. Each of the four octagonal silicon carbide MOSFET cell structures uses one N-type drift region and junction termination in conjunction with the SBD.
The substrate concentration of the N-type silicon carbide substrate is 1e19 to 1e21cm -3 The thickness of the substrate of the N-type silicon carbide substrate is 100 to 500 mu m. The ion implantation dosage of the P-Body area is 1e13 to 1e15cm -2 The injection energy is 50 to 400KeV, the junction depth is 0.6 to 1.2 mu m, and the concentration range of the formed P-Body area is 5e16 to 5e18cm -3 . The ion implantation dosage of the first P + type source region and the second P + type source region is 1e14 to 1e16cm -2 The implantation energy is 50-300KeV, the junction depth is 0.2-0.8 mu m, and the doping concentration range of the formed P + type source region is 5-18-1e20cm -3 . The ion implantation dosage of the N + type source region is 1e14 to 1e116cm -2 The implantation energy is 50-300KeV, the junction depth is 0.2-0.8 mu m, and the doping concentration range of the formed N + type source region is 5-18-1e20cm -3 . The ion implantation dosage of the JFET region is 1e11 to 1e14cm -2 The injection energy is 20 to 300KeV, the junction depth is 0.1 to 0.8 mu m, and the doping concentration range of the formed JFET area is 1e16 to 1e18cm -3 。
The difference between the cell layout structures in fig. 1 and fig. 2 is only that the area ratio of the middle square SBD is different, which is used to indicate that the area ratio of the middle SBD can be adjusted by adjusting the proportion of the straight sides of the hypotenuses of the octagon, thereby realizing the flexibility of adjustment. Fig. 3 is a cross-sectional view of a chip structure.
The manufacturing method of the octagonal silicon carbide MOSFET cell layout structure comprises the following steps, and the structural schematic diagram of the intermediate product of each step is shown in FIGS. 4 (a) to 4 (n):
the concentration of the N-type silicon carbide substrate is 1e19 to 1e21cm -3 The substrate thickness was 100 to 500 μm, as shown in FIG. 4 (a). Growing an N-drift region N-drift on an epitaxial layer of an N-type silicon carbide substrate, wherein the thickness of the epitaxial layer is 5 to 50 mu m, and the doping concentration is 1e15 to 1e17 cm -3 As shown in fig. 4 (b).
in the steps, P-Body regions are ion-implanted to form symmetrical P-Body regions on the left side and the right side of the N-drift region N-drift, and the implantation dosage is 1e13 to 1e15cm -2 The injection energy is 50 to 400KeV, the junction depth is 0.6 to 1.2 mu m, and the concentration range of the formed P-Body doped region is 5e16 to 5e18cm -3 As shown in fig. 4 (c). A mask is shared, P + region ions are implanted into a region between the two SBDs and the P-Body region and a region close to the edge inside the P-Body region, and the implantation dosage of the P + region ions is 1e14 to 1e16cm -2 The implantation energy is 40-300KeV, the junction depth is 0.1-0.8 mu m, and the doping concentration ranges of the first P + type source region and the second P + type source region are 5 e18-1e20cm -3 As shown in fig. 4 (d). Injecting N + region ions in the P-Body region close to the first P + type source region, wherein the injection dosage of the N + region ions is 1e14 to 1e16cm -2 The implantation energy is 50-300KeV, the junction depth is 0.2-0.8 mu m, and the doping concentration range of the formed N + type source region is 5 e18-1e20cm -3 As shown in fig. 4 (e). Injecting JFET region ions between the first P + type source region and the P-Body region, wherein the injection dosage of the JFET region ions is 1e11-1e14cm -2 The implantation energy is 20 to 300KeV, the junction depth is 0.1 to 0.8 mu m, and the doping concentration range of the formed N + type source region is 1e16 to 1e18cm -3 As shown in fig. 4 (f). Annealing the carbon film, activating implanted ions, and depositing the carbon film with the thickness of 0.1 to 2.0 mu m, the annealing temperature of 1000 to 2000 ℃, the annealing time of 0.1 to 1h, wherein as shown in figure 4 (g), the carbon film is etched by oxygen field deposition, and the thickness of the oxygen field is 0.5 to 4 mu m.
in the step 3, a gate Oxide area is grown above the N + type source area, the JFET area and the P-body area, the growth temperature of the gate Oxide area is 1000-1500 ℃, the growth time is 0.5-4 h, the growth environment is dry oxygen/air/water vapor, and the thickness of the gate Oxide layer after growth is 0.3-0.8 mu m, as shown in figure 4 (h). And (3) performing deposition etching on the gate oxide region to form a polysilicon gate Poly region, wherein the deposition thickness of the polysilicon in the polysilicon gate Poly region is 0.5-3.0 μm, as shown in fig. 4 (i). And (5) carrying out deposition and etching on the insulating layer to form a gate Oxide area which surrounds the polycrystalline silicon gate electrode Poly area, wherein the deposition thickness of the gate Oxide area is 0.5-3.0 mu m, as shown in figure 4 (j).
And (5) carrying out Ohmic contact open-hole metal sputtering to form an Ohmic region, wherein the sputtering metal is Ti/Ni, and the thickness of the Ohmic region is 0.05-0.5 mu m, as shown in figure 4 (k). And (3) performing Schottky contact metal sputtering to form a Schottky contact Schottky region above the SBD structure, wherein the sputtering metal is Ti/Ni/W/Pt, the sputtering thickness is 0.05-0.5 mu m, and the annealing temperature is 1000-2000 ℃, as shown in figure 4 (l).
in the step 4, a gate contact hole is opened, metal deposition and etching are performed to form a source Metal area at the top of the chip, the Metal area is used as source Metal, and the Metal thickness is 0.5 to 5.0 μm, as shown in fig. 4 (m).
And 5, growing drain metal below the N-type silicon carbide substrate.
And carrying out back ohmic contact and Metal deposition to form a drain Metal area at the bottom of the chip, wherein the Metal area is used as drain Metal, and the thickness of the Metal is 0.5-5.0 mu m, as shown in figure 4 (n).
To sum up, this application is through new cellular structure design, with inside the integrated silicon carbide MOSFET device of SBD, not only can reduce the encapsulation cost of device, improves the device integration level, can also avoid extra parasitic effect. In addition, in the silicon carbide MOSFET structure of the integrated SBD, the silicon carbide MOSFET and the SBD share a drift region and a junction terminal, thereby further reducing the chip area. Studies have shown that inserting SBDs uniformly into each sic MOSFET cell allows the SBD to operate at maximum current, without the body diode conducting, and therefore, intra-cell integration is more advantageous than extra-cell integration. In addition, compared with a split source structure, the split gate structure reduces the area of gate leakage, reduces the capacitance of the gate leakage, can improve the switching speed and reduces the power consumption of the switch.
Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention. It can be clearly understood by those skilled in the art that, for convenience and simplicity of description, the specific working process of the apparatus and the device described above may refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of modules or components may be combined or integrated into another system, or some features may be omitted, or not executed.
The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.
In addition, each functional module in the embodiments of the present invention may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module. The foregoing description is only exemplary of the preferred embodiments of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
It should be understood that the order of execution of the steps in the summary of the invention and the embodiments of the present invention does not absolutely imply any order of execution, and the order of execution of the steps should be determined by their functions and inherent logic, and should not be construed as limiting the process of the embodiments of the present invention.
Claims (10)
1. A layout structure of silicon carbide MOSFET cells is characterized in that the structure comprises an SBD and four octagonal silicon carbide MOSFET cell structures;
the bevel edges of the four octagonal silicon carbide MOSFET cell structures are arranged in a butt joint array mode to form a middle square hollow area;
the SBD is arranged in the middle square hollow area, and the middle square hollow area where the SBD is arranged is in contact with the bevel edges of the octagonal silicon carbide MOSFET unit cell structures.
2. The silicon carbide MOSFET cell layout structure according to claim 1, wherein the connection structure of the four octagonal silicon carbide MOSFET cell structures includes a normal gate structure and a split gate structure, the middle square hole region where the SBD is located is the split gate structure, and the middle square hole region where the SBD is located and the oblique side mutual contact region of the four octagonal silicon carbide MOSFET cell structures are both the normal gate structure.
3. The silicon carbide MOSFET cell layout structure of claim 2, wherein each of the four octagonal silicon carbide MOSFET cell structures comprises:
an N-type silicon carbide substrate;
a first source metal in ohmic contact with the N-type silicon carbide substrate;
the N-type drift region is formed by epitaxial growth of the N-type silicon carbide substrate, a first source region, a second source region and a JFET region are arranged on the top of the epitaxial layer along the epitaxial growth direction, the surface of the N-type drift region is internally provided with the first source region, the second source region and the JFET region, the first source region comprises a P-Body region, a first P + type source region and an N + type source region, the P-Body region, the first P + type source region and the N + type source region are adjacent and located on the P-Body region, and the N + type source region is closer to the JFET region than the first P + type source region; the second source electrode region is a second P + type source electrode region, and the JFET region is positioned between the first source electrode region and the second source electrode region;
preparing an isolation gate region on the N-type drift region, wherein the isolation gate region is in ohmic contact with the N-type drift region and comprises a POLY region, and a gate oxide layer wraps the surface of the POLY region;
and growing a second source metal on the N-type drift region and the isolation gate region, wherein the second source metal is in ohmic contact with the N-type drift region.
4. The silicon carbide MOSFET cell layout structure of claim 3, wherein each of the four octagonal silicon carbide MOSFET cell structures share one of the N-type drift region and junction termination with the SBD.
5. The silicon carbide MOSFET cell layout structure as claimed in claim 4, wherein the substrate concentration of the N-type silicon carbide substrate is 1e19 to 1e21cm -3 The thickness of the N-type silicon carbide substrate is 100 to 500 mu m.
6. The layout structure of the SiC MOSFET cell of claim 4, wherein the P-Body region is an ion implantThe amount is 1e13 to 1e15cm -2 The injection energy is 50 to 400KeV, the knot depth is 0.6 to 1.2 mu m, and the concentration range of the formed P-Body area is 5e16 to 5e18cm -3 。
7. The layout structure of the SiC MOSFET cell of claim 4, wherein the ion implantation dose of the P + type source region is 1e14 to 1e116cm -2 The implantation energy is 50-300KeV, the junction depth is 0.2-0.8 mu m, and the doping concentration range of the formed P + type source region is 5 e18-1e20cm -3 。
8. The layout structure of the SiC MOSFET cell of claim 4, wherein the ion implantation dose of the N + type source region is 1e14 to 1e116cm -2 The implantation energy is 50-300KeV, the junction depth is 0.2-0.8 mu m, and the doping concentration range of the formed N + type source region is 5 e18-1e20cm -3 。
9. The layout structure of the SiC MOSFET cell according to claim 4, wherein the ion implantation dose of the JFET region is 1e11 to 1e14cm -2 The injection energy is 20 to 300KeV, the junction depth is 0.1 to 0.8 mu m, and the doping concentration range of the formed JFET area is 1e16 to 1e18cm -3 。
10. A method of fabricating a silicon carbide MOSFET cell layout structure according to any of claims 1 to 9, the method comprising the steps of:
step 1, growing an N-type drift region on an epitaxial layer of an N-type silicon carbide substrate;
step 2, performing multiple times of ion implantation on the N-type drift region to generate a first source electrode region, a second source electrode region, a JFET region and an SBD region, wherein the first source electrode region comprises a P-Body region, a first P + type source region and an N + type source region which have different doping concentrations, and the second source electrode region is a second P + type source region;
step 3, preparing an isolation gate region on the N-type drift region, wherein the isolation gate region comprises a POLY region, wrapping a layer of gate oxide layer on the surface of the POLY region in a thermal oxidation growth mode, and forming a Schottky contact region above the SBD region through metal sputtering;
step 4, growing source metal on the N-type drift region, the isolation gate region and the SBD region;
and 5, growing drain metal below the N-type silicon carbide substrate.
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