CN102097479A - Low-voltage buried channel VDMOS (vertical double-diffused metal oxide semiconductor) device - Google Patents
Low-voltage buried channel VDMOS (vertical double-diffused metal oxide semiconductor) device Download PDFInfo
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- CN102097479A CN102097479A CN 201010594452 CN201010594452A CN102097479A CN 102097479 A CN102097479 A CN 102097479A CN 201010594452 CN201010594452 CN 201010594452 CN 201010594452 A CN201010594452 A CN 201010594452A CN 102097479 A CN102097479 A CN 102097479A
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Abstract
The invention provides a low-voltage buried channel VDMOS (vertical double-diffused metal oxide semiconductor) device, belonging to the technical field of semiconductor devices. The device has the following beneficial effects: the channel resistance is greatly reduced by adopting the buried layer channel structure; the MOS gate oxide layer is very thin; the MOS surface field effect is utilized; an accumulation layer is formed when forward voltage is applied between the gate and the source while a depletion layer is formed when backward voltage is applied between the gate and the source; and electron or hole accumulation occurs on the lower semiconductor surface of the gate oxide layer under low forward gate voltage, thus acquiring extremely low resistance and good switch characteristics. The device can be widely applied to portable power supplies and CPU power supply systems.
Description
Technical field
A kind of low pressure buried channel VDMOS device belongs to technical field of semiconductor device.
Background technology
Power MOSFET (mos field effect transistor) is the power switching device of new generation that grows up on MOS integrated circuit technology basis.Vertical DMOS (VDMOS) device has the input impedance height, a series of unique features such as switching speed is fast, operating frequency is high, voltage control, Heat stability is good, has obtained at aspects such as switching power supply, high-frequency heating, computer interface circuit and power amplifiers at present to use widely.
VDMOS (vertical DMOS field-effect transistor) though device in the low pressure applications field, can obtain comparatively ideal conducting resistance and switching characteristic, but the supply voltage of using along with integrated circuit constantly reduces, the conduction loss that is produced by the power device conducting resistance becomes a bottleneck of restriction entire circuit system energy efficiency, and institute is so that the lower conduction loss of low voltage power devices acquisition is the direction that power device constantly advances always.
Traditional VDMOS device, as shown in Figure 1, what wherein the polygate electrodes utmost point 9 adopted is planar gate structure, electric current is when flowing to the raceway groove parallel with the grid surface, the inversion-layer channel that P type tagma 5 below the polygate electrodes 9 is formed by the semiconductor surface transoid is the only way which must be passed of electric current, it becomes a series resistance on the current channel, and the VDMOS channel resistance is far longer than JFET resistance when low pressure, becomes the maximum part of VDMOS conducting resistance.The existence of the channel resistance that forms just because of this inversion-layer channel makes conventional low VDMOS device be difficult to obtain lower conduction loss.
Document B.Jayant Baliga, Fellow IEEE, Tsengyou Syau and Prasad Venkatraman, TheAccumulation-Mode Field-Effect Transistor A New Ultralow On-Resistance MOSFET, IEEEELECTRON DEVICE LETTERS, VOL.13, NO.8, AUGUST 1992, provide a kind of trench gate accumulation type ultralow conducting resistance MOSFET device, as shown in Figure 2, wherein polysilicon gate has adopted trench gate 3 structures to replace planar gate structure, does not exist P type tagma and trench gate 3 to extend to N in this structure always
+Drain region 1, by a series of special processing such as sidewall oxidations, the N in the sidewall oxide outside
-Formed raceway groove in the epi region 2 perpendicular to silicon chip surface.Electric current is from N during work
+Source region 4 directly flows to vertical-channel and enters N
+Drain region 1 makes primitive unit cell density increase, and has improved the on state characteristic of device, has reduced conducting resistance, thereby has obtained lower conduction loss.But this kind structure is had higher requirement to manufacturing process, and reverse leakage current is big.
Summary of the invention
The invention provides a kind of low pressure buried channel VDMOS device, this device architecture and traditional VDMOS similar adopt planar technique to make, and use the energetic ion injection to replace traditional double diffusion technique when the dark P body of preparation goes, and only use 4 reticle.Withstand voltage reaching more than the 30V, leakage current level and traditional structure are suitable substantially, and conduction resistance only is 95 μ Ω cm
2, much smaller than 600 μ Ω cm of traditional structure
2
Technical solution of the present invention is as follows:
A kind of low pressure buried channel VDMOS device, its basic structure comprise metallization drain electrode 1, N as shown in Figure 3
+ Substrate 2, N
- Epitaxial loayer 3, dark P tagma 5, N type heavily doped region 6, P type heavily doped region 7, gate oxide 8, polygate electrodes 9, metallizing source 10.Metallization drain electrode 1 is positioned at N
+Substrate 2 back sides, N
- Epitaxial loayer 3 is positioned at N
+Substrate 2 fronts.Two dark P tagmas 5 are positioned at N
-The both sides on epitaxial loayer 3 tops, the Outboard Sections in dark P tagma 5 links to each other with metallizing source 10 by P type heavily doped region 7; The inside part in dark P tagma 5 links to each other with metallizing source 10 by N type heavily doped region 6.N between two N type heavily doped regions 6
-The surface of epitaxial loayer 3 is gate oxides 8, and the surface of gate oxide 8 is polygate electrodes 9, is spacer medium between polygate electrodes 9 and the metallizing source 10.Described dark P tagma 5 adopts the energetic ion injection technology to make; The thickness of described gate oxide 8 is between 5～30 nanometers.
In the technique scheme:
A kind of low pressure buried channel VDMOS device provided by the present invention adopts the manufacturing process compatible mutually with conventional cmos technology, satisfying under the very little situation of puncture voltage and leakage current, can obtain minimum conduction resistance.Be example now, operation principle of the present invention is described with Fig. 3.
A kind of low pressure buried channel VDMOS device provided by the present invention, gate oxide 8 thickness extremely thin (several nanometers only being arranged) to tens nanometers, and distance is about 1 micron between two dark P tagmas 5.Structure of the present invention is not when adding any voltage, by gate oxide 8, N
-Two depletion regions overlap fully and exhaust about two buried channel structures, 11 quilts of epitaxial loayer 3 and dark P tagma 5 formations: top is gate oxide 8 and N
-The metal-oxide-semiconductor structure depletion region that epitaxial loayer 3 constitutes is dark P tagma 5 and its top N below
-The PN junction depletion region that epitaxial loayer 3 is constituted.When polygate electrodes 9 and metallizing source 10 ground connection, metallization drain electrode 1 adds positive voltage to be tested when withstand voltage, buried channel structure 11 and junction field effect transistor district 4 (by two dark P tagmas 5 and between N
-Epitaxial loayer 3) work simultaneously, make the current path of drain-to-source by complete pinch off, leakage current is very little, punctures to occur in dark P tagma 5 and its below N
-The PN junction place that epitaxial loayer 3 constitutes; When metallizing source 10 ground connection, when polygate electrodes 9 adds positive voltage, form how many carrier accumulation layers in the buried channel structure 11, raceway groove is opened, and when metallization drain electrode 1 adds positive voltage, forms forward conduction.
Because junction field effect transistor district 4 relative broads (about 1 micron), so do not add at device under the situation of any biasing, junction field effect transistor district 4 not exclusively exhausts, and promptly this district can be charge carrier path is provided; Because buried channel district 11 is extremely thin, so not adding under any biasing at device, this district do not exhaust fully, and charge carrier can not pass through, and for buried channel district 11, it exhausts thickness and N that situation depends on gate oxide 8
-The concentration in epitaxial loayer 3 and dark P tagma 5.So the conducting of device and unlatching depend primarily on the situation of buried channel structure 11, the i.e. bias conditions of gate voltage.Because gate oxide 8 thickness extremely thin (several nanometers only being arranged to tens nanometers), so the grid-control ability of device is very strong, this makes the conversion of device between unlatching and spent condition be very easy to.Like this, the conducting resistance of device mainly depends on N
-The concentration of epitaxial loayer 3 and thickness so satisfying the situation of device withstand voltage, in order to reduce conducting resistance, should increase N as far as possible
-The concentration of epitaxial loayer 3 and reduce N
-The thickness of epitaxial loayer 3.In addition, because gate oxide as thin as a wafer, so the threshold voltage of device is lower.
A kind of low pressure buried channel VDMOS as shown in Figure 3 that is provided has carried out emulation.The emulation device parameters is: N
+Substrate zone 2 mixes 1.8 * 10
19Cm
-3N
- Epitaxial loayer 3 mixes 2 * 10
16Cm
-3, thickness is 3 μ m; Junction field effect transistor district 4 width (i.e. distance between two dark P tagmas 5) are 1.4um; P tagma 5 doping contents are 3 * 10
17Cm
-3, thickness is 0.45 μ m; N type heavily doped region 6 mixes 8 * 10
19Cm
-3, width is 0.1um; P type heavily doped region 7 mixes 1.8 * 10
20Cm
-3, width is 0.1um; Gate oxide 8 thickness are 8nm, and width is 1.4um; Buried channel district 11 thickness are 0.05um; Emulation cellular width is 2 μ m.Fig. 4 is the puncture voltage simulation curve figure of above-mentioned a kind of low pressure buried channel VDMOS, and as shown in Figure 4, the breakdown characteristics of device is good, and puncture voltage can reach 31V, and leakage current is very little.Fig. 5 is its threshold voltage characteristic simulation curve, and as shown in Figure 5, the threshold voltage of this device is less, and the transfer characteristic of device is issued to saturated at less gate source voltage.Fig. 6 is on-resistance characteristics simulation curve figure, and wherein gate source voltage equals 10V.As shown in Figure 6, the conducting resistance of device is 95 μ Ω cm
2In sum, a kind of low pressure buried channel VDMOS provided by the invention, its technology is very simple with respect to conventional VDMOS structure, and owing to combine junction field tubular construction and buried channel structure, satisfying under the withstand voltage situation, making that the leakage current of device is less, conducting resistance is minimum.
Description of drawings
Fig. 1 is traditional VDMOS device architecture schematic diagram
Wherein, the 1st, metallization drain electrode, the 2nd, N
+Substrate zone, the 3rd, N
-Epitaxial loayer, the 4th, junction field effect transistor district, the 5th, P tagma, the 6th, N type heavily doped region, the 7th, P type heavily doped region, the 8th, gate oxide, the 9th, polygate electrodes, the 10th, metallizing source.
Fig. 2 is the ultralow conducting resistance MOSFET device architecture of an a kind of trench gate accumulation type schematic diagram.
Wherein, the 1st, metallization drain electrode, the 2nd, N
+Substrate zone, the 3rd, N
-Epitaxial loayer, the 4th, groove polysilicon gate, the 5th, N type heavily doped region, the 6th, gate oxide, the 7th, metallizing source.
Fig. 3 is a kind of low pressure buried channel VDMOS structural representation provided by the invention.
Wherein, the 1st, metallization drain electrode, the 2nd, N
+Substrate zone, the 3rd, N
-Epitaxial loayer, the 4th, junction field effect transistor district, the 5th, dark P tagma, the 6th, N type heavily doped region, the 7th, P type heavily doped region, the 8th, gate oxide, the 9th, polygate electrodes, the 10th, metallizing source, the 11st, buried channel structure.
Fig. 4 is a kind of low pressure buried channel VDMOS puncture voltage simulation curve figure provided by the present invention.
As can be seen from the figure the puncture voltage of structure of the present invention is more than 31V.
Fig. 5 is the threshold voltage characteristic simulation curve figure of a kind of low pressure buried channel VDMOS provided by the present invention.
Fig. 6 is the on-resistance characteristics simulation curve figure of the grid voltage of a kind of low pressure buried channel VDMOS provided by the present invention when equaling 10V.
Embodiment
A kind of low pressure buried channel VDMOS as shown in Figure 3, comprises metallization negative electrode 1, N
+Substrate zone 2, N
- Epitaxial loayer 3, junction field effect transistor district 4, dark P tagma 5, P type heavily doped region 6, N type heavily doped region 7, gate oxide 8, polygate electrodes 9, metallization anode 10, buried channel structure 11.
A kind of low pressure buried channel VDMOS device, embodiment can adopt following method to prepare, and processing step is:
One, monocrystalline silicon is prepared, and adopts N type heavy doping study on floating zone silicon (N type impurity) substrate 2, and doping content is 1.8 * 10
19Cm
-3, its crystal orientation is＜100 〉, thickness is 5 μ m.
Two, outer layer growth adopts vapour phase epitaxy VPE method under 1000 ℃ of temperature, vacuum condition, the N of growth 3 μ m on substrate 2
- Epitaxial loayer 3, phosphorus doping density are 2 * 10
16Cm
-3
Three, boron is injected in dark P tagma, at the thick photoresist of whole silicon wafer surface deposition one deck 4 μ m, carries out the figure in the dark P of photoetching tagma 5 with the Poly reticle, high-energy boron ion injection then, and dosage is 6.5 * 10
12Cm
-2, energy is 80KeV, forms dark P tagma 5, doping content is 3 * 10
17Cm
-3, dark P tagma 5 upper surface junction depths are 0.05 μ m, dark P tagma 5 lower surface junction depths are 0.5 μ m.
Four, the preparation polysilicon gate uses dried oxygen method, in the time of 1000 ℃, and 2.5slm O
2With dry-oxygen oxidation under the 67sccmHCl atmosphere condition 2.5 minutes, growth thickness is the gate oxide of 8nm, chemical vapor deposition 15 minutes under the 5slm SiH4 atmospheric condition in the time of 635 ℃, deposition thickness is the polysilicon of 0.4 μ m, with multi-crystal silicon area Poly reticle, adopt prior art that polysilicon and gate oxide are carried out the photoetching of metal-oxide-semiconductor structure figure, obtain polygate electrodes 9 and silicon dioxide gate oxide 8.
Five, preparation N type heavily doped region NSD uses multi-crystal silicon area Poly reticle to carry out heavily doped region arsenic and injects, and dosage is 7 * 10
13Cm
-2, energy is 20KeV, obtains N type heavily doped region 7, peak doping concentration is 8 * 10
19Cm
-3, junction depth is 0.1 μ m.
Six, preparation P type heavily doped region PSD uses multi-crystal silicon area PSD reticle to carry out heavily doped region boron and injects, and dosage is 4 * 10
14Cm
-2, energy is 30KeV, obtains N type heavily doped region 7, peak doping concentration is 8 * 10
19Cm
-3, junction depth is 0.3 μ m.
Seven, preparation contact hole, 5slm SiH in the time of 520 ℃
4, 15slm O
2, 33sccm B
2H
6With 23sccm PH
3Chemical vapor deposition is 35 minutes under the atmospheric condition, and deposition thickness is the SiO of 3um
2, adopt the Contact reticle to carry out etch polysilicon electrode and metallizing source contact hole.
Eight, front-side metallization is the metallic aluminium of 4 μ m at entire device surface sputtering one layer thickness, adopts the Metal reticle to carry out the etching metallic aluminium, forms gate electrode metal pressure welding point and metallization anode 10 metal crimp solder joints.
Nine, thinning back side and metallization are carried out mechanical reduction to the device back side and are handled, device be thinned to about 15 μ m, and be the metallic aluminium of 4 μ m by prior art at device back spatter thickness afterwards, form metallization drain electrode 1 lead-in wire.
Carry out preliminary survey, scribing, sintering, lead-in wire bonding, middle survey, encapsulation and total the survey by prior art again, obtain low pressure buried channel VDMOS device of the present invention.By the puncture voltage simulation curve of the prepared low pressure buried channel VDMOS device of above-mentioned preparation process as shown in Figure 4, as shown in Figure 4, the breakdown characteristics of device is good, and puncture voltage can reach 31V, and leakage current is very little.Fig. 5 is its threshold voltage characteristic simulation curve, and as shown in Figure 5, the threshold voltage of this device is less, and the transfer characteristic of device is issued to saturated at less gate source voltage.Fig. 6 is on-resistance characteristics simulation curve figure, and wherein gate source voltage equals 10V.As shown in Figure 6, the conducting resistance of device is 95 μ Ω cm
2
Adopt 4 reticle in the method for present embodiment altogether, be followed successively by the Poly reticle, PSD reticle, Contact reticle and Metal reticle according to the order of version number.
The ion implantation process that the method for present embodiment is carried out has: dark P tagma boron injects, and NSD phosphorus injects, and PSD boron injects.
Adopt a kind of low pressure buried channel VDMOS of the present invention, can realize low conduction voltage drop.Along with development of semiconductor, adopt the present invention can also make more low energy-consumption electronic device fast.
Claims (2)
1. a low pressure buried channel VDMOS device comprises metallization drain electrode (1), N
+Substrate (2), N
-Epitaxial loayer (3), dark P tagma (5), N type heavily doped region (6), P type heavily doped region (7), gate oxide (8), polygate electrodes (9), metallizing source (10); Metallization drain electrode (1) is positioned at N
+Substrate (2) back side, N
-Epitaxial loayer (3) is positioned at N
+Substrate (2) front; Two dark P tagmas (5) are positioned at N
-The both sides on epitaxial loayer (3) top, the Outboard Sections in dark P tagma (5) links to each other with metallizing source (10) by P type heavily doped region (7); The inside part in dark P tagma (5) links to each other with metallizing source (10) by N type heavily doped region (6); N between two N type heavily doped regions (6)
-The surface of epitaxial loayer (3) is gate oxide (8), and the surface of gate oxide (8) is polygate electrodes (9), is spacer medium between polygate electrodes (9) and the metallizing source (10); Described dark P tagma (5) adopts the energetic ion injection technology to make; The thickness of described gate oxide (8) is between 5～30 nanometers.
2. a kind of low pressure buried channel VDMOS device according to claim 1 is characterized in that, dark P tagma (5) adopts the high-energy boron ion to inject, and injects energy and be 50KeV～150KeV and implantation dosage 3 * 10
12～5 * 10
13Cm
-2Between, N type heavily doped region (6) adopts arsenic ion to inject or the arsenic ion diffusion, and the arsenic ion energy is that 10KeV～30KeV and dosage are 2 * 10
19～9 * 10
19Cm
-3Between, P type heavily doped region (7) adopts the boron ion to inject or the boron ions diffusion, and the boron ion energy is that 20～40KeV and dosage are 2 * 10
19～2 * 10
20Cm
-3Between.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102364688A (en) * | 2011-11-09 | 2012-02-29 | 电子科技大学 | Vertical double-diffusion metal oxide semiconductor field effect transistor (MOSFET) |
| CN102420251A (en) * | 2011-12-05 | 2012-04-18 | 电子科技大学 | VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) device with non-uniform floating island structure |
| CN103840007A (en) * | 2014-03-10 | 2014-06-04 | 中国科学院微电子研究所 | VDMOS transistor with shielding grid structure |
| CN104810286A (en) * | 2014-01-23 | 2015-07-29 | 北大方正集团有限公司 | MOS tube and manufacture method thereof |
| CN107153157A (en) * | 2016-03-03 | 2017-09-12 | 北京大学 | Dipulse Sofe Switch method of testing distinguishes GaN HEMT surfaces and cushion current collapse |
| CN107170672A (en) * | 2017-05-18 | 2017-09-15 | 上海先进半导体制造股份有限公司 | VDMOS gate oxide growth method |
| CN108231898A (en) * | 2017-12-14 | 2018-06-29 | 东南大学 | A kind of silicon carbide power semiconductor devices of low on-resistance |
| CN115020478A (en) * | 2022-08-08 | 2022-09-06 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
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| CN102364688A (en) * | 2011-11-09 | 2012-02-29 | 电子科技大学 | Vertical double-diffusion metal oxide semiconductor field effect transistor (MOSFET) |
| CN102420251A (en) * | 2011-12-05 | 2012-04-18 | 电子科技大学 | VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) device with non-uniform floating island structure |
| CN104810286B (en) * | 2014-01-23 | 2019-04-09 | 北大方正集团有限公司 | A kind of metal-oxide-semiconductor and its manufacturing method |
| CN104810286A (en) * | 2014-01-23 | 2015-07-29 | 北大方正集团有限公司 | MOS tube and manufacture method thereof |
| CN103840007A (en) * | 2014-03-10 | 2014-06-04 | 中国科学院微电子研究所 | VDMOS transistor with shielding grid structure |
| CN103840007B (en) * | 2014-03-10 | 2017-04-19 | 北京中科新微特科技开发股份有限公司 | VDMOS of shield grid structure |
| CN107153157A (en) * | 2016-03-03 | 2017-09-12 | 北京大学 | Dipulse Sofe Switch method of testing distinguishes GaN HEMT surfaces and cushion current collapse |
| CN107153157B (en) * | 2016-03-03 | 2019-11-01 | 北京大学 | Dipulse Sofe Switch method of testing distinguishes the surface GaN HEMT and buffer layer current collapse |
| CN107170672A (en) * | 2017-05-18 | 2017-09-15 | 上海先进半导体制造股份有限公司 | VDMOS gate oxide growth method |
| WO2019114201A1 (en) * | 2017-12-14 | 2019-06-20 | 东南大学 | Silicon carbide power semiconductor device having low on-resistance |
| CN108231898A (en) * | 2017-12-14 | 2018-06-29 | 东南大学 | A kind of silicon carbide power semiconductor devices of low on-resistance |
| CN115020478A (en) * | 2022-08-08 | 2022-09-06 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
| CN115020478B (en) * | 2022-08-08 | 2022-10-04 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
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Application publication date: 20110615 |