WO2019114201A1 - Silicon carbide power semiconductor device having low on-resistance - Google Patents
Silicon carbide power semiconductor device having low on-resistance Download PDFInfo
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- WO2019114201A1 WO2019114201A1 PCT/CN2018/088785 CN2018088785W WO2019114201A1 WO 2019114201 A1 WO2019114201 A1 WO 2019114201A1 CN 2018088785 W CN2018088785 W CN 2018088785W WO 2019114201 A1 WO2019114201 A1 WO 2019114201A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 31
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000002161 passivation Methods 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 108091006146 Channels Proteins 0.000 description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000003208 petroleum Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Definitions
- the device of the present invention can be provided with a plurality of N-type regions in the P-type base region, as shown in Fig. 9, so that the device can obtain more conductive channels in the on state, thereby further improving the current capability of the device.
- FIG. 1 is a perspective view showing the structure of a conventional silicon carbide power semiconductor device.
- FIG. 2 is a perspective view showing the structure of a silicon carbide power semiconductor device of the present invention.
- FIG. 4 is a top cross-sectional view of a silicon carbide power semiconductor device of the present invention.
- a low on-resistance silicon carbide power semiconductor device is an axisymmetric structure, comprising: an N-type substrate 1 in one of the N-type substrates 1 A drain metal 10 is connected to the side, an N-type drift region 2 is provided on the other side of the N-type substrate 1, and a pair of P-type base regions 3 are symmetrically disposed in the N-type drift region 2, and in each of the P-type base regions 3 A P+ type body contact region 4 and an N+ type source region 5 are respectively disposed, a gate oxide layer 7 is disposed on the surface of the N type drift region 2, and a polysilicon gate 8 is disposed on the surface of the gate oxide layer 7 on the polysilicon gate 8.
- a passivation layer 6 is disposed, and the passivation layer 6 wraps both sides of the polysilicon gate 8, and the source metal 9 is connected to the N-type source region 5 and the P-type body contact region 6, which is characterized in that each P-type base
- the array 3 is provided with an array of N-type regions 11 respectively, and the array is surrounded by the P-type base region 3, and the upper surface is separated from the gate oxide layer 7, and the N-type region 11 starts from N+.
- the source region 5 extends horizontally in the channel direction to the N-type drift region 2, and the N-type region 11 and the P-type base region 3 are spaced apart in the gate width direction of the device, and the N-type region 11 is in the P-type region in the natural state.
Abstract
A silicon carbide power semiconductor device having low on-resistance, which is an axisymmetric structure and which comprises: an N-type substrate (1), wherein an N-type drift region (2) is provided on the N-type substrate, and a pair of P-type base regions (3) are symmetrically provided in the N-type drift region, a P+ type body contact region (4) and an N+ type source region (5) being provided in the P-type base region; a gate oxide layer (7) is provided on a surface of the N-type drift region, and a polysilicon gate (8) is provided on a surface of the gate oxide layer; an array formed by N-type regions (11) is provided within the P-type base regions, an upper surface being separated from the gate oxide layer; the N-type regions and the P-type base regions are distributed at intervals in the device gate width direction, and the distance from the N-type regions to the gate oxide layer, the thickness, and the doping concentration cause the N-type regions to be exactly pinched off in the natural state. While maintaining the breakdown voltage of the device, the on-resistance of the device is lowered, the on-state current capabilities of the device are improved, and on-state energy loss is reduced.
Description
本发明主要涉及高压功率半导体器件领域，具体来说，是一种低导通电阻的碳化硅功率半导体器件，适用于航天、航空、石油勘探、核能、雷达与通信等高温、高频、大功率、强辐射等极端环境并存的应用领域。The invention mainly relates to the field of high voltage power semiconductor devices, in particular to a silicon carbide power semiconductor device with low on-resistance, suitable for high temperature, high frequency and high power such as aerospace, aviation, petroleum exploration, nuclear energy, radar and communication. Application areas where extreme environments such as strong radiation coexist.
碳化硅是近十几年来迅速发展起来的宽禁带半导体材料之一。与广泛应用的半导体材料硅、锗以及砷化镓相比，碳化硅具有宽禁带、高击穿电场、高载流子饱和漂移速率、高热导率及高功率密度等优点，是制备高温、大功率、高频器件的理想材料。目前美、欧、日等发达国家已经基本解决了碳化硅单晶生长和同质外延薄膜等问题，在大功率半导体器件领域占据主导地位。据报道，2014年1月中国首次实现碳化硅大功率器件的批量生产，在以美、欧、日为主导的半导体领域形成突破。Silicon carbide is one of the wide band gap semiconductor materials that has developed rapidly in the past decade. Compared with widely used semiconductor materials such as silicon, germanium and gallium arsenide, silicon carbide has the advantages of wide band gap, high breakdown electric field, high carrier saturation drift rate, high thermal conductivity and high power density. Ideal for high power, high frequency devices. At present, the developed countries such as the United States, Europe, and Japan have basically solved the problems of silicon carbide single crystal growth and homoepitaxial thin films, and have dominated the field of high-power semiconductor devices. According to reports, in January 2014, China achieved mass production of high-power silicon carbide devices for the first time, forming a breakthrough in the semiconductor field dominated by the United States, Europe and Japan.
图1所示的是常规的碳化硅功率半导体器件，包括：N型衬底，在N型衬底的一侧连接有漏极金属，在N型衬底的另一侧设有N型漂移区，在N型漂移区中对称设置一对P型基区，N+型源区和P+型体接触区，在N型漂移区的表面设有栅氧层，在栅氧层的表面设有多晶硅栅，在多晶硅栅的上方设有钝化层，在N+型源区和P+型体接触区连接有源极金属。当有足够大的正电压施加在多晶硅栅上时，P型基区与栅氧化层的界面会产生一个反型沟道，电子可以通过沟道从N+型有源区注入到N型漂移区。但是由于常规的碳化硅功率半导体器件的导电沟道紧贴在栅氧化层下方，栅氧化层表面的缺陷会对载流子输运产生影响，因此常规的碳化硅功率半导体器件导通电阻较高。Figure 1 shows a conventional silicon carbide power semiconductor device comprising: an N-type substrate having a drain metal connected to one side of the N-type substrate and an N-type drift region on the other side of the N-type substrate. a pair of P-type base regions, an N+-type source region and a P+-type body contact region are symmetrically disposed in the N-type drift region, a gate oxide layer is disposed on the surface of the N-type drift region, and a polysilicon gate is disposed on the surface of the gate oxide layer A passivation layer is disposed above the polysilicon gate, and the source metal is connected to the N+ source region and the P+ body contact region. When a sufficiently large positive voltage is applied to the polysilicon gate, the interface between the P-type base region and the gate oxide layer creates an inversion channel through which electrons can be injected from the N+ type active region into the N-type drift region. However, since the conductive channel of the conventional silicon carbide power semiconductor device is closely under the gate oxide layer, defects on the surface of the gate oxide layer may affect carrier transport, so the conventional silicon carbide power semiconductor device has a high on-resistance. .
发明内容Summary of the invention
本发明就是针对上述问题，提出了一种低导通电阻的碳化硅功率半导体器件，该结构在保持击穿电压不变的基础上，有效降低器件的导通电阻、提升了器件的通态I-V特性、降低了件在导通状态下的能量损耗。The present invention is directed to the above problem, and proposes a silicon carbide power semiconductor device with low on-resistance, which effectively reduces the on-resistance of the device and improves the on-state IV of the device while maintaining the breakdown voltage constant. Characteristics, reducing the energy loss of the component in the on state.
本发明采用如下技术方案：一种低导通电阻的碳化硅功率半导体器件，所述低导通电阻的碳化硅功率半导体器件为轴对称结构，包括：N型衬底，在N型 衬底的一侧连接有漏极金属，在N型衬底的另一侧设有N型漂移区，在N型漂移区中对称设置一对P型基区，在各P型基区中分别设有P+型体接触区和N+型源区，在N型漂移区的表面设有栅氧层，在栅氧层的表面设有多晶硅栅，在多晶硅栅上设有钝化层且所述钝化层包裹多晶硅栅的两侧，在N型源区和P型体接触区连接有源极金属，其特征在于：在各P型基区体内分别设有由N-型区构成的阵列且所述阵列被P型基区包裹在其内部，上表面与栅氧层相分离，所述N-型区始于N+型源区沿沟道方向水平延伸至N型漂移区，在器件栅宽方向上N-型区与P型基区间隔分布，且自然状态下N-型区在P型基区的辅助耗尽下恰好完全夹断。所述N-型区上表面与栅氧层之间的距离约为0.2-0.3μm。所述N-型区厚度为150-250nm。所述N-型区的掺杂浓度为1e16-4e17cm
-3。所述N-型区的宽度与栅宽的比例为0.1-0.5:1。所述的被P型基区包裹在其内部的N-型区阵列可以不止一层，自然状态下各层N-型区阵列在P型基区的辅助耗尽下均恰好完全夹断。
The present invention adopts the following technical solution: a low on-resistance silicon carbide power semiconductor device, the low on-resistance silicon carbide power semiconductor device is an axisymmetric structure, including: an N-type substrate, on an N-type substrate A drain metal is connected to one side, an N-type drift region is disposed on the other side of the N-type substrate, a pair of P-type base regions are symmetrically disposed in the N-type drift region, and P+ is respectively disposed in each of the P-type base regions. a body contact region and an N+ source region, a gate oxide layer is disposed on a surface of the N-type drift region, a polysilicon gate is disposed on a surface of the gate oxide layer, a passivation layer is disposed on the polysilicon gate, and the passivation layer is wrapped On both sides of the polysilicon gate, a source metal is connected to the N-type source region and the P-type body contact region, wherein an array of N-type regions is respectively disposed in each P-type base region and the array is The P-type base region is wrapped therein, and the upper surface is separated from the gate oxide layer. The N-type region starts from the N+-type source region and extends horizontally in the channel direction to the N-type drift region, in the device gate width direction N- The type region is spaced apart from the P-type base region, and in the natural state, the N-type region is completely pinched off under the auxiliary depletion of the P-type base region. The distance between the upper surface of the N-type region and the gate oxide layer is about 0.2-0.3 μm. The N-type region has a thickness of 150-250 nm. The doping concentration of the N-type region is 1e16-4e17 cm -3 . The ratio of the width of the N-type region to the gate width is 0.1-0.5:1. The array of N-type regions surrounded by the P-type base region may have more than one layer. In the natural state, the array of N-type regions of each layer is completely pinched off under the auxiliary depletion of the P-type base region.
与现有技术相比，本发明具有如下优点：Compared with the prior art, the present invention has the following advantages:
(1)、本发明器件采用在P型基区中设置N-型区的结构，通过增加有效导通路径，从而有效降低器件导通电阻和阈值电压，获得更高的开态电流能力。(1) The device of the present invention adopts a structure in which an N-type region is provided in a P-type base region, thereby effectively reducing the on-resistance and the threshold voltage of the device by increasing the effective conduction path, thereby obtaining a higher on-state current capability.
当栅极电压为零时，N-型区与P型基区完全耗尽，功率半导体管在常态下关闭。当有设定的正电压施加在栅极上时，除了在P型基区与栅氧化层之间的界面会产生的反型沟道，由于N-型区与P型基区之间的耗尽层在正栅压下减小，原本恰好完全夹断的N-型区与P型基区上下接触面也会感应出有效导电沟道，且N-型区位于P型基区体内，N-型区与P型基区纵向接触面上也会感应出有效导电沟道，N+源区的电子会同时通过多条沟道到达功率半导体管的N-型漂移区，从而有效的降低了器件的导通电阻，使本发明器件在开态下电流能力获得极大的提升。如图5所示，与常规功率半导体器件相比，本发明的功率半导体器件在开态下有更高的电流能力。When the gate voltage is zero, the N-type region and the P-type base region are completely depleted, and the power semiconductor tube is turned off in a normal state. When a set positive voltage is applied to the gate, in addition to the inversion channel generated at the interface between the P-type base region and the gate oxide layer, due to the consumption between the N-type region and the P-type base region The inner layer is reduced under the positive grid pressure, and the upper and lower contact surfaces of the N-type region and the P-type base region which are originally completely pinched off also induce an effective conductive channel, and the N-type region is located in the P-type base region, N The effective contact channel is also induced on the longitudinal contact surface of the -type region and the P-type base region, and the electrons in the N+ source region simultaneously reach the N-type drift region of the power semiconductor tube through a plurality of channels, thereby effectively reducing the device. The on-resistance of the device greatly improves the current capability of the device of the present invention in the on state. As shown in FIG. 5, the power semiconductor device of the present invention has a higher current capability in an open state than a conventional power semiconductor device.
(2)本发明器件采用在P型基区中设置N-型区的结构，N-型区位于器件体内且被P型基区所包裹，从而使得N-型区感应出的有效导电沟道与栅氧层相分离，消除了栅氧层缺陷对载流子传输的影响，因此其有效载流子迁移率比与栅氧层相接触的表面沟道高的多，从而进一步降低了功率半导体管导通电阻。如图 6所示，与常规功率半导体器件相比，本发明的功率半导体器件阈值电压更小，导通电阻更小。(2) The device of the present invention adopts a structure in which an N-type region is provided in a P-type base region, and the N-type region is located in the device body and is surrounded by the P-type base region, thereby causing an effective conductive channel induced by the N-type region. Separation from the gate oxide layer eliminates the effect of gate oxide defects on carrier transport, so its effective carrier mobility is much higher than that of the surface channel in contact with the gate oxide layer, further reducing power semiconductors. Tube on resistance. As shown in FIG. 6, the power semiconductor device of the present invention has a smaller threshold voltage and a smaller on-resistance than a conventional power semiconductor device.
(3)本发明器件在栅宽方向上N-型区与P型基区间隔分布，这样的分段式结构使得P型基区体内上下电位一致，从而可以有效避免阈值电压漂移和寄生三极管开启，获得比较稳定的工作状态。(3) The device of the present invention is spaced apart from the P-type base region in the gate width direction. Such a segmented structure makes the upper and lower potentials of the P-type base region uniform, thereby effectively avoiding threshold voltage drift and parasitic transistor opening. , get a relatively stable working state.
(4)本发明器件在P型基区中设置的N-型区不在主PN结上，不易发生雪崩击穿，因而对器件的击穿电压的影响比较小。如图7所示，与常规功率半导体器件相比，本发明器件的击穿电压几乎保持不变。(4) The N-type region provided in the P-type base region of the device of the present invention is not on the main PN junction, and is less prone to avalanche breakdown, and thus has less influence on the breakdown voltage of the device. As shown in Figure 7, the breakdown voltage of the device of the present invention remains almost unchanged as compared to conventional power semiconductor devices.
(5)本发明器件在P型基区中可设置多层N-型区，如图9所示，因此器件在开态下可以获得更多的导电沟道，从而进一步提高器件的电流能力。(5) The device of the present invention can be provided with a plurality of N-type regions in the P-type base region, as shown in Fig. 9, so that the device can obtain more conductive channels in the on state, thereby further improving the current capability of the device.
图1是常规碳化硅功率半导体器件结构立体图。1 is a perspective view showing the structure of a conventional silicon carbide power semiconductor device.
图2是本发明碳化硅功率半导体器件结构立体图。2 is a perspective view showing the structure of a silicon carbide power semiconductor device of the present invention.
图3是本发明碳化硅功率半导体器件结构侧剖立体图。Figure 3 is a side cross-sectional perspective view showing the structure of a silicon carbide power semiconductor device of the present invention.
图4是本发明碳化硅功率半导体器件俯视剖面图。4 is a top cross-sectional view of a silicon carbide power semiconductor device of the present invention.
图5是本发明器件与常规碳化硅功率半导体器件在栅压为8V时的I-V曲线比较图。可以看出本发明器件使开态下的电流能力的得到了明显的提高。Figure 5 is a graph comparing the I-V curve of the device of the present invention with a conventional silicon carbide power semiconductor device at a gate voltage of 8V. It can be seen that the device of the present invention provides a significant improvement in current capability in the on state.
图6是本发明器件与常规碳化硅功率半导体器件的阈值电压比较图。可以看出本发明器件使阈值电压得到了明显的降低。Figure 6 is a graph comparing threshold voltages of a device of the present invention with a conventional silicon carbide power semiconductor device. It can be seen that the device of the present invention provides a significant reduction in threshold voltage.
图7是本发明器件与常规碳化硅功率半导体器件的击穿电压比较图。可以看出本发明器件击穿电压几乎不变。Figure 7 is a graph comparing the breakdown voltage of a device of the present invention with a conventional silicon carbide power semiconductor device. It can be seen that the breakdown voltage of the device of the present invention is almost constant.
图8是本发明碳化硅功率半导体器件工艺实现图。Figure 8 is a process realization diagram of a silicon carbide power semiconductor device of the present invention.
图9是本发明碳化硅功率半导体器件的P型基区中设置多层N-型区阵列的结构图。Figure 9 is a structural view showing the arrangement of a plurality of N-type region arrays in a P-type base region of a silicon carbide power semiconductor device of the present invention.
下面结合说明书附图对本发明作详细说明。The invention will now be described in detail in conjunction with the drawings.
参照图2，一种低导通电阻的碳化硅功率半导体器件，所述低导通电阻的碳化硅功率半导体器件为轴对称结构，包括：N型衬底1，在N型衬底1的一侧连接有漏极金属10，在N型衬底1的另一侧设有N型漂移区2，在N型漂移区2中对称设置一对P型基区3，在各P型基区3中分别设有P+型体接触区4和N+ 型源区5，在N型漂移区2的表面设有栅氧层7，在栅氧层7的表面设有多晶硅栅8，在多晶硅栅8上设有钝化层6且所述钝化层6包裹多晶硅栅8的两侧，在N型源区5和P型体接触区6连接有源极金属9，其特征在于：在各P型基区3体内分别设有由N-型区11构成的阵列且所述阵列被P型基区3包裹在其内部，上表面与栅氧层7相分离，所述N-型区11始于N+型源区5沿沟道方向水平延伸至N型漂移区2，在器件栅宽方向上N-型区11与P型基区3间隔分布，且自然状态下N-型区11在P型基区3的辅助耗尽下恰好完全夹断。所述N-型区11上表面与栅氧层7之间的距离约为0.2-0.3μm。所述N-型区11厚度为150-250nm。所述N-型区11的掺杂浓度为1e16-4e17cm
-3。所述N-型区11的宽度与栅宽的比例为0.1-0.5:1。所述的被P型基区3包裹在其内部的N-型区11阵列可以不止一层，自然状态下各层N-型区11阵列在P型基区3的辅助耗尽下均恰好完全夹断。
2, a low on-resistance silicon carbide power semiconductor device, the low on-resistance silicon carbide power semiconductor device is an axisymmetric structure, comprising: an N-type substrate 1 in one of the N-type substrates 1 A drain metal 10 is connected to the side, an N-type drift region 2 is provided on the other side of the N-type substrate 1, and a pair of P-type base regions 3 are symmetrically disposed in the N-type drift region 2, and in each of the P-type base regions 3 A P+ type body contact region 4 and an N+ type source region 5 are respectively disposed, a gate oxide layer 7 is disposed on the surface of the N type drift region 2, and a polysilicon gate 8 is disposed on the surface of the gate oxide layer 7 on the polysilicon gate 8. A passivation layer 6 is disposed, and the passivation layer 6 wraps both sides of the polysilicon gate 8, and the source metal 9 is connected to the N-type source region 5 and the P-type body contact region 6, which is characterized in that each P-type base The array 3 is provided with an array of N-type regions 11 respectively, and the array is surrounded by the P-type base region 3, and the upper surface is separated from the gate oxide layer 7, and the N-type region 11 starts from N+. The source region 5 extends horizontally in the channel direction to the N-type drift region 2, and the N-type region 11 and the P-type base region 3 are spaced apart in the gate width direction of the device, and the N-type region 11 is in the P-type region in the natural state. Zone 3's auxiliary exhaustion just happens Pinch-off. The distance between the upper surface of the N-type region 11 and the gate oxide layer 7 is about 0.2-0.3 μm. The N-type region 11 has a thickness of 150-250 nm. The doping concentration of the N-type region 11 is 1e16-4e17 cm -3 . The ratio of the width of the N-type region 11 to the gate width is 0.1-0.5:1. The array of N-type regions 11 surrounded by the P-type base region 3 may have more than one layer. In the natural state, the array of N-type regions 11 of each layer is exactly complete under the auxiliary depletion of the P-type base region 3. Pinched.
本发明采用如下方法来制备(参照图8)：The present invention is prepared by the following method (refer to Fig. 8):
第一步，在N型衬底1的表面生长一层N型外延层漂移区2.1。In the first step, an N-type epitaxial layer drift region 2.1 is grown on the surface of the N-type substrate 1.
第二步，通过铝离子注入在N型外延层漂移区2.1中形成P型基区3.1。In the second step, a P-type base region 3.1 is formed in the drift region 2.1 of the N-type epitaxial layer by aluminum ion implantation.
第三步，在N型外延层漂移区2.1表面生长一层N-型外延层11。In the third step, an N-type epitaxial layer 11 is grown on the surface of the drift region 2.1 of the N-type epitaxial layer.
第四步，在N-型外延层11表面生长一层P型外延层3.2。In the fourth step, a P-type epitaxial layer 3.2 is grown on the surface of the N-type epitaxial layer 11.
第五步，通过铝离子注入形成P+型体接触区4。In the fifth step, the P + -type body contact region 4 is formed by aluminum ion implantation.
第六步，通过氮离子注入形成N+型源区5。In the sixth step, the N+ type source region 5 is formed by nitrogen ion implantation.
第七步，通过氮离子注入形成N型漂移区2.2，构成整个浓度一致的整个N型漂移区。In the seventh step, an N-type drift region 2.2 is formed by nitrogen ion implantation to form an entire N-type drift region of uniform concentration.
第八步，生长栅氧化层7。In the eighth step, the gate oxide layer 7 is grown.
第九步，淀积多晶硅，刻蚀出多晶硅栅8。In the ninth step, polysilicon is deposited and the polysilicon gate 8 is etched.
第十步，刻蚀电极接触区后淀积金属，再刻蚀金属引出电极，最后进行钝化处理。In the tenth step, after the electrode contact region is etched, the metal is deposited, and then the metal extraction electrode is etched, and finally passivation treatment is performed.
Claims (6)
- 一种低导通电阻的碳化硅功率半导体器件，所述低导通电阻的碳化硅功率半导体器件为轴对称结构，包括：N型衬底(1)，在N型衬底(1)的一侧连接有漏极金属(10)，在N型衬底(1)的另一侧设有N型漂移区(2)，在N型漂移区(2)中对称设置一对P型基区(3)，在各P型基区(3)中分别设有P+型体接触区(4)和N+型源区(5)，在N型漂移区(2)的表面设有栅氧层(7)，在栅氧层(7)的表面设有多晶硅栅(8)，在多晶硅栅(8)上设有钝化层(6)且所述钝化层(6)包裹多晶硅栅(8)的两侧，在N型源区(5)和P型体接触区(6)连接有源极金属(9)，其特征在于：在各P型基区(3)体内分别设有由N-型区(11)构成的阵列且所述阵列被P型基区(3)包裹在其内部，上表面与栅氧层(7)相分离，所述N-型区(11)始于N+型源区(5)沿沟道方向水平延伸至N型漂移区(2)，在器件栅宽方向上N-型区(11)与P型基区(3)间隔分布，且自然状态下N-型区(11)在P型基区(3)的辅助耗尽下恰好完全夹断。A low on-resistance silicon carbide power semiconductor device, the low on-resistance silicon carbide power semiconductor device being an axisymmetric structure comprising: an N-type substrate (1), and a N-type substrate (1) a drain metal (10) is connected to the side, an N-type drift region (2) is disposed on the other side of the N-type substrate (1), and a pair of P-type base regions are symmetrically disposed in the N-type drift region (2) ( 3) A P+ type body contact region (4) and an N+ type source region (5) are respectively disposed in each P type base region (3), and a gate oxide layer is provided on the surface of the N type drift region (2) (7) a polysilicon gate (8) on the surface of the gate oxide layer (7), a passivation layer (6) on the polysilicon gate (8) and a polysilicon gate (8) on the passivation layer (6) On both sides, the source metal (9) is connected to the N-type source region (5) and the P-type body contact region (6), and is characterized in that: N-type is provided in each of the P-type base regions (3). An array of regions (11) and the array is surrounded by a P-type base region (3), the upper surface being separated from the gate oxide layer (7), the N-type region (11) starting from an N+ source The region (5) extends horizontally in the channel direction to the N-type drift region (2), and the N-type region (11) and the P-type base region (3) are spaced apart in the gate width direction of the device, and the N-type is in a natural state. (11) just pinched off completely with the aid of the P-type base region (3) depletion.
- 根据权利要求1所述的低导通电阻的碳化硅功率半导体器件，其特征在于，所述N-型区(11)上表面与栅氧层(7)之间的距离约为0.2-0.3μm。The low on-resistance silicon carbide power semiconductor device according to claim 1, wherein a distance between an upper surface of said N-type region (11) and a gate oxide layer (7) is about 0.2-0.3 μm. .
- 根据权利要求1所述的低导通电阻的碳化硅功率半导体器件，其特征在于，所述N-型区(11)厚度为150-250nm。The low on-resistance silicon carbide power semiconductor device according to claim 1, wherein the N-type region (11) has a thickness of 150 to 250 nm.
- 根据权利要求1所述的低导通电阻的碳化硅功率半导体器件，其特征在于，所述N-型区(11)的掺杂浓度为1e16-4e17cm -3。 The low on-resistance silicon carbide power semiconductor device according to claim 1, wherein the N-type region (11) has a doping concentration of 1e16 to 4e17 cm -3 .
- 根据权利要求1所述的低导通电阻的碳化硅功率半导体器件，其特征在于，所述N-型区(11)的宽度与栅宽的比例为0.1-0.5:1。The low on-resistance silicon carbide power semiconductor device according to claim 1, wherein a ratio of a width of the N-type region (11) to a gate width is 0.1 to 0.5:1.
- 根据权利要求1所述的低导通电阻的碳化硅功率半导体器件，其特征在于，所述的被P型基区(3)包裹在其内部的N-型区(11)阵列可以不止一层，但自然状态下各层N-型区(11)阵列在P型基区(3)的辅助耗尽下均恰好完全夹断。The low on-resistance silicon carbide power semiconductor device according to claim 1, wherein said array of N-type regions (11) surrounded by a P-type base region (3) may have more than one layer. However, in the natural state, the array of N-type regions (11) of each layer is completely pinched off under the auxiliary depletion of the P-type base region (3).
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