JP6588340B2 - Nitride power device and manufacturing method thereof - Google Patents
Nitride power device and manufacturing method thereof Download PDFInfo
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- JP6588340B2 JP6588340B2 JP2015556386A JP2015556386A JP6588340B2 JP 6588340 B2 JP6588340 B2 JP 6588340B2 JP 2015556386 A JP2015556386 A JP 2015556386A JP 2015556386 A JP2015556386 A JP 2015556386A JP 6588340 B2 JP6588340 B2 JP 6588340B2
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- 150000004767 nitrides Chemical class 0.000 title claims description 144
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000010410 layer Substances 0.000 claims description 242
- 229910052710 silicon Inorganic materials 0.000 claims description 97
- 239000010703 silicon Substances 0.000 claims description 97
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 95
- 239000000758 substrate Substances 0.000 claims description 87
- 239000004065 semiconductor Substances 0.000 claims description 69
- 230000004888 barrier function Effects 0.000 claims description 28
- 229910002601 GaN Inorganic materials 0.000 claims description 22
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 20
- 230000006911 nucleation Effects 0.000 claims description 16
- 238000010899 nucleation Methods 0.000 claims description 16
- 229910002704 AlGaN Inorganic materials 0.000 claims description 6
- 238000003780 insertion Methods 0.000 claims description 6
- 230000037431 insertion Effects 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 6
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 5
- 229910004541 SiN Inorganic materials 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910004140 HfO Inorganic materials 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 description 33
- 239000000463 material Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 230000004048 modification Effects 0.000 description 8
- 238000012986 modification Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 230000002829 reductive effect Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000002441 reversible effect Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- -1 fluorine ions Chemical class 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003325 tomography Methods 0.000 description 1
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Description
本発明は、マイクロエレクトロニクス技術分野に属し、窒化物パワーデバイスおよび該窒化物パワーデバイスの製造方法に関し、特に、厚い空間電荷空乏領域を形成することが可能な半導体ドーピング複数層構造をＳｉ基板に導入することにより、大きな印加電圧に耐えることが可能になり、デバイスの破壊電圧を向上させる。 The present invention belongs to the field of microelectronics, and relates to a nitride power device and a method for manufacturing the nitride power device, and in particular, a semiconductor-doped multi-layer structure capable of forming a thick space charge depletion region is introduced into a Si substrate. By doing so, it becomes possible to withstand a large applied voltage, and the breakdown voltage of the device is improved.
第３世代の半導体材料である窒化ガリウム（ＧａＮ）は、大きなバンドギャップ、高い電子の飽和ドリフト速度、高い破壊電界強度、良い熱伝導性能などの特性を有するため、現在の研究のホットスポットとなっている。電子デバイスにおいて、シリコンおよびヒ化ガリウムよりも、窒化ガリウム材料が、高温、高周波、高電圧、およびハイパワーのデバイスの製造に好適であるため、窒化ガリウム基電子デバイスは、良い応用の見通しを持っている。 Gallium nitride (GaN), a third-generation semiconductor material, has characteristics such as a large bandgap, high electron saturation drift velocity, high breakdown electric field strength, and good thermal conductivity, making it a hot spot for current research. ing. In electronic devices, gallium nitride based electronic devices have good application prospects because gallium nitride materials are better suited for manufacturing high temperature, high frequency, high voltage, and high power devices than silicon and gallium arsenide. ing.
従来から、窒化ガリウムパワーデバイスは、サファイアまたは炭化ケイ素基板上において製作され、窒化ガリウムヘテロ接合の導電チャネルの特殊性およびプロセスの難しさの制限で、窒化ガリウムパワーデバイスは、基本的に平面構造であり、基板が厚く且つ破壊電界が高いため、デバイスは、横方向の破壊が一般的であり、例えば、フィールドプレート構造、ゲートとドレインとの距離の増加などのような幾つかの平面最適化技術によって、デバイスの破壊電圧を向上させることができる。しかし、サファイアおよび炭化ケイ素基板材料は、高価であり、且つ、大きいサイズの基板材料およびエピタキシャル層を実現しにくいので、窒化ガリウムパワーデバイスは、コストが高く、市場化が難しい。 Traditionally, gallium nitride power devices have been fabricated on sapphire or silicon carbide substrates, and due to the limitations of the gallium nitride heterojunction conductive channel and process difficulties, gallium nitride power devices are essentially planar structures. Because the substrate is thick and the breakdown field is high, the device is typically subject to lateral breakdown, for example, some planar optimization techniques such as field plate structure, increased gate to drain distance, etc. Thus, the breakdown voltage of the device can be improved. However, since sapphire and silicon carbide substrate materials are expensive and difficult to achieve large size substrate materials and epitaxial layers, gallium nitride power devices are expensive and difficult to market.
現在、大きいサイズのシリコン基板上に窒化ガリウムパワーデバイスを成長させる技術は、成熟しつつあり、且つ、コストが低く、窒化ガリウムパワーデバイスの市場化を推進する主流方向であり、トライオード構造の窒化ガリウムパワーデバイスを例として、その構成は、図１Ａに示すように、シリコン基板１と、窒化物核形成層２と、窒化物バッファ層３と、窒化物チャネル層４と、窒化物バリア層５と、誘電体パッシベーション層９と、ソース６、ドレイン７、およびゲート８が含まれる３つの電極と、を含む。シリコン材料自体の導電性および低い臨界電界に起因して、シリコン基窒化ガリウムパワーデバイスは、いずれも、飽和破壊電圧を有し、この飽和破壊電圧は、シリコン基板上に成長させた窒化物エピタキシャル層の厚さによって決まる。また、デバイスにおける静電気の蓄積によるＥＳＤ（静電気放電）を避け、および、回路において電圧のマッチングを実現するために、基板接地は、必ず避けられない選択であり、これにより、図１Ｂに示すように、シリコン基窒化ガリウムパワーデバイスは、基板が接地される場合の破壊電圧Ｖｂｒ１が、浮動接地の場合の破壊電圧Ｖｂｒ２より半分に減少し、高抵抗ＦＺシリコンを用いても、その電気抵抗率は、通常、１０４Ｏｈｍ.ｃｍを超えず、窒化物の電気抵抗率（＞１０９Ｏｈｍ.ｃｍ）より遥かに小さく、分圧の働きをすることができない。そこで、シリコン基板上の窒化物パワーデバイスの破壊電圧を向上させることは、現在、すぐに解決すべき課題である。 Currently, the technology for growing gallium nitride power devices on large silicon substrates is becoming mature, low cost, and the mainstream driving the commercialization of gallium nitride power devices. Taking the power device as an example, the configuration is as shown in FIG. 1A, and includes a silicon substrate 1, a nitride nucleation layer 2, a nitride buffer layer 3, a nitride channel layer 4, and a nitride barrier layer 5. , A dielectric passivation layer 9 and three electrodes including a source 6, a drain 7, and a gate 8. Due to the conductivity of the silicon material itself and the low critical electric field, all silicon-based gallium nitride power devices have a saturation breakdown voltage, which is a nitride epitaxial layer grown on a silicon substrate. It depends on the thickness. Further, in order to avoid ESD (electrostatic discharge) due to static electricity accumulation in the device and to realize voltage matching in the circuit, grounding the substrate is an inevitable choice, and as shown in FIG. 1B. In the silicon-based gallium nitride power device, the breakdown voltage Vbr1 when the substrate is grounded is reduced to half of the breakdown voltage Vbr2 when the substrate is floating, and even if high resistance FZ silicon is used, the electrical resistivity is Usually, it does not exceed 10 4 Ohm.cm and is much smaller than the electrical resistivity of nitride (> 10 9 Ohm.cm) and cannot act as a partial pressure. Therefore, improving the breakdown voltage of the nitride power device on the silicon substrate is a problem to be solved immediately.
エピタキシャル層の厚さを増加させることによって、シリコン基板窒化物高電圧デバイスの破壊電圧を向上させることができ、現在、シリコン材料上に窒化物エピタキシャル層を成長させる技術は成熟しつつあるが、シリコン材料と窒化物との間に巨大な格子不整合および熱的不整合が存在しているため、成長する窒化物エピタキシャル層の厚さが大幅に制限され、一般的に、約２μｍから４μｍ程度であり、厚すぎる窒化物エピタキシャル層を成長させるには、もっと長い時間が必要となり、コストを増大させ、スループットを低下させることになるうえに、エピタキシャル層の品質が悪くなり、反りまたはクラックが発生しやすく、プロセスの難しさを増大させ、歩留まりを低下させるなどに至る。 By increasing the thickness of the epitaxial layer, the breakdown voltage of the silicon substrate nitride high voltage device can be improved, and the technology for growing the nitride epitaxial layer on the silicon material is now mature, Due to the large lattice and thermal mismatches between the material and the nitride, the thickness of the growing nitride epitaxial layer is severely limited, typically in the order of 2 to 4 μm. In addition, growing a nitride epitaxial layer that is too thick requires a longer time, which increases costs, lowers throughput, degrades the quality of the epitaxial layer, and causes warping or cracking. Easily, increasing the difficulty of the process and reducing the yield.
基板が接地されると、デバイスの破壊電圧も縦方向の破壊で影響される。この縦方向の破壊電圧は、エピタキシャル層の耐えることが可能な電圧、およびシリコン基板の耐えることが可能な電圧によって決まる。従って、全体の縦方向の破壊電圧は、シリコン基板の耐電圧性の改善によって向上することができる。 When the substrate is grounded, the breakdown voltage of the device is also affected by the vertical breakdown. This longitudinal breakdown voltage depends on the voltage that the epitaxial layer can withstand and the voltage that the silicon substrate can withstand. Therefore, the overall breakdown voltage in the vertical direction can be improved by improving the voltage resistance of the silicon substrate.
シリコン基板の厚さは、一般的に一定であり、厚すぎると、コストを増大させるとともに、シリコン上の窒化物エピタキシャル層の品質に影響し、プロセスの難しさも増大させるので、基板の厚さを増加させることによりシリコン基板の耐電圧性を向上させることは、実行可能ではない。 The thickness of the silicon substrate is generally constant, and if it is too thick, it increases cost and affects the quality of the nitride epitaxial layer on the silicon and also increases the difficulty of the process. It is not feasible to improve the voltage resistance of the silicon substrate by increasing it.
シリコン半導体デバイスにおいて、シリコン材料で製作されたＰＮダイオードは、高い逆方向の印加電圧に耐えることができる。一般的に、シリコン基板において、ドーピングによってＮ型ドープ領域およびＰ型ドープ領域を形成し、２つのドープ領域の内部に１つのＰＮ接合が形成され、空間電荷空乏領域が形成され、空間電荷領域は、内部の導電電子および空穴がゼロに近似するまで非常に少なく、高抵抗領域に類似するものであり、破壊電界が高く、一定の印加電圧に耐えることができる。空間電荷領域は、耐えることが可能な電圧がその幅に関係し、空間電荷領域が広いほど、耐えることが可能な電圧が大きくなり、即ち、ＰＮダイオードの破壊電圧が大きくなる。空間電荷領域の幅は、ドーピング濃度および印加電圧による影響を受け、一般的に、印加電圧の増加につれて、空間電荷領域の幅が次第に大きくなり、ドーピング濃度が高い場合、空間電荷領域が狭いことに対し、同様の電圧下、ドーピング濃度が低い場合、空間電荷領域の幅が広く、より高い印加電圧に耐えることができる。Ｎ型ドープ領域およびＰ型ドープ領域の内部の電子および空穴がまったく空乏になると、空間電荷領域の幅は拡張することなく、印加電圧を引き続いて増加させると、空間電荷領域が破壊されてしまうことになる。シリコンドーピングプロセスが成熟して安定するものであり、異なる構成、異なる濃度のドーピング分布を形成することが可能であるので、異なる電圧に耐えることが可能なＰＮダイオードが生じている。 In silicon semiconductor devices, PN diodes made of silicon material can withstand high reverse applied voltages. In general, in a silicon substrate, an N-type doped region and a P-type doped region are formed by doping, one PN junction is formed inside the two doped regions, a space charge depletion region is formed, and the space charge region is The internal conductive electrons and vacancies are very few until close to zero, similar to the high resistance region, have a high breakdown electric field, and can withstand a constant applied voltage. In the space charge region, the voltage that can be endured is related to its width, and the wider the space charge region, the larger the voltage that can be endured, that is, the breakdown voltage of the PN diode increases. The width of the space charge region is affected by the doping concentration and the applied voltage. Generally, as the applied voltage increases, the width of the space charge region gradually increases, and when the doping concentration is high, the space charge region is narrow. On the other hand, when the doping concentration is low under the same voltage, the space charge region is wide and can withstand a higher applied voltage. If the electrons and vacancies inside the N-type doped region and the P-type doped region are completely depleted, the space charge region will not be expanded, and if the applied voltage is continuously increased, the space charge region will be destroyed. It will be. Since the silicon doping process is mature and stable and different configurations and different concentrations of doping distribution can be formed, PN diodes are created that can withstand different voltages.
これに鑑み、エピタキシャルドーピングまたはイオン注入によって、シリコン基板の内部に、厚さが薄い横方向のＰ型ドープ半導体層およびＮ型ドープ半導体層を導入することができる。Ｐ型ドープ半導体層およびＮ型ドープ半導体層の内部に空間電荷領域が形成され、空間電荷領域の内部の導電電子および空穴がまったく空乏になり、空間電荷領域は、基本的に絶縁であり、高抵抗領域に近似するものであり、破壊電界が高く、一定の印加電圧に耐えることができる。空間電荷領域は、耐えることが可能な電圧が空間電荷領域の幅に関係し、空間電荷領域が広いほど、耐えることが可能な電圧が大きい。逆方向の印加電圧の増加につれて、空間電荷領域は、絶えず広くなり、耐えることが可能な電圧も絶えず大きくなり、半導体ドーピング層が薄いため、ドープ半導体層全体の内部の電子および空穴がまったく空乏になり、ドープ半導体領域全体は、高抵抗領域となり、高い印加電圧に耐えることが可能になる。複数層のＮ型半導体層およびＰ型半導体層がある場合、複数層の空間電荷空乏領域が形成され、且つ、１つの厚い空間電荷空乏領域が構成され、とても高い印加電圧に耐えることができ、実際には、デバイスの耐えるべき電圧に応じて、ドープ半導体層の具体的な構造を決定することができる。 In view of this, a lateral thin P-type doped semiconductor layer and N-type doped semiconductor layer can be introduced into the silicon substrate by epitaxial doping or ion implantation. A space charge region is formed inside the P-type doped semiconductor layer and the N-type doped semiconductor layer, conductive electrons and vacancies inside the space charge region are completely depleted, and the space charge region is basically insulating, It approximates a high resistance region, has a high breakdown electric field, and can withstand a constant applied voltage. The voltage that can withstand the space charge region is related to the width of the space charge region, and the wider the space charge region, the larger the voltage that can be withstand. As the applied voltage increases in the reverse direction, the space charge region is constantly widened, the voltage that can be withstood is constantly increased, and the semiconductor doping layer is thin, so the electrons and vacancies inside the entire doped semiconductor layer are completely depleted. Thus, the entire doped semiconductor region becomes a high resistance region and can withstand a high applied voltage. When there are a plurality of N-type semiconductor layers and P-type semiconductor layers, a plurality of space charge depletion regions are formed, and one thick space charge depletion region is formed, which can withstand a very high applied voltage, In practice, the specific structure of the doped semiconductor layer can be determined according to the voltage that the device must withstand.
シリコン基板に導入されたＰ型ドープ半導体層およびＮ型ドープ半導体層によって形成された空間電荷領域は、導電シリコン基板に１つの耐高電圧層が挿入されることに相当し、シリコン基板の耐電圧性を向上させ、さらに、デバイス全体の破壊電圧を向上させ、特に、シリコン基板が接地される場合に、ドレインと基板電極との間の縦方向の破壊電圧を大幅に向上させる。 The space charge region formed by the P-type doped semiconductor layer and the N-type doped semiconductor layer introduced into the silicon substrate corresponds to the insertion of one high voltage layer into the conductive silicon substrate. And the breakdown voltage of the entire device is improved. In particular, when the silicon substrate is grounded, the breakdown voltage in the vertical direction between the drain and the substrate electrode is greatly improved.
本発明は、空間電荷空乏領域を形成することが可能な半導体ドーピング複数層構造をシリコン基板に導入することにより実現可能な、高い破壊電圧に耐える窒化物パワーデバイスを提供することを目的とする。この半導体ドーピング複数層構造は、薄いｎ型シリコン層およびｐ型シリコン層を交互に繰り返すことにより構成され、一定の印加電圧下で、半導体ドーピング層の各層ごとに空間電荷空乏領域が生じ、半導体ドーピング複数層構造全体で１つの厚い空間電荷空乏領域を形成し、大きな印加電圧に耐えることができ、半導体ドーピング複数層構造が厚いほど、形成される空間電荷領域が厚くなり、耐えることが可能な電圧降下が高くなる。また、本発明は、上記窒化物パワーデバイスの製造方法も提供することを他の目的とする。 An object of the present invention is to provide a nitride power device that can withstand a high breakdown voltage that can be realized by introducing a semiconductor-doped multi-layer structure capable of forming a space charge depletion region into a silicon substrate. This semiconductor-doped multi-layer structure is formed by alternately repeating thin n-type silicon layers and p-type silicon layers, and a space charge depletion region is generated in each layer of the semiconductor doping layer under a constant applied voltage. One thick space charge depletion region can be formed in the entire multi-layer structure and can withstand a large applied voltage. The thicker the semiconductor-doped multi-layer structure, the thicker the space charge region formed and the voltage that can withstand The descent becomes higher. Another object of the present invention is to provide a method for manufacturing the nitride power device.
本発明の一局面によれば、窒化物パワーデバイスが提供され、前記窒化物パワーデバイスは、空間電荷空乏領域を形成することが可能な半導体ドーピング複数層構造を含むシリコン基板と、上記シリコン基板上におけるエピタキシャル複数層構造と、前記エピタキシャル複数層構造上に形成される電極と、を含み、該エピタキシャル複数層構造は、少なくとも、窒化物核形成層と、前記窒化物核形成層上に形成される窒化物バッファ層と、前記窒化物バッファ層上に形成される窒化物チャネル層と、を含み、前記窒化物パワーデバイスがトライオード構造である場合、前記電極は、ソースおよびドレイン、並びに、ソースとドレインとの間のゲートを含み、前記窒化物パワーデバイスがダイオード構造である場合、前記電極は、正極および負極を含む。 According to one aspect of the present invention, a nitride power device is provided, the nitride power device including a silicon substrate including a semiconductor-doped multi-layer structure capable of forming a space charge depletion region, and the silicon substrate on the silicon substrate. And an electrode formed on the epitaxial multilayer structure, wherein the epitaxial multilayer structure is formed on at least the nitride nucleation layer and the nitride nucleation layer When the nitride power device has a triode structure, the electrode includes a source and a drain, and a source and a drain, including a nitride buffer layer and a nitride channel layer formed on the nitride buffer layer. When the nitride power device has a diode structure, the electrode includes a positive electrode and a negative electrode. Including the.
好ましくは、上記窒化物パワーデバイスにおいて、上記半導体ドーピング複数層構造は、１層のｎ型半導体層および１層のｐ型半導体層で構成されるｐｎ接合であってよく、１つの空間空乏領域を含み、もしくは、ｎ型半導体層およびｐ型半導体層を交互に繰り返すことにより構成される複数層構造であってもよく、複数のｐｎ接合、即ち、複数の空間空乏領域を含む。 Preferably, in the nitride power device, the semiconductor-doped multi-layer structure may be a pn junction including one n-type semiconductor layer and one p-type semiconductor layer. Alternatively, it may be a multi-layer structure configured by alternately repeating n-type semiconductor layers and p-type semiconductor layers, and includes a plurality of pn junctions, that is, a plurality of space depletion regions.
シリコン基板が接地される場合、窒化物パワーデバイスには、正方向のバイアス電圧を印加してもよいし、逆方向のバイアス電圧を印加してもよい、ということを考慮すると、単層のｎ型半導体および単層のｐ型半導体で、双方向の電圧降下を引き受けることができない。このため、実用の基板構造は、複数層のｎ型およびｐ型半導体層で構成する必要がある。 Considering that when the silicon substrate is grounded, the nitride power device may be applied with a forward bias voltage or a reverse bias voltage. Bi-directional voltage drop cannot be assumed in a p-type semiconductor and a single-layer p-type semiconductor. For this reason, a practical substrate structure must be composed of a plurality of n-type and p-type semiconductor layers.
好ましくは、上記窒化物パワーデバイスにおいて、上記半導体ドーピング複数層構造におけるｎ型半導体層およびｐ型半導体層の厚さが２ｎｍより大きく、該半導体ドーピング複数層構造におけるｎ型半導体層およびｐ型半導体層がそれぞれｎ−型半導体およびｐ−型半導体であり、半導体ドーピング複数層構造全体の層数、厚さ、およびドーピング濃度は、耐えるべき電圧に応じて調節することができる。
好ましくは、上記窒化物パワーデバイスにおいて、上記半導体ドーピング複数層構造の製作方法がエピタキシャル成長またはイオン注入である。
Preferably, in the nitride power device, the thickness of the n-type semiconductor layer and the p-type semiconductor layer in the semiconductor-doped multi-layer structure is greater than 2 nm, and the n-type semiconductor layer and the p-type semiconductor layer in the semiconductor-doped multi-layer structure Are an n-type semiconductor and a p-type semiconductor, respectively, and the number of layers, the thickness, and the doping concentration of the entire semiconductor-doped multilayer structure can be adjusted according to the voltage to be withstood.
Preferably, in the nitride power device, the method for producing the semiconductor-doped multi-layer structure is epitaxial growth or ion implantation.
好ましくは、上記窒化物パワーデバイスにおいて、上記半導体ドーピング複数層構造は、シリコン基板のトップ層、または内部、または裏面、あるいは、それらの任意の組み合わせに形成することが可能である。 Preferably, in the nitride power device, the semiconductor-doped multi-layer structure can be formed on the top layer, or the inside, or the back surface of the silicon substrate, or any combination thereof.
好ましくは、上記窒化物パワーデバイスにおいて、上記窒化物チャネル層上に窒化物バリア層が設けられており、窒化物チャネル層と窒化物バリア層との界面に二次元電子ガスが形成されている。
好ましくは、上記窒化物パワーデバイスには、上記バリア層上における誘電体層をさらに含む。
Preferably, in the nitride power device, a nitride barrier layer is provided on the nitride channel layer, and a two-dimensional electron gas is formed at an interface between the nitride channel layer and the nitride barrier layer.
Preferably, the nitride power device further includes a dielectric layer on the barrier layer.
好ましくは、上記窒化物パワーデバイスにおいて、上記誘電体層は、ＳｉＮ、ＳｉＯ２、ＳｉＯＮ、Ａｌ２Ｏ３、ＨｆＯ２、ＨｆＡｌＯｘのうちの１つを含み、もしくは、それらの任意の組み合わせである。
好ましくは、上記窒化物パワーデバイスには、上記バリア層上における窒化ガリウムキャップ層をさらに含む。
Preferably, in the nitride power device, the dielectric layer includes one of SiN, SiO 2 , SiON, Al 2 O 3 , HfO 2 , HfAlOx, or any combination thereof.
Preferably, the nitride power device further includes a gallium nitride cap layer on the barrier layer.
好ましくは、上記窒化物パワーデバイスには、上記バリア層と上記チャネル層との間におけるＡｌＮ挿入層をさらに含む。
好ましくは、上記窒化物パワーデバイスには、上記バッファ層と上記チャネル層との間におけるＡｌＧａＮバックバリア層をさらに含む。
好ましくは、上記窒化物パワーデバイスにおいて、上記ゲートの下に誘電体層を有する。
Preferably, the nitride power device further includes an A 1 N insertion layer between the barrier layer and the channel layer.
Preferably, the nitride power device further includes an Al GaN back barrier layer between the buffer layer and the channel layer.
Preferably, the nitride power device has a dielectric layer under the gate.
好ましくは、上記窒化物パワーデバイスにおいて、上記ゲートはゲートフィールドプレートを有し、および／または、上記ドレインはドレインフィールドプレートを有する。 Preferably, in the nitride power device, the gate has a gate field plate and / or the drain has a drain field plate.
本発明の一局面によれば、窒化物パワーデバイスを製造するための方法が提供され、前記方法は、空間電荷空乏領域を形成することが可能な半導体ドーピング複数層構造をシリコン基板に導入するステップと、上記半導体ドーピング複数層構造を含むシリコン基板上に窒化物核形成層を成長させるステップと、上記窒化物核形成層上に窒化物バッファ層を成長させるステップと、上記窒化物バッファ層上に窒化物チャネル層を成長させるステップと、上記窒化物チャネル層上に接触電極を形成するステップと、を含み、前記窒化物パワーデバイスがトライオード構造である場合、前記電極は、ソースおよびドレイン、並びに、ソースとドレインとの間のゲートを含み、前記窒化物パワーデバイスがダイオード構造である場合、前記電極は、正極および負極を含む。 According to one aspect of the present invention, a method is provided for fabricating a nitride power device, the method comprising introducing a semiconductor doped multilayer structure capable of forming a space charge depletion region into a silicon substrate. Growing a nitride nucleation layer on the silicon substrate including the semiconductor-doped multi-layer structure, growing a nitride buffer layer on the nitride nucleation layer, and on the nitride buffer layer Growing a nitride channel layer; and forming a contact electrode on the nitride channel layer, wherein if the nitride power device has a triode structure, the electrode comprises a source and a drain; and If the nitride power device has a diode structure, including a gate between the source and drain, the electrode is positive And a negative electrode.
好ましくは、上記の窒化物パワーデバイスを製造するための方法において、上記半導体ドーピング複数層構造の製作方法がエピタキシャル成長またはイオン注入である。 Preferably, in the method for manufacturing the nitride power device, the method for manufacturing the semiconductor-doped multi-layer structure is epitaxial growth or ion implantation.
以下、図面を参照して本発明の具体的な実施形態を説明することにより、本発明の上述した特徴、利点、および目的をもっと良く了解させることが可能になると信じる。 The following description of specific embodiments of the invention with reference to the drawings is believed to enable a better understanding of the above features, advantages and objects of the invention.
背景技術に記載されたように、従来のシリコン基板窒化物パワーデバイスは、シリコン基板が接地された後、デバイス全体の縦方向の破壊電圧が元の半分に減少するため、デバイスの電圧破壊の確率を大幅に増大させる。 As described in the background art, the conventional silicon substrate nitride power device has a probability of voltage breakdown of the device because the vertical breakdown voltage of the entire device is reduced to half after the silicon substrate is grounded. Is greatly increased.
本発明では、従来技術の欠陥に基づき、高い破壊電圧に耐えることが可能な窒化物パワーデバイスを提供している。この窒化物パワーデバイスでは、シリコン基板において、ｐ型シリコン層およびｎ型シリコン層を交互に配列したｐｎ接合が製作される。印加電圧が窒化物パワーデバイスに印加される場合、ｐｎ接合ごとに、１つの空間電荷空乏領域が形成され、１つまたは複数の空間電荷空乏領域の重ね合わせによって、デバイス全体の破壊電圧を大幅に向上させ、デバイスが電圧により破壊されるリスクを低減させる。
以下、図面を参照して、本発明の解決手段を詳しく説明する。
The present invention provides a nitride power device that can withstand high breakdown voltages based on prior art defects. In this nitride power device, a pn junction in which p-type silicon layers and n-type silicon layers are alternately arranged is manufactured on a silicon substrate. When an applied voltage is applied to the nitride power device, one space charge depletion region is formed for each pn junction, and the superposition of one or more space charge depletion regions significantly increases the breakdown voltage of the entire device. Improve and reduce the risk that the device will be destroyed by voltage.
Hereinafter, the solution means of the present invention will be described in detail with reference to the drawings.
図２Ａを参照されたい。図２Ａは、本発明の第１実施形態のシリコン基板上の窒化物パワーデバイスの構成を示す図である。本実施形態では、トライオード構造を有する電界効果トランジスタを用いて説明する。この窒化物パワーデバイスは、空間電荷空乏領域を形成することが可能な半導体ドーピング複数層構造１０を含むシリコン基板１と、上記シリコン基板１上におけるエピタキシャル複数層構造と、を含む。該エピタキシャル複数層構造は、窒化物核形成層２と、ＧａＮまたはＡｌＮまたは他の窒化物を含み、基板材料と高品質窒化物エピタキシャル層とをマッチングする働きをして、上方の窒化ガリウム／窒化アルミニウムガリウムからなるヘテロ接合の結晶体品質、表面トボグラフィ、および電気的性質などのパラメータに影響するバッファ層３と、バッファ層３上に成長させ、アンドープＧａＮ層を含むチャネル層４と、チャネル層４上に成長させ、ＡｌＧａＮまたは他の窒化物を含み、チャネル層４とともに半導体ヘテロ接合構造を構成して、界面において高濃度の二次元電子ガスを形成し、ＧａＮチャネル層のヘテロ接合の界面において導電チャネルを生じさせるバリア層５と、バリア層５上に堆積され、材料表面をパッシベーションするための、ＳｉＮ、ＳｉＯ２、ＳｉＯＮ、Ａｌ２Ｏ３、ＨｆＯ２、ＨｆＡｌＯｘのうちの１つを含み、もしくは、それらの任意の組み合わせである誘電体層９と、を含む。ソース６とドレイン７との間の領域において、誘電体層がエッチングされてノッチを形成し、その後、金属を堆積してゲート８が形成される。本発明では、シリコン基板において、空間電荷空乏領域を形成することが可能な半導体ドーピング複数層構造１０が導入され、この半導体ドーピング複数層構造１０は、本発明の革新的なものであり、ｐ型半導体層およびｎ型半導体層で構成されるｐｎ接合、もしくは、複数層のｐ型半導体層およびｎ型半導体層を交互に繰り返すことにより構成される複数のｐｎ接合である。半導体層は薄く、厚さが一般的に２ｎｍより大きく、エピタキシャル成長またはイオン注入によって形成することができる。半導体ドーピング複数層構造全体の層数、厚さ、およびドーピング濃度は、耐えるべき電圧に応じて調節することができ、ｎ型およびｐ型半導体のドーピング濃度が低いように、即ち、ｎ−型およびｐ−型半導体が形成されるようにしてもよい。ドレインに正方向の電圧が印加されて、基板が接地される場合、ｐｎ接合ごとに空間電荷空乏領域が生じ、半導体ドーピング複数層構造全体で１つの厚い空間電荷空乏領域を形成し、大きな電圧降下に耐えることが可能になる。このような方法によって、デバイスの破壊電圧が大幅に向上する。説明すべきものとして、本実施形態で例示しているパワーデバイスが電界効果トランジスタであるので、基板上におけるエピタキシャル複数層構造には、チャネル層上におけるバリア層、およびバリア層の表面における誘電体層などが含まれるが、パワーデバイスは、他の機能を有する半導体デバイスであってもよい。このため、本発明として、エピタキシャル複数層構造は、特定の機能を有する半導体デバイスの実現のみを目的とする場合、少なくとも、核形成層と、バッファ層と、窒化物チャネル層と、を含む。 See FIG. 2A. FIG. 2A is a diagram showing a configuration of a nitride power device on a silicon substrate according to the first embodiment of the present invention. In the present embodiment, description will be made using a field effect transistor having a triode structure. The nitride power device includes a silicon substrate 1 including a semiconductor-doped multi-layer structure 10 capable of forming a space charge depletion region, and an epitaxial multi-layer structure on the silicon substrate 1. The epitaxial multi-layer structure includes a nitride nucleation layer 2 and GaN or A 1 N or other nitride, which serves to match the substrate material and the high quality nitride epitaxial layer to form an upper gallium nitride layer. / Buffer layer 3 affecting parameters such as crystal quality, surface tomography, and electrical properties of heterojunction made of aluminum gallium nitride, channel layer 4 grown on buffer layer 3 and including undoped GaN layer, channel Growing on layer 4 and including AlGaN or other nitride, forming a semiconductor heterojunction structure with channel layer 4 to form a high concentration two-dimensional electron gas at the interface, and interface of heterojunction of GaN channel layer A barrier layer 5 that produces a conductive channel in and a material layer deposited on the barrier layer 5 and passivated Because of, including SiN, SiO 2, SiON, include one of Al 2 O 3, HfO 2, HfAlOx, or a dielectric layer 9 any combination thereof, the. In the region between the source 6 and the drain 7, the dielectric layer is etched to form a notch, and then a metal is deposited to form the gate 8. In the present invention, a semiconductor-doped multi-layer structure 10 capable of forming a space charge depletion region in a silicon substrate is introduced. This semiconductor-doped multi-layer structure 10 is an innovative one of the present invention and is p-type. It is a pn junction constituted by a semiconductor layer and an n-type semiconductor layer, or a plurality of pn junctions constituted by alternately repeating a plurality of p-type semiconductor layers and n-type semiconductor layers. The semiconductor layer is thin and has a thickness generally greater than 2 nm and can be formed by epitaxial growth or ion implantation. The overall number, thickness, and doping concentration of the semiconductor doped multilayer structure can be adjusted according to the voltage to be withstood so that the doping concentration of the n-type and p-type semiconductors is low, i.e. n-type and A p-type semiconductor may be formed. When a positive voltage is applied to the drain and the substrate is grounded, a space charge depletion region occurs at each pn junction, forming one thick space charge depletion region in the entire semiconductor doped multi-layer structure, and a large voltage drop It becomes possible to endure. By such a method, the breakdown voltage of the device is greatly improved. Since the power device illustrated in the present embodiment is a field effect transistor, the epitaxial multilayer structure on the substrate includes a barrier layer on the channel layer, a dielectric layer on the surface of the barrier layer, and the like. However, the power device may be a semiconductor device having other functions. Therefore, as the present invention, the epitaxial multilayer structure includes at least a nucleation layer, a buffer layer, and a nitride channel layer when the purpose is to realize a semiconductor device having a specific function.
（参考例）
図２Ｂは、本発明の第１実施形態の１つの変形であり、図２Ａと異なる点がシリコン基板１にある。該シリコン基板１は、低濃度ドープのＰ−シリコンおよびｎ型シリコンで構成される。ドレインに正方向の電圧が印加されて、基板が接地される場合、該シリコン基板１は、逆バイアスのＰＮ接合に類似するものであり、空間電荷空乏領域が形成され、一定の電圧降下に耐えることが可能になり、デバイスの破壊電圧を向上させる。
(Reference example)
FIG. 2B is one modification of the first embodiment of the present invention, and the silicon substrate 1 is different from FIG. 2A. The silicon substrate 1 is composed of lightly doped P-silicon and n-type silicon. When a positive voltage is applied to the drain and the substrate is grounded, the silicon substrate 1 is similar to a reverse-biased PN junction, and a space charge depletion region is formed to withstand a constant voltage drop. It is possible to improve the breakdown voltage of the device.
（参考例）
図２Ｃは、本発明の第１実施形態の他の変形であり、図２Ａおよび図２Ｂと異なる点がシリコン基板１にある。該シリコン基板１は、３層構造を有し、高濃度ドープのｐ＋シリコン、低濃度ドープのｐ−シリコン、およびｎ型シリコンで構成される。該シリコン基板１の機能は、図２Ａおよび図２Ｂにおけるシリコン基板１の機能と同様であり、ここで説明を省略する。
(Reference example)
FIG. 2C shows another modification of the first embodiment of the present invention. The silicon substrate 1 is different from FIGS. 2A and 2B. The silicon substrate 1 has a three-layer structure and is composed of highly doped p + silicon, lightly doped p-silicon, and n-type silicon. The function of the silicon substrate 1 is the same as that of the silicon substrate 1 in FIGS. 2A and 2B, and the description thereof is omitted here.
（参考例）
図３は、本発明の第１実施形態の１つの変形であり、直接にシリコン基板のトップ層にエピタキシャル成長またはドーピングのプロセスを行うことにより、半導体ドーピング複数層構造がシリコン基板のトップ層に位置するようにし、窒化物核形成層２およびバッファ層３などを直接に半導体ドーピング複数層構造上に成長させることができ、図２におけるシリコン基板の内部に位置する半導体ドーピング複数層構造に比べると、この構造の製造プロセスが相対的に簡単化される。
(Reference example)
FIG. 3 is a variation of the first embodiment of the present invention, in which a semiconductor-doped multi-layer structure is located in the top layer of the silicon substrate by performing an epitaxial growth or doping process directly on the top layer of the silicon substrate. Thus, the nitride nucleation layer 2 and the buffer layer 3 and the like can be directly grown on the semiconductor-doped multi-layer structure, compared with the semiconductor-doped multi-layer structure located inside the silicon substrate in FIG. The manufacturing process of the structure is relatively simplified.
図４は、本発明の第１実施形態の他の変形であり、直接にシリコン基板の裏面にエピタキシャル成長またはドーピングのプロセスを行うことにより、半導体ドーピング複数層構造がシリコン基板の裏面に位置するようにし、図３におけるシリコン基板のトップ層に位置する半導体ドーピング複数層構造に比べると、窒化物核形成層２およびバッファ層３などを直接に半導体ドーピング複数層構造上に成長させるプロセスの難しさを低減させる。 FIG. 4 shows another modification of the first embodiment of the present invention, in which the epitaxial growth or doping process is performed directly on the back surface of the silicon substrate so that the semiconductor-doped multi-layer structure is located on the back surface of the silicon substrate. Compared to the semiconductor-doped multi-layer structure located in the top layer of the silicon substrate in FIG. 3, the difficulty of the process of growing the nitride nucleation layer 2 and the buffer layer 3 directly on the semiconductor-doped multi-layer structure is reduced. Let
図５は、本発明の第１実施形態の他の変形である。一般的に、半導体ドーピング複数層構造の層数および厚さは、耐えるべき電圧によって決まり、印加電圧が高くない場合、半導体ドーピング複数層構造は、厚すぎることが必要ではなく、プロセスは、簡単化することができる。図５に示すように、該半導体ドーピング複数層構造１０は、１層のｎ型半導体および１層のｐ型半導体で構成される。ここで、ｎ型半導体層は、最もトップ層に位置し、窒化物エピタキシャル層に接近する。ｎ型半導体層は、厚い低濃度ドープ半導体層であってもよく、ｐ型半導体層は、薄い高濃度ドープ半導体層であってもよい。ドレインに正方向の電圧が印加されて、基板が接地される場合、該半導体ドーピング双層構造は、逆バイアスのＰＮ接合に類似するものであり、空間電荷空乏領域が形成され、一定の電圧降下に耐えることが可能になり、デバイスの破壊電圧を向上させる。該半導体ドーピング双層構造は、シリコン基板のトップ層または裏面に位置してもよい。
該第１実施形態の窒化物パワーデバイスの製造において、
FIG. 5 is another modification of the first embodiment of the present invention. In general, the number and thickness of layers in a semiconductor-doped multilayer structure is determined by the voltage to withstand, and if the applied voltage is not high, the semiconductor-doped multilayer structure does not need to be too thick and the process is simplified can do. As shown in FIG. 5, the semiconductor-doped multi-layer structure 10 is composed of one layer of n-type semiconductor and one layer of p-type semiconductor. Here, the n-type semiconductor layer is located at the top layer and approaches the nitride epitaxial layer. The n-type semiconductor layer may be a thick lightly doped semiconductor layer, and the p-type semiconductor layer may be a thin highly doped semiconductor layer. When a positive voltage is applied to the drain and the substrate is grounded, the semiconductor-doped bilayer structure is similar to a reverse-biased PN junction, a space charge depletion region is formed, and a constant voltage drop It is possible to withstand and improve the breakdown voltage of the device. The semiconductor doping bilayer structure may be located on the top layer or the back surface of the silicon substrate.
In manufacturing the nitride power device of the first embodiment,
空間電荷空乏領域を形成することが可能な半導体ドーピング複数層構造をシリコン基板に導入するステップと、上記半導体ドーピング複数層構造を含むシリコン基板上に窒化物核形成層を成長させるステップと、上記窒化物核形成層上に窒化物バッファ層を成長させるステップと、上記窒化物バッファ層上に窒化物チャネル層を成長させるステップと、上記窒化物チャネル層上に接触電極を形成するステップと、を含む。 Introducing a semiconductor doped multilayer structure capable of forming a space charge depletion region into a silicon substrate; growing a nitride nucleation layer on the silicon substrate including the semiconductor doped multilayer structure; Growing a nitride buffer layer on the nucleation layer; growing a nitride channel layer on the nitride buffer layer; and forming a contact electrode on the nitride channel layer. .
半導体ドーピング複数層構造については、エピタキシャル成長またはイオン注入によって、該半導体ドーピング複数層構造をシリコン基板の内部、トップ表面、または裏面に製作し、所要の破壊電圧の多少に応じて、該半導体ドーピング複数層構造の層数および厚さを決定することができる。 For a semiconductor-doped multi-layer structure, the semiconductor-doped multi-layer structure is fabricated on the inside, top surface, or back surface of a silicon substrate by epitaxial growth or ion implantation, and the semiconductor-doped multi-layer structure is formed depending on the required breakdown voltage. The number of layers and the thickness of the structure can be determined.
（参考例）
図６は、本発明の第２実施形態のシリコン基板上の窒化物パワーデバイスの構成を示す図である。該実施形態では、ダイオード構造を有するダイオードデバイスを用いて説明する。窒化物ダイオードデバイスのシリコン基板に半導体ドーピング複数層構造を導入することにより、ダイオードの逆方向の破壊電圧を向上させることができる。ここで、電極８は、ショットキー接合であり、ダイオードの正極とされ、電極７は、オーム接触であり、ダイオードの負極とされる。
(Reference example)
FIG. 6 is a diagram showing a configuration of a nitride power device on a silicon substrate according to the second embodiment of the present invention. The embodiment will be described using a diode device having a diode structure. By introducing a semiconductor-doped multi-layer structure into the silicon substrate of a nitride diode device, the breakdown voltage in the reverse direction of the diode can be improved. Here, the electrode 8 is a Schottky junction and is a positive electrode of the diode, and the electrode 7 is an ohmic contact and is a negative electrode of the diode.
図７は、本発明の第３実施形態のシリコン基板上の窒化物パワーデバイスの構成を示す図である。該実施形態では、他のトライオード構造のＭＯＳＦＥＴデバイスを用いて説明する。該ＭＯＳＦＥＴデバイスは、窒化物ｎチャネルＭＯＳＦＥＴデバイスであり、該デバイスのシリコン基板に半導体ドーピング複数層構造を導入することにより、デバイスの破壊電圧を大幅に向上させる。窒化物チャネル層のソースおよびドレインの下方の領域は、ｎ型高濃度ドープ領域であり、一般的にシリコンがドーピングされ、ゲートの下方の領域は、ｐ型低濃度ドープであり、一般的にマグネシウムがドーピングされ、ゲート金属の下の誘電体層は、一般的に、ＳｉＯ２、ＳｉＮ、ＡｌＮ、Ａｌ２Ｏ３、または他の絶縁誘電体層である。 FIG. 7 is a diagram showing a configuration of a nitride power device on a silicon substrate according to the third embodiment of the present invention. In the present embodiment, description will be made using another MOSFET device having a triode structure. The MOSFET device is a nitride n-channel MOSFET device, which significantly improves the breakdown voltage of the device by introducing a semiconductor doped multi-layer structure into the silicon substrate of the device. The region below the source and drain of the nitride channel layer is an n-type heavily doped region, typically doped with silicon, and the region below the gate is p-type lightly doped, typically magnesium. The dielectric layer under the gate metal is typically SiO 2 , SiN, AlN, Al 2 O 3 , or other insulating dielectric layer.
図８は、本発明の第４実施形態のシリコン基板上の窒化物パワーデバイスの構成を示す図である。バリア層上にＧａＮキャップ層１１を成長させることにより、ＡｌＧａＮバリア層の材料表面は、欠陥状態密度および表面状態密度が大きいため、多くの電子が捕獲され、チャネルにおける二次元電子ガスに影響を与え、デバイスの特性および信頼性を低減する。バリア層の表面に１層のＧａＮを成長させて保護層とすることにより、バリア層の材料表面の欠陥状態および表面状態によるデバイスの特性への影響を効果的に減少することができる。 FIG. 8 is a diagram showing a configuration of a nitride power device on a silicon substrate according to the fourth embodiment of the present invention. By growing the GaN cap layer 11 on the barrier layer, the material surface of the AlGaN barrier layer has a large defect state density and a large surface state density, so that many electrons are captured and affect the two-dimensional electron gas in the channel. Reduce device characteristics and reliability. By growing a single layer of GaN on the surface of the barrier layer to form a protective layer, it is possible to effectively reduce the influence of the defect state and surface state of the material of the barrier layer on the device characteristics.
図９は、本発明の第５実施形態のシリコン基板上の窒化物パワーデバイスの構成を示す図である。バリア層とチャネル層との間にＡｌＮ挿入層１２を導入することにより、ＡｌＮのバンドギャップが非常に高いので、より効果的に電子をヘテロ接合のポテンシャル井戸に制限することができ、二次元電子ガスの濃度を向上させ、また、ＡｌＮ挿入層によれば、導電チャネルとＡｌＧａＮバリア層とが分離され、バリア層による電子への散乱効果が低減され、これにより、電子移動度を高めて、デバイス全体の特性を向上させることができる。 FIG. 9 is a diagram showing a configuration of a nitride power device on a silicon substrate according to the fifth embodiment of the present invention. By introducing the AlN insertion layer 12 between the barrier layer and the channel layer, the band gap of A 1 N is very high, so that electrons can be more effectively limited to the potential well of the heterojunction. Dimensional electron gas concentration is improved, and according to the AlN insertion layer, the conductive channel and the AlGaN barrier layer are separated, and the scattering effect on the electrons by the barrier layer is reduced, thereby increasing the electron mobility. The characteristics of the entire device can be improved.
図１０は、本発明の第６実施形態のシリコン基板上の窒化物パワーデバイスの構成を示す図である。バッファ層とチャネル層との間にＡｌＧａＮバックバリア層１３が導入される。一定の印加電圧下では、チャネル内の電子がバッファ層に入ることになり、特に、短チャネルデバイスにおいて、このような現象がより深刻になることで、ゲートによるチャネル電子への制御が相対的に弱くなり、短チャネル効果が発生し、加えて、バッファ層における欠陥や不純物が多いため、チャネル内の二次元電子ガスに影響を与え、例えば、電流コラプスを生じる。ＡｌＧａＮバックバリア層を導入することにより、チャネル電子とバッファ層とを分離し、二次元電子ガスをチャネル層に効果的に制限し、短チャネル効果および電流コラプス効果を改善することができる。
FIG. 10 is a diagram showing a configuration of a nitride power device on a silicon substrate according to the sixth embodiment of the present invention. An AlGaN back barrier layer 13 is introduced between the buffer layer and the channel layer. Under a constant applied voltage, electrons in the channel enter the buffer layer. Especially in short channel devices, this phenomenon becomes more serious, and the control of the channel electrons by the gate is relatively It becomes weaker and the short channel effect occurs. In addition, since there are many defects and impurities in the buffer layer, it affects the two-dimensional electron gas in the channel, for example, current collapse occurs. By introducing the AlGaN back barrier layer, the channel electrons and the buffer layer can be separated, the two-dimensional electron gas can be effectively limited to the channel layer, and the short channel effect and the current collapse effect can be improved.
図１１は、本発明の第７実施形態のシリコン基板上の窒化物パワーデバイスの構成を示す図である。ゲートの下方に絶縁誘電体層１４を挿入して、ＭＩＳＦＥＴ構造を形成する。この１層の絶縁誘電体は、デバイスのパッシベーション層とされるとともに、ゲート絶縁層であり、ゲートのリーク電流を効果的に低減することができる。絶縁誘電体層１４は、ＳｉＮ、ＳｉＯ２、ＳｉＯＮ、Ａｌ２Ｏ３、ＨｆＯ２、ＨｆＡｌＯｘのうちの１つを含み、もしくは、それらの任意の組み合わせである。 FIG. 11 is a diagram showing a configuration of a nitride power device on a silicon substrate according to the seventh embodiment of the present invention. An insulating dielectric layer 14 is inserted under the gate to form a MISFET structure. The one-layer insulating dielectric serves as a passivation layer of the device and is a gate insulating layer, and can effectively reduce the gate leakage current. The insulating dielectric layer 14 includes one of SiN, SiO 2 , SiON, Al 2 O 3 , HfO 2 , HfAlOx, or any combination thereof.
図１２は、本発明の第８実施形態のシリコン基板上の窒化物パワーデバイスの構成を示す図である。該窒化物パワーデバイスのゲート８および／またはソース６上には、さらにゲートフィールドプレート１５および／またはソースフィールドプレート１６が設けられている。ゲートおよび／またはソースにフィールドプレート構造を導入することにより、ゲートのドレインに接近する側の電界強度を低減し、ゲートのリーク電流を減少し、デバイスの破壊電圧をさらに向上させることができる。 FIG. 12 is a diagram showing a configuration of a nitride power device on a silicon substrate according to the eighth embodiment of the present invention. A gate field plate 15 and / or a source field plate 16 are further provided on the gate 8 and / or the source 6 of the nitride power device. By introducing a field plate structure to the gate and / or source, the electric field strength on the side close to the drain of the gate can be reduced, the gate leakage current can be reduced, and the breakdown voltage of the device can be further improved.
本発明を基にして、シリコン基板上の窒化物チャネル層またはバリア層の構成、あるいはデバイスの製造プロセスを変更することによっても、窒化物パワーデバイスの強化型デバイスを実現することができ、例えば、フッ素イオンでゲート金属の下方の材料領域を衝撃することにより、強化型デバイスなどを形成することができる。 Based on the present invention, nitride power device enhanced devices can also be realized by changing the configuration of the nitride channel layer or barrier layer on the silicon substrate, or by changing the device manufacturing process, for example, A reinforced device or the like can be formed by impacting the material region below the gate metal with fluorine ions.
上記をまとめると、本発明では、シリコン基板上の窒化物パワーデバイスおよびその製造方法が提供され、ｎ型シリコン層およびｐ型シリコン層を交互に繰り返すことにより構成される半導体ドーピング複数層構造をシリコン基板に導入することにより、空間電荷空乏領域が形成され、デバイスの破壊電圧を向上させ、デバイスが電圧により破壊されるリスクを低減させる。 In summary, according to the present invention, a nitride power device on a silicon substrate and a method for manufacturing the same are provided, and a semiconductor-doped multi-layer structure configured by alternately repeating an n-type silicon layer and a p-type silicon layer is provided in silicon. By introducing it into the substrate, a space charge depletion region is formed, improving the breakdown voltage of the device and reducing the risk of the device being destroyed by the voltage.
上記は、例示的な実施例を介して、本発明の窒化物パワーデバイス、および窒化物パワーデバイスを製造するための方法を詳しく説明しているが、上述したこれらの実施例は、取り尽くされたものではなく、当業者は、本発明の精神および範囲内で、様々な変更および修正を実現することができる。従って、本発明は、これらの実施例に限定されるものではなく、本発明の範囲は、添付の特許請求の範囲のみに従う。例えば、上記は、シリコン基板においてｎ型シリコン層およびｐ型シリコン層を交互に繰り返すことにより構成される半導体ドーピング複数層構造を例として説明しているが、理解すべきものとして、基板の耐電圧性を向上させるために、当業者に公知の他の構造または材料を使用することができ、これについて、本発明は、何らかの制限もない。 The above describes the nitride power device of the present invention and the method for manufacturing the nitride power device in detail through exemplary embodiments, but these embodiments described above are exhausted. However, those skilled in the art can implement various changes and modifications within the spirit and scope of the present invention. Accordingly, the present invention is not limited to these examples, and the scope of the present invention is limited solely to the appended claims. For example, the above has been described by taking as an example a semiconductor-doped multi-layer structure formed by alternately repeating an n-type silicon layer and a p-type silicon layer on a silicon substrate. Other structures or materials known to those skilled in the art can be used to improve the, and the present invention is not subject to any limitation.
１ シリコン基板
２ 窒化物核形成層
３ 窒化物バッファ層
４ 窒化物チャネル層
５ 窒化物バリア層
６ ソース
７ ドレイン
８ ゲート
９ 誘電体パッシベーション層
１０ 半導体ドーピング複数層構造
１１ ＧａＮキャップ層
１２ ＡｌＮ挿入層
１３ ＡｌＧａＮバックバリア層
１４ 絶縁誘電体層
１５ ゲートフィールドプレート
１６ ソースフィールドプレート
DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Nitride nucleation layer 3 Nitride buffer layer 4 Nitride channel layer 5 Nitride barrier layer 6 Source 7 Drain 8 Gate 9 Dielectric passivation layer 10 Semiconductor doped multiple layer structure 11 GaN cap layer 12 A l N insertion layer 13 A l GaN back barrier layer 14 an insulating dielectric layer 15 gate field plate 16 source field plate
Claims (13)
空間電荷空乏領域を形成することが可能な半導体ドーピング複数層構造を内部または裏面に形成し、表面が半導体ドーピング構造ではないシリコン表面を有するシリコン基板と、
上記半導体ドーピング構造ではないシリコン表面上におけるエピタキシャル複数層構造と、
前記エピタキシャル複数層構造上に形成される電極と、を含み、
上記エピタキシャル複数層構造は、窒化物核形成層と、前記窒化物核形成層上に形成される窒化物バッファ層と、前記窒化物バッファ層上に形成される窒化物チャネル層と、を含み、
前記窒化物パワーデバイスがトライオード構造である場合、前記電極は、ソースおよびドレイン、並びに、ソースとドレインとの間のゲートを含み、
前記窒化物パワーデバイスがダイオード構造である場合、前記電極は、正極および負極を含む窒化物パワーデバイス。 A nitride power device,
Forming a semiconductor-doped multi-layer structure capable of forming a space charge depletion region inside or on the back surface, and a silicon substrate having a silicon surface whose surface is not a semiconductor doping structure;
An epitaxial multilayer structure on the silicon surface that is not the semiconductor doping structure;
An electrode formed on the epitaxial multilayer structure,
The epitaxial multilayer structure includes a nitride nucleation layer, a nitride buffer layer formed on the nitride nucleation layer, and a nitride channel layer formed on the nitride buffer layer,
When the nitride power device has a triode structure, the electrode includes a source and a drain, and a gate between the source and the drain;
When the nitride power device has a diode structure, the electrode includes a positive electrode and a negative electrode.
空間電荷空乏領域を形成することが可能な半導体ドーピング複数層構造を表面が半導体ドーピング構造ではないシリコン表面を有するシリコン基板の内部または裏面に導入するステップと、
上記半導体ドーピング構造ではないシリコン表面上にエピタキシャル複数層構造を成長させるステップと、
上記エピタキシャル複数層構造上に電極を形成するステップと、を含み、
上記半導体ドーピング構造ではないシリコン表面上にエピタキシャル複数層構造を成長させるステップは、
上記シリコン表面上に窒化物核形成層を成長させ、
上記窒化物核形成層上に窒化物バッファ層を成長させ、
上記窒化物バッファ層上に窒化物チャネル層を成長させ、
前記窒化物パワーデバイスがトライオード構造である場合、前記電極は、ソースおよびドレイン、並びに、ソースとドレインとの間のゲートを含み、前記窒化物パワーデバイスがダイオード構造である場合、前記電極は、正極および負極を含む、
ことを特徴とする窒化物パワーデバイスの製造方法。 A method for manufacturing a nitride power device, comprising:
Introducing a semiconductor doped multilayer structure capable of forming a space charge depletion region into or inside a silicon substrate having a silicon surface whose surface is not a semiconductor doping structure;
Growing an epitaxial multilayer structure on a silicon surface that is not the semiconductor doping structure;
Forming an electrode on the epitaxial multilayer structure,
Growing an epitaxial multilayer structure on a silicon surface that is not the semiconductor doping structure,
Growing a nitride nucleation layer on the silicon surface;
Growing a nitride buffer layer on the nitride nucleation layer;
Growing a nitride channel layer on the nitride buffer layer;
When the nitride power device has a triode structure, the electrode includes a source and a drain and a gate between the source and drain, and when the nitride power device has a diode structure, the electrode has a positive electrode And negative electrode,
A method for manufacturing a nitride power device.
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