CN117497579B - Silicon carbide IGBT structure, manufacturing method and electronic equipment - Google Patents
Silicon carbide IGBT structure, manufacturing method and electronic equipment Download PDFInfo
- Publication number
- CN117497579B CN117497579B CN202311836302.8A CN202311836302A CN117497579B CN 117497579 B CN117497579 B CN 117497579B CN 202311836302 A CN202311836302 A CN 202311836302A CN 117497579 B CN117497579 B CN 117497579B
- Authority
- CN
- China
- Prior art keywords
- region
- active
- silicon carbide
- layer
- active region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 89
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 89
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000003860 storage Methods 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims description 43
- 239000002184 metal Substances 0.000 claims description 43
- 239000000463 material Substances 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 10
- 230000001965 increasing effect Effects 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 15
- 230000004888 barrier function Effects 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A silicon carbide IGBT structure, a manufacturing method and electronic equipment belong to the technical field of semiconductors, two grid source structures are bilaterally symmetrical, and a bilaterally symmetrical tangential plane is a sagittal plane; the drift layer is arranged on the upper surface of the substrate; the two gate source structures and the buffer area are both positioned on the upper surface of the drift layer and are arranged at intervals; the first active region and the second active region are arranged in the buffer region and are positioned on the upper surface of the buffer region; the charge storage region is arranged between the two first wells; the gate-source structure comprises a first well, a first active layer, a third active region and a gate structure; the first well is arranged on the upper surface of the drift layer; a preset distance is arranged between the first trap and the sagittal plane; the first active layer is arranged in the first well and is positioned on the upper surface of the first well; the third active region is arranged on one side of the first well away from the sagittal plane; the grid structure covers the top of the first well; the plurality of second active layers are arranged between the two grid structures; the conduction loss and the chip area are reduced, the reliability is increased, and the process is simplified.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a silicon carbide IGBT structure, a manufacturing method and electronic equipment.
Background
Insulated gate bipolar transistors (insulate-gate bipolar transistor, IGBTs) combine the advantages of high input impedance of metal oxide semiconductor field effect transistors and high current density of bipolar devices, showing great advantages in the medium frequency high power domain. The maximum voltage of the silicon-based IGBT can reach 8.4 kV, which is close to the limit of the silicon device, but the frequency and operating temperature also greatly limit the further development of the silicon-based IGBT in these fields. Silicon carbide has higher breakdown field strength, higher intrinsic temperature, higher thermal conductivity and higher carrier saturation drift velocity as a wide bandgap material. Therefore, the silicon carbide IGBT device shows stronger competitiveness in the high-voltage, high-temperature and high-power fields. In practical application, the anti-parallel diode is needed to process reverse current, the silicon-based IGBT usually adopts the body diode to reduce parasitic inductance and play a role of follow current, but for the silicon carbide IGBT, the material band gap is wider, the opening voltage (about 2.7V) of the body diode is far higher than that of the silicon-based IGBT (about 1.5V), and the conduction loss is larger.
The related silicon carbide IGBT can perform reverse freewheeling by integrating the SiC IGBT with a schottky barrier diode (schottky barrier diode, SBD) or junction field-effect transistor (JFET) in anti-parallel, but is usually connected in parallel in a plane, which increases the chip area; there is also a related structure in which the silicon carbide IGBT controls the opening of the freewheel channel at the time of reversal by the split gate, but it has problems of gate reliability, complicated process, and low current density. And because IGBT is bipolar device, so its body region stores the minority carrier and can seriously influence the switching performance, generally accelerate the minority carrier extraction through the recovery diode (fast recovery diode, FRD), but the effect is limited.
Therefore, the related silicon carbide IGBT has the problems of large conduction loss, large chip area, poor reliability and complex process.
Disclosure of Invention
The application aims to provide a structure, a manufacturing method and electronic equipment of a silicon carbide IGBT, and aims to solve the problems of large conduction loss, large chip area, poor reliability and complex process of the related silicon carbide IGBT.
The embodiment of the application provides a silicon carbide IGBT structure, which comprises two grid source structures which are bilaterally symmetrical, a substrate, a charge storage region, a drift layer, a buffer region, a first active region and a second active region, wherein the bilaterally symmetrical tangential planes are sagittal planes;
The drift layer is arranged on the upper surface of the substrate;
The two gate-source structures and the buffer area are both positioned on the upper surface of the drift layer and are arranged at intervals;
the first active region and the second active region are arranged in the buffer region and are positioned on the upper surface of the buffer region;
The charge storage region is disposed between two first wells;
The gate-source structure comprises:
The first well is arranged on the upper surface of the drift layer; wherein a preset distance is arranged between the first trap and the sagittal plane;
the first active layer is arranged in the first well and positioned on the upper surface of the first well;
A third active region disposed on a side of the first well away from the sagittal plane;
a gate structure covering a top of the first well;
the structure of the silicon carbide IGBT further comprises:
a plurality of second active layers disposed between two of the gate structures;
wherein the third active region, the second active region, the substrate, the second active layer, and the first well are of a first type; the buffer region, the charge storage region, the drift layer, the first active region, and the first active layer are of a second type.
In one embodiment, the silicon carbide IGBT structure includes:
And a fourth active region located between the third active region and the buffer region and on an upper surface of the drift layer.
In one embodiment, the first type is P-type and the second type is N-type; or alternatively
The first type is N-type, and the second type is P-type.
In one embodiment, the method further comprises:
A first metal layer covering the third active region, the first active layer, and the second active layer;
a second metal layer located on the upper surface of the first active region and the upper surface of the second active region;
A third metal layer connected to the gate structure;
The first metal layer is an emitter electrode of the silicon carbide IGBT, the second metal layer is a collector electrode of the silicon carbide IGBT, and the third metal layer is a gate electrode of the silicon carbide IGBT.
In one embodiment, the gate structure material includes silicon dioxide and polysilicon; the material of the second active layer includes polysilicon; materials of the charge storage region, the drift layer, the buffer region, the first active region, the second active region, the third active region, the first active layer, and the first well include silicon carbide.
The embodiment of the application also provides a manufacturing method of the silicon carbide IGBT, which comprises the following steps:
forming a drift layer on the upper surface of the substrate;
Forming a buffer region and a charge storage region on the upper surface of the drift layer;
Forming two first wells which are bilaterally symmetrical on the upper surface of the first side of the drift layer and are positioned on two sides of the charge storage region; the tangential plane which is bilaterally symmetrical is a sagittal plane, and a preset distance is arranged between the first trap and the sagittal plane;
forming two first active layers in the two first wells and on the upper surfaces of the first wells respectively to form a buffer area, and forming a first active area on the upper surfaces of the buffer areas and in the buffer area;
Forming two third active regions on the sides of the two first wells far away from the sagittal plane respectively, and forming a second active region on the upper surface of the buffer region and in the buffer region;
forming two gate structures on top of the two first wells respectively;
a plurality of second active layers are formed between the two gate structures.
In one embodiment, the forming two first active layers in the two first wells and on the upper surface of the first wells, and forming a first active region on the upper surface of the buffer region and in the buffer region further includes:
a fourth active region is formed between the third active region and the buffer region and on the upper surface of the drift layer.
In one embodiment, after forming the plurality of second active layers between the two gate structures, the method further includes:
Forming a first metal layer on the third active region, the upper surface of the first active layer, and the upper surface of the second active layer;
forming a second metal layer on the upper surface of the first active region and the upper surface of the second active region;
And forming a third metal layer connected with the grid structure.
In one embodiment, the third active region, the second active region, the substrate, the second active layer, and the first well are of a first type; the buffer region, the charge storage region, the drift layer, the first active region, and the first active layer are of a second type.
The embodiment of the application also provides electronic equipment, which comprises the structure of the silicon carbide IGBT.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: since the first and second active regions function as collectors, the first well functions as a gate, and the first and third active regions function as emitters. The second active layer and the drift layer form a heterojunction. When the silicon carbide IGBT is applied with forward voltage, the collector electrode and the emitter electrode are conducted, the heterojunction is reversely biased, and a depletion layer of the heterojunction expands and pinches off a freewheel channel; when the silicon carbide IGBT is applied with reverse voltage, the collector and the emitter are turned off, the heterojunction is forward biased, and the depletion layer of the heterojunction expands and pinches off the flywheel to conduct, so that the reverse flywheel can be achieved without anti-parallel integration of the SiC IGBT and the Schottky barrier diode or the junction field effect transistor, the conduction loss and the chip area are reduced, the reliability is increased, and the process is simplified.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it will be apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a silicon carbide IGBT according to an embodiment of the application;
fig. 2 is a schematic structural diagram of a freewheel channel in a silicon carbide IGBT structure according to an embodiment of the present application;
FIG. 3 is a band diagram of a silicon carbide IGBT structure according to one embodiment of the present application;
FIG. 4 is another energy band diagram of a silicon carbide IGBT structure according to an embodiment of the present application;
Fig. 5 is another schematic structural diagram of a silicon carbide IGBT according to an embodiment of the application;
fig. 6 is another schematic structural diagram of a silicon carbide IGBT according to an embodiment of the application;
fig. 7 is a schematic diagram illustrating formation of a drift layer in a method for manufacturing a silicon carbide IGBT according to an embodiment of the application;
FIG. 8 is a schematic diagram of forming a buffer region and a charge storage region in a method for fabricating a silicon carbide IGBT according to an embodiment of the application;
Fig. 9 is a schematic diagram illustrating formation of a first well in a method for manufacturing a silicon carbide IGBT according to an embodiment of the application;
fig. 10 is a schematic diagram of forming a first active layer, a buffer region and a first active region in a method for manufacturing a silicon carbide IGBT according to an embodiment of the application;
fig. 11 is a schematic diagram of forming a second active region and a third active region in the method for manufacturing a silicon carbide IGBT according to the embodiment of the application;
Fig. 12 is a schematic diagram of forming a gate structure in a method for manufacturing a silicon carbide IGBT according to an embodiment of the application;
Fig. 13 is a schematic diagram illustrating formation of a plurality of second active layers in a method for manufacturing a silicon carbide IGBT according to an embodiment of the application;
Fig. 14 is a schematic diagram illustrating formation of a fourth active region in a method for manufacturing a silicon carbide IGBT according to an embodiment of the application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Fig. 1 shows the structure of a silicon carbide IGBT according to an embodiment of the invention, and for convenience of explanation, only the portions related to the embodiment of the invention are shown, and the details are as follows:
the structure of the silicon carbide IGBT comprises two grid source structures which are bilaterally symmetrical, a substrate 10, a charge storage region 80, a drift layer 20, a buffer region 90, a first active region 04 and a second active region 05, wherein the bilaterally symmetrical tangential plane is a sagittal plane 100.
The drift layer 20 is provided on the upper surface of the substrate 10.
Both gate-source structures and buffer regions 90 are located on the upper surface of the drift layer 20 and are spaced apart.
The first active region 04 and the second active region 05 are disposed in the buffer region 90 and located on the upper surface of the buffer region 90.
The charge storage region 80 is disposed between the two first wells 30.
The gate-source structure includes a first well 30, a first active layer 40, a third active region 70, and a gate structure 50.
The first well 30 is provided on the upper surface of the drift layer 20; wherein a predetermined distance is provided between the first well 30 and the sagittal plane 100.
The first active layer 40 is disposed in the first well 30 and located on the upper surface of the first well 30.
The third active region 70 is disposed on a side of the first well 30 remote from the sagittal plane 100.
The gate structure 50 covers the top of the first well 30;
the structure of the silicon carbide IGBT further includes a plurality of second active layers 60.
The plurality of second active layers 60 are disposed between the two gate structures 50.
Wherein the third active region 70, the second active region 05, the substrate 10, the second active layer 60 and the first well 30 are of the first type; the buffer region 90, the charge storage region 80, the drift layer 20, the first active region 04, and the first active layer 40 are of the second type. The first type and the second type are different.
It should be noted that the first type is P-type, and the second type is N-type; or alternatively
The first type is N type and the second type is P type.
It should be noted that the second active layer 60 is highly doped, the doping concentration is more than 1e19, the width is about 0.1 to 0.2 μm, and the freewheel channel width is about 0.1 to 0.2 μm, and the structure can increase the freewheel channel with little or no increase in the cell area.
The number of the second active layers 60 is more than two, and the description of the present application uses 2 second active layers 60 to form the freewheel channels, and embodiments that simply increase the number of the second active layers 60 and the freewheel channels are also within the scope of the present application.
In a specific implementation, the first active region 04 and the third active region 70 serve as emitters, the first well 30 serves as a gate, and the first active layer 40 and the second active layer 60 serve as collectors. The second active layer 60 forms a heterojunction with the drift layer 20. Taking the first type as P-type and the second type as N-type as an example, when the silicon carbide IGBT applies a forward voltage, the emitter is connected to a low potential, electrons sequentially pass through the emitter electrode, the first active layer 40, the first well 30, the charge storage region 80, the drift region, the buffer region 90, the first active region 04/the second active region 05 to the collector electrode, and holes sequentially pass through the collector electrode, the second active region 05, the buffer region 90, the drift region, the charge storage region 80, the first well 30, and the third active region 70 to the emitter electrode, the collector and the emitter are turned on, the heterojunction is reversely biased, and a depletion layer of the heterojunction expands to pinch off a freewheel channel, as shown in part (a) of fig. 2. When the silicon carbide IGBT is applied with reverse voltage, the collector is connected with high potential, the collector and the emitter are turned off, the heterojunction is forward biased, the depletion layer of the heterojunction expands and pinches off and turns on, as shown in part (b) of fig. 2, electrons sequentially pass through the collector electrode, the first active region 04, the buffer, the drift layer 20, the charge storage region 80 and the heterojunction to the emitter, so that the reverse freewheel effect can be achieved without reversely integrating the SiC MOSFET with the SBD or the junction field effect transistor JFET in parallel, the conduction loss and the chip area are reduced, the reliability and the current density are increased, and the process is simplified.
As shown in fig. 3, the heterojunction energy band diagram is that, due to the difference of forbidden band widths, silicon and silicon carbide contact forms a potential barrier difference of a conduction band, in order to prevent the influence on voltage resistance caused by excessive forward leakage, the forward electron barrier Ep-forward should be large enough, and here the forward electron barrier Ep-forward is about 0.7eV; to increase the forward electron barrier height, it is considered to form a schottky contact on the second active layer 60. Silicon has no barrier difference with silicon carbide contact, so holes can pass freely.
When the grid of the silicon carbide IGBT is turned off and the collector is forward biased, a large number of holes from the collector are gathered below the first well 30 through the drift layer 20 and are difficult to be completely combined or extracted, the heterojunction has no hole barrier, and holes can be rapidly extracted, but when the grid is turned on, the holes are directly transmitted to the emitter through the heterojunction, and the grid of the silicon carbide IGBT loses control function; in order to avoid the above problem, the charge storage region 80 is added at the heterojunction interface, thereby pulling down the energy band, generating a hole barrier, so that holes from the collector need to overcome a certain barrier difference to reach the emitter, and enhancing the gate control capability, as shown in fig. 4. However, it should be noted that the concentration of the charge storage region 80 is not too high, because the high concentration SiC makes the heterojunction barrier thin, electron tunneling from the second active region 05 to the CSL occurs more easily, the leakage current increases, and the voltage resistance is deteriorated. The doping type of the charge storage region 80 is the second type. The doping concentration of the charge storage region 80 is greater than the doping concentration of the drift layer 20 and less than the doping concentration of the first active layer 40. The material of the charge storage region 80 is silicon carbide. The provision of the charge storage region 80 also reduces the JFET effect between the first wells 30, increasing the forward conduction current of the silicon carbide IGBT.
It should be noted that the doping type of the third active region 70 is the first type. The third active region 70 is heavily doped. The material of the third active region 70 may be silicon carbide.
By providing the third active region 70, isolation is formed between adjacent heterojunction integrated silicon carbide transistors, and integration of the cells of the plurality of heterojunction integrated silicon carbide transistors is also achieved.
As shown in fig. 5, the structure of the silicon carbide IGBT further includes a fourth active region 03.
A fourth active region 03 located between the third active region 70 and the buffer region 90 and on the upper surface of the drift layer 20.
Note that the doping type of the fourth active region 03 is the first type. The fourth active region 03 is lightly doped. The material of the fourth active region 03 may be silicon carbide.
The fourth active region 03 and the drift layer 20 form a super junction-like structure, so that the voltage-withstanding capability is improved; in addition, for the super junction-like structure, a large-area semiconductor column exists in the drift region, so that a certain minority carrier storage effect exists, the switching characteristic is poor, a heterojunction has no hole barrier, holes can pass through freely, the effect of rapidly extracting holes is achieved, and the switching frequency is improved.
As shown in fig. 6, the structure of the silicon carbide IGBT further includes a first metal layer 01, a second metal layer 02, and a third metal layer.
A first metal layer 01 covering the third active region 70, the first active layer 40, and the second active layer 60;
A second metal layer 02 located on the upper surface of the first active region 04 and the upper surface of the second active region 05;
a third metal layer connected to the gate structure 50;
the first metal layer 01 is an emitter electrode of the silicon carbide IGBT, the second metal layer 02 is a collector electrode of the silicon carbide IGBT, and the third metal layer is a gate electrode of the silicon carbide IGBT.
The first metal layer 01 is an emitter electrode of the heterojunction-integrated silicon carbide transistor, the second metal layer 02 is a collector electrode of the heterojunction-integrated silicon carbide transistor, and the third metal layer is a gate electrode of the heterojunction-integrated silicon carbide transistor.
By way of example and not limitation, the second active layer 60 and the first metal layer 01 are schottky contacts, thereby increasing the potential barrier and reducing leakage current when the silicon carbide IGBT applies a forward voltage.
In particular implementations, the material of gate structure 50 includes silicon dioxide and polysilicon; the material of the second active layer 60 includes polysilicon; the materials of the charge storage region 80, the drift layer 20, the buffer region 90, the first active region 04, the second active region 05, the third active region 70, the first active layer 40, and the first well 30 include silicon carbide.
Corresponding to an embodiment of a silicon carbide IGBT, the invention also provides an embodiment of a method of manufacturing a silicon carbide IGBT.
A method of manufacturing a silicon carbide IGBT, the method comprising steps 401 to 407.
In step 401, as shown in fig. 7, a drift layer 20 is formed on the upper surface of a substrate 10.
The drift layer 20 is formed on the upper surface of the substrate 10 by sputtering or vapor deposition.
In step 402, as shown in fig. 8, the buffer region 90 and the charge storage region 80 are formed on the upper surface of the drift layer 20.
The buffer region 90 and the charge storage region 80 are formed on the upper surface of the drift layer 20 by ion implantation.
In step 403, as shown in fig. 9, two first wells 30 are formed on the upper surface of the first side of the drift layer 20 and on both sides of the charge storage region 80, which are bilaterally symmetrical; wherein the bilaterally symmetrical tangential plane is a sagittal plane 100, and a preset distance is provided between the first well 30 and the sagittal plane 100;
Two first wells 30 are formed symmetrically left and right on the upper surface of the first side of the drift layer 20 and on both sides of the charge storage region 80 by ion implantation.
In step 404, as shown in fig. 10, two first active layers 40 are formed in the two first wells 30 and located on the upper surfaces of the first wells 30, respectively, forming a buffer region 90, and a first active region 04 is formed on the upper surface of the buffer region 90 and located in the buffer region 90;
Two first active layers 40 are formed in the two first wells 30 respectively and located at the upper surfaces of the first wells 30 by ion implantation, and a buffer region 90 is formed by ion implantation, and a first active region 04 is formed at the upper surface of the buffer region 90 and located in the buffer region 90.
In step 405, as shown in fig. 11, two third active regions 70 are formed on the sides of the two first wells 30 away from the sagittal plane 100, and a second active region 05 is formed on the upper surface of the buffer region 90 and located in the buffer region 90;
forming two third active regions 70 on the sides of the two first wells 30 away from the sagittal plane 100 by ion implantation, and forming a second active region 05 on the upper surface of the buffer region 90 and in the buffer region 90;
in step 406, as shown in fig. 12, two gate structures 50 are formed on top of the two first wells 30, respectively;
Two gate structures 50 are formed on top of the two first wells 30 by thermal oxygen oxidation and polysilicon deposition, respectively.
In step 407, as shown in fig. 13, a plurality of second active layers 60 are formed between two gate structures 50.
A plurality of second active layers 60 are formed between the two gate structures 50 by vapor deposition and ion implantation.
In particular, step 404-2 is further included after step 404.
In step 404-2, as shown in fig. 14, a fourth active region 03 is formed between the third active region 70 and the buffer region 90 and on the upper surface of the drift layer 20.
Note that the third active region 70, the second active region 05, the substrate 10, the second active layer 60, and the first well 30 are of the first type; the buffer region 90, the charge storage region 80, the drift layer 20, the first active region 04, and the first active layer 40 are of the second type.
In particular, step 407 further includes steps 408 to 410.
In step 406, a first metal layer is formed on the third active region, the upper surface of the first active layer, and the upper surface of the second active layer.
In step 407, a second metal layer is formed on the upper surface of the first active region and the upper surface of the second active region.
In step 408, a third metal layer is formed in connection with the gate structure.
It is worth emphasizing that the first metal layer is an emitter electrode of a silicon carbide IGBT, the second metal layer is a collector electrode of the silicon carbide IGBT, and the third metal layer is a gate electrode of the silicon carbide IGBT.
It is noted that the metal layer may be gold or palladium.
The embodiment of the invention comprises two grid source structures which are bilaterally symmetrical, a substrate, a charge storage area, a drift layer, a buffer area, a plurality of second active layers, a first active area and a second active area, wherein the bilaterally symmetrical tangential planes are sagittal planes; the drift layer is arranged on the upper surface of the substrate; the two gate source structures and the buffer area are both positioned on the upper surface of the drift layer and are arranged at intervals; the first active region and the second active region are arranged in the buffer region and are positioned on the upper surface of the buffer region; the charge storage region is arranged between the two first wells; the gate-source structure comprises a first well, a first active layer, a third active region and a gate structure; the first well is arranged on the upper surface of the drift layer; wherein a preset distance is arranged between the first trap and the sagittal plane; the first active layer is arranged in the first well and is positioned on the upper surface of the first well; the third active region is arranged on one side of the first well away from the sagittal plane; the grid structure covers the top of the first well; the plurality of second active layers are arranged between the two grid structures; wherein the third active region, the second active region, the substrate, the second active layer and the first well are of a first type; the buffer region, the charge storage region, the drift layer, the first active region and the first active layer are of a second type; the conduction loss and the chip area are reduced, the reliability and the current density are increased, and the process is simplified.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (7)
1. The silicon carbide IGBT structure is characterized by comprising two grid source structures which are bilaterally symmetrical, a substrate, a charge storage region, a drift layer, a buffer region, a first active region and a second active region, wherein the bilaterally symmetrical tangential planes are sagittal planes;
The drift layer is arranged on the upper surface of the substrate;
The two gate-source structures and the buffer area are both positioned on the upper surface of the drift layer and are arranged at intervals;
the first active region and the second active region are arranged in the buffer region and are positioned on the upper surface of the buffer region;
The charge storage region is disposed between two first wells;
The gate-source structure comprises:
The first well is arranged on the upper surface of the drift layer; wherein a preset distance is arranged between the first trap and the sagittal plane;
the first active layer is arranged in the first well and positioned on the upper surface of the first well;
A third active region disposed on a side of the first well away from the sagittal plane;
a gate structure covering a top of the first well;
the structure of the silicon carbide IGBT further comprises:
a plurality of second active layers disposed between two of the gate structures;
a first metal layer covering the charge storage region, the third active region, the first active layer, and the second active layer;
a second metal layer located on the upper surface of the first active region and the upper surface of the second active region;
A third metal layer connected to the gate structure;
The first metal layer is an emitter electrode of the silicon carbide IGBT, the second metal layer is a collector electrode of the silicon carbide IGBT, and the third metal layer is a gate electrode of the silicon carbide IGBT;
Wherein the third active region, the second active region, the substrate, the second active layer, and the first well are of a first type; the buffer region, the charge storage region, the drift layer, the first active region, and the first active layer are of a second type;
Exposing an upper surface of the charge storage region between a plurality of the second active layers, the first metal layer being in direct contact with the exposed upper surface of the charge storage region;
the material of the second active layer includes polysilicon; the material of the charge storage region comprises silicon carbide;
a heterojunction is formed between the second active layer and the charge storage region.
2. The structure of a silicon carbide IGBT of claim 1 wherein the structure of the silicon carbide IGBT comprises:
And a fourth active region located between the third active region and the buffer region and on an upper surface of the drift layer.
3. The structure of silicon carbide IGBTs of claim 1, wherein the first type is P-type and the second type is N-type; or alternatively
The first type is N-type, and the second type is P-type.
4. A structure of a silicon carbide IGBT as claimed in any one of claims 1 to 3, wherein the material of the gate structure comprises silicon dioxide and polysilicon; the materials of the drift layer, the buffer region, the first active region, the second active region, the third active region, the first active layer, and the first well include silicon carbide.
5. A method of manufacturing a silicon carbide IGBT, the method comprising:
forming a drift layer on the upper surface of the substrate;
Forming a buffer region and a charge storage region on the upper surface of the drift layer;
Forming two first wells which are bilaterally symmetrical on the upper surface of the first side of the drift layer and are positioned on two sides of the charge storage region; the tangential plane which is bilaterally symmetrical is a sagittal plane, and a preset distance is arranged between the first trap and the sagittal plane;
forming two first active layers in the two first wells and on the upper surfaces of the first wells respectively to form a buffer area, and forming a first active area on the upper surfaces of the buffer areas and in the buffer area;
Forming two third active regions on the sides of the two first wells far away from the sagittal plane respectively, and forming a second active region on the upper surface of the buffer region and in the buffer region;
forming two gate structures on top of the two first wells respectively;
forming a plurality of second active layers between the two gate structures;
Forming a first metal layer on the charge storage region, the third active region, the upper surface of the first active layer, and the upper surface of the second active layer;
forming a second metal layer on the upper surface of the first active region and the upper surface of the second active region;
Forming a third metal layer connected with the grid structure;
The first metal layer is an emitter electrode of the silicon carbide IGBT, the second metal layer is a collector electrode of the silicon carbide IGBT, and the third metal layer is a gate electrode of the silicon carbide IGBT;
Wherein the third active region, the second active region, the substrate, the second active layer, and the first well are of a first type; the buffer region, the charge storage region, the drift layer, the first active region, and the first active layer are of a second type;
Exposing an upper surface of the charge storage region between a plurality of the second active layers, the first metal layer being in direct contact with the exposed upper surface of the charge storage region;
the material of the second active layer includes polysilicon; the material of the charge storage region comprises silicon carbide;
a heterojunction is formed between the second active layer and the charge storage region.
6. The method according to claim 5, wherein forming two first active layers in the two first wells and on the upper surface of the first well, and forming a first active region in the buffer region and on the upper surface of the buffer region, respectively, further comprises:
a fourth active region is formed between the third active region and the buffer region and on the upper surface of the drift layer.
7. An electronic device comprising the structure of the silicon carbide IGBT according to any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311836302.8A CN117497579B (en) | 2023-12-28 | 2023-12-28 | Silicon carbide IGBT structure, manufacturing method and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311836302.8A CN117497579B (en) | 2023-12-28 | 2023-12-28 | Silicon carbide IGBT structure, manufacturing method and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117497579A CN117497579A (en) | 2024-02-02 |
| CN117497579B true CN117497579B (en) | 2024-05-07 |
Family
ID=89685264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311836302.8A Active CN117497579B (en) | 2023-12-28 | 2023-12-28 | Silicon carbide IGBT structure, manufacturing method and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117497579B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117712122B (en) * | 2024-02-08 | 2024-04-26 | 深圳天狼芯半导体有限公司 | Silicon carbide IGBT structure, manufacturing method and electronic equipment |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005051096A (en) * | 2003-07-30 | 2005-02-24 | Nissan Motor Co Ltd | Semiconductor device and method for manufacturing the same |
| CN107248533A (en) * | 2017-06-09 | 2017-10-13 | 电子科技大学 | A kind of carborundum VDMOS device and preparation method thereof |
| CN109119463A (en) * | 2018-08-29 | 2019-01-01 | 电子科技大学 | A kind of lateral trench type MOSFET element and preparation method thereof |
| CN109192780A (en) * | 2018-08-29 | 2019-01-11 | 电子科技大学 | A kind of lateral MOSFET device and preparation method thereof |
| CN110459596A (en) * | 2019-08-29 | 2019-11-15 | 电子科技大学 | A kind of lateral insulated gate bipolar transistor and preparation method thereof |
| CN110473917A (en) * | 2019-08-22 | 2019-11-19 | 电子科技大学 | A kind of transversal I GBT and preparation method thereof |
| CN110534576A (en) * | 2019-09-09 | 2019-12-03 | 电子科技大学 | A kind of splitting bar 4H-SiC VDMOS device |
| CN114664929A (en) * | 2022-04-21 | 2022-06-24 | 电子科技大学 | Split gate SiC MOSFET (silicon carbide metal oxide semiconductor field effect transistor) integrated with heterojunction diode and manufacturing method thereof |
| CN115832039A (en) * | 2022-12-09 | 2023-03-21 | 宁波达新半导体有限公司 | Reverse conducting IGBT device |
| KR20230050726A (en) * | 2021-10-08 | 2023-04-17 | 서강대학교산학협력단 | Mosfet device and method thereof |
| CN117038733A (en) * | 2023-07-20 | 2023-11-10 | 江苏瑞元半导体有限公司 | Silicon carbide chip and manufacturing method |
-
2023
- 2023-12-28 CN CN202311836302.8A patent/CN117497579B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005051096A (en) * | 2003-07-30 | 2005-02-24 | Nissan Motor Co Ltd | Semiconductor device and method for manufacturing the same |
| CN107248533A (en) * | 2017-06-09 | 2017-10-13 | 电子科技大学 | A kind of carborundum VDMOS device and preparation method thereof |
| CN109119463A (en) * | 2018-08-29 | 2019-01-01 | 电子科技大学 | A kind of lateral trench type MOSFET element and preparation method thereof |
| CN109192780A (en) * | 2018-08-29 | 2019-01-11 | 电子科技大学 | A kind of lateral MOSFET device and preparation method thereof |
| CN110473917A (en) * | 2019-08-22 | 2019-11-19 | 电子科技大学 | A kind of transversal I GBT and preparation method thereof |
| CN110459596A (en) * | 2019-08-29 | 2019-11-15 | 电子科技大学 | A kind of lateral insulated gate bipolar transistor and preparation method thereof |
| CN110534576A (en) * | 2019-09-09 | 2019-12-03 | 电子科技大学 | A kind of splitting bar 4H-SiC VDMOS device |
| KR20230050726A (en) * | 2021-10-08 | 2023-04-17 | 서강대학교산학협력단 | Mosfet device and method thereof |
| CN114664929A (en) * | 2022-04-21 | 2022-06-24 | 电子科技大学 | Split gate SiC MOSFET (silicon carbide metal oxide semiconductor field effect transistor) integrated with heterojunction diode and manufacturing method thereof |
| CN115832039A (en) * | 2022-12-09 | 2023-03-21 | 宁波达新半导体有限公司 | Reverse conducting IGBT device |
| CN117038733A (en) * | 2023-07-20 | 2023-11-10 | 江苏瑞元半导体有限公司 | Silicon carbide chip and manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117497579A (en) | 2024-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103383958B (en) | A kind of RC-IGBT device and making method thereof | |
| CN110148629B (en) | Groove type silicon carbide MOSFET device and preparation method thereof | |
| CN105742346B (en) | Double division trench gate charge storage type RC-IGBT and its manufacturing method | |
| CN105932042A (en) | Double-split groove gate charge storage type IGBT and manufacturing method thereof | |
| CN109192772A (en) | A kind of groove-shaped insulated gate bipolar transistor and preparation method thereof | |
| CN105870179B (en) | A kind of trench gate charge storage type RC-IGBT and its manufacturing method | |
| CN105206656A (en) | Reverse conducting IGBT device | |
| CN117497579B (en) | Silicon carbide IGBT structure, manufacturing method and electronic equipment | |
| WO2020151088A1 (en) | Super-junction power vdmos having extremely low reverse recovery charge | |
| CN106067480A (en) | A kind of binary channels RC LIGBT device and preparation method thereof | |
| CN112420694B (en) | Reversible conduction silicon carbide JFET power device integrated with reverse Schottky freewheel diode | |
| CN102364688A (en) | Vertical double-diffusion metal oxide semiconductor field effect transistor (MOSFET) | |
| CN113471290B (en) | Tunneling-assisted conduction silicon/silicon carbide heterojunction MOSFET power device | |
| CN110504308B (en) | High-speed low-loss multi-groove-gate high-voltage power device | |
| CN109904155A (en) | A kind of silicon carbide MOSFET device of the reversed freewheeling diode of integrated high-speed | |
| US9263560B2 (en) | Power semiconductor device having reduced gate-collector capacitance | |
| CN115188814B (en) | RC-JGBT device and manufacturing method thereof | |
| CN117497601B (en) | Structure, manufacturing method and electronic equipment of planar silicon carbide transistor | |
| CN117476774B (en) | Structure, manufacturing method and electronic equipment of vertical silicon carbide transistor | |
| CN117497600B (en) | Structure, manufacturing method and electronic equipment of super-junction silicon carbide transistor | |
| CN105870180A (en) | Double split trench gate charge storage-type RC-IGBT and manufacturing method thereof | |
| CN115295547A (en) | Low-loss reversible-conduction silicon carbide field effect power transistor device | |
| CN109860303A (en) | A kind of insulated-gate power device of accumulation type channel | |
| CN109860171A (en) | The ambipolar SiC semiconductor power device of the reversed freewheeling diode of integrated high-speed | |
| CN116153992B (en) | Reverse-conduction insulated gate bipolar transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |