CN110473917A - A kind of transversal I GBT and preparation method thereof - Google Patents
A kind of transversal I GBT and preparation method thereof Download PDFInfo
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Abstract
The invention belongs to power semiconductor device technology field, it is related to a kind of transversal I GBT and preparation method thereof.The present invention reduces the conducting resistance of device in the case where not influencing device electric breakdown strength in the super-junction structure that 3 dimension sides are directed upwardly on the basis of traditional transversal I GBT, the N-type charge storage layer of introducing can improve drift region carrier concentration distribution, further decrease the conduction voltage drop of device, the introducing of separate gate structures simultaneously, which can effectively shield N-type charge storage layer, influences and reduces grid capacitance especially Miller capacitance to improve the switching speed of device to device electric breakdown strength, the introducing of PMOS structure can speed up the extraction speed of carrier under device off state simultaneously, improve the turn-off speed of device, reduce the switching loss of device.
Description
Technical field
The invention belongs to power semiconductor device technology field, it is related to a kind of transversal I GBT device and preparation method thereof.
Background technique
From insulated gate bipolar transistor the 1980s (IGBT) by invention since, because its combine MOSFET (absolutely
Edge type field-effect tube) with the working mechanism of BJT (bipolar junction transistor), with MOSFET be easy to drive, input impedance is low,
The fast advantage of switching speed, and have the advantages that the on state current of BJT is big, conduction voltage drop is low, loss is small, stability is good.Thus
It is widely used in the every field such as traffic, communication, household electrical appliance and aerospace.The utilization of IGBT significantly improves electricity
Power electronic system.
Since IGBT emerges, how to reduce the loss of IGBT is always the target of people's research.IGBT is a kind of conductance tune
Type device processed, in order to reduce the conductance modulation ability that the forward conduction voltage drop of IGBT needs to enhance its drift region.Common method
It is to increase the injection efficiency of anode PN to improve the doping concentration of anode p type impurity or the doping concentration of reduction N-type buffer layer
The quantity for improving drift region carrier achievees the purpose that enhancing conductance modulation effect, however the disadvantages of the method are as follows in drift region
Excess carriers cause the turn-off time too long, the big equal adverse effects of turn-off power loss.Another method is using surface injection enhancing
Effect introduces N-type charge storage layer such as in IGBT, is transported to N-type charge storage when injecting the hole to come from IGBT anode
When layer lower section, since the barrier effect of N-type charge storage layer leads to hole accumulation, according to charge balance requirements electron concentration herein
Also drift region carrier concentration distribution is increased accordingly therefore improved, the saturation voltage drop of device is reduced.However electric charge storage layer
The breakdown voltage of device can be made to degenerate, limit device high pressure field application, and this will increase device saturation electricity
Stream reduces shorted devices trouble free service ability.
Summary of the invention
In order to solve the problems in the existing technology, the present invention proposes that a kind of transverse direction 3 ties up IGBT structure and its production side
Method.The purpose of the present invention is improving the tradeoff between the switching loss of device of IGBT device conduction voltage drop, disappear simultaneously
Influence except N type charge storage layer to device electric breakdown strength and saturation current, base of the present invention in traditional transversal I GBT (Fig. 1)
Super-junction structure is introduced on plinth, the introducing of superjunction in the case of not reducing device electric breakdown strength so that reduce the conducting pressure of device
Drop, while in the PMOS structure that 3 dimension sides are directed upwardly into separate gate structures, P+ buried layer and p-type base area, N-type charge storage layer is constituted
Make the potential of NMOS channel clamped firmly when device forward conduction, such anode current would not be with anode voltage
Increase and increase, to achieve the purpose that reduce device saturation current.In device shutdown for hole provide it is additional release it is logical
Road, accelerates the extraction speed of excess carriers, therefore reduces the switching loss of device, while separate gate structures are able to suppress
The introducing of influence and separate gate structures of the N-type charge storage layer to device pressure resistance reduces grid capacitance especially Miller electricity
Hold, the switching speed for improving device further reduced the switching loss of device.
A kind of transversal I GBT device architecture provided by the invention, (it is along AB line, the section of CD line and EF line as shown in Figure 2
Figure is respectively as shown in figure 3, figure 4 and figure 5), including the underlayer electrode 1 being cascading from bottom to up, be located at underlayer electrode 1 it
On P-type semiconductor substrate 2, the buried oxide layer 3 on P-type semiconductor substrate 2, it is characterised in that: above buried oxide layer 3
It is provided with mutually indepedent and arranged side by side p-type base area 7, N-type charge storage layer 16, superjunction N column 42, in P type base area 7
It is internally provided with mutually indepedent and the placed side by side contact zone P+ 9 and N+ emitter region 8, above the superjunction N column 41 and is discharged
It sets and mutually independent superjunction P column 42 and N-type field stop layer 5, there is P+ buried layer 17 inside the superjunction P column 42, described
There is P+ collecting zone 6 inside N-type field stop layer 5, there is emitter metal 1 above the contact zone P+ 9 and N+ emitter region 8,
Above the N+ emitter region 8 and emitter metal side wall has dielectric layer 13, the N+ emitter region 8, p-type base area 7, N-type electricity
There is dielectric layer 10 above lotus accumulation layer 16, P+ buried layer 17, there is dielectric layer 12, institute above the P+ buried layer 17, superjunction P column 42
Stating has collector electrode metal 15 above P+ collecting zone 6, the N+ emitter region 8, p-type base area 7, N-type charge storage layer 16, P+ are buried
Layer top has dielectric layer 10, has gate electrode 11, separate gate electrodes 19 above the dielectric layer 10, the gate electrode with separate
Gate electrode has spacer medium layer 18, the separate gate electrodes 19 and 14 equipotential of emitter metal, and the N+ emitter region 8 is along Z
Direction is connected directly by the end of 11 lower section of gate electrode, the separate gate electrodes 19 with emitter metal.
Further, as shown in Figure 6 (its along AB line, CD line and EF line sectional view respectively as shown in Fig. 7, Fig. 8, Fig. 9),
Separate gate electrodes 19 of the invention are isolated with emitter metal 14 by dielectric layer 13；
Further, as shown in Figure 10 (its along AB line, CD line and EF line sectional view respectively such as Figure 11, Figure 12, Figure 13
It is shown), the L-shaped semi-surrounding of separate gate electrodes 19 of the invention lives gate electrode 11；
Further, as shown in figure 14 (its along AB line, CD line and EF line sectional view respectively such as Figure 15, Figure 16, Figure 17
It is shown), 7 junction depth of p-type base area of the invention is less than the junction depth of N-type charge storage layer 16 and by 16 semi-surrounding of N-type charge storage layer
Firmly.
Further, the semiconductor material of the IGBT device in the present invention uses Si, SiC, GaAs or GaN；
A kind of transversal I GBT production method provided by the invention, comprising the following steps:
The first step, chooses certain thickness SOI material, and SOI material has n type semiconductor layer, buried oxide layer, P type substrate three
Divide and constitute, n type semiconductor layer doping concentration is 1015~1017A/cm3；The doped layer concentration of P type substrate is 1014~1015A/
cm3；
Second step deposits one layer of polycrystalline and is passed through in oxide layer in N-type semiconductor surface oxidation growth layer of oxide layer
Photoetching, etching form gate electrode and separate gate electrodes；
Third step grows one layer of pre-oxidation layer, passes through ion implanting N-type impurity using self-registered technology and the obtained N that anneals
Type charge storage layer, the energy of ion implanting are 200~500KeV, implantation dosage 1013~1014A/cm2, annealing temperature is
1100~1200 DEG C, annealing time 10~30 minutes；Ion implanting p type impurity simultaneously anneals p-type base area 7 is made, and Implantation Energy is
60~300KeV, implantation dosage 1013~1014A/cm2, annealing temperature be 1100 DEG C~1200 DEG C, annealing time be 10~
30 minutes；Ion implanting N-type impurity and p type impurity respectively, the energy of ion implanting N-type impurity are 30~60keV, injectant
Amount is 1015~1016A/cm2, the energy of ion implanting p type impurity is 60~80keV, implantation dosage 1015~1016A/
cm2, annealing temperature is 900 DEG C, and the time is 20~30 minutes, and N+ emitter region 8 and the P+ hair for contacting with each other and being arranged side by side is made
Penetrate area 9；Superjunction P column 42 is made in ion implanting p type impurity and annealing, and Implantation Energy is 100~400KeV, implantation dosage 1012
~1013A/cm2, annealing temperature is 1100 DEG C~1200 DEG C, and annealing time is 10~40 minutes；Ion implanting p type impurity system
P type buried layer 17 is obtained, ion implantation energy is 30~60keV, implantation dosage 1013~1015A/cm2, ion implanting N-type impurity
And anneal and N-type field stop layer 5 is made, ion implantation energy is 200~500KeV, implantation dosage 1013~1014A/cm2, move back
Fiery temperature is 1100~1200 DEG C, annealing time 10~50 minutes；P-type collecting zone 6 is made in ion implanting p type impurity, injects energy
Amount is 40~60KeV, implantation dosage 1012~1013A/cm2。
4th step, positive dielectric layer deposited and by photoetching, etching and etc. etch emitter metal contact zone and
Collector electrode metal contact zone simultaneously deposits metal and etches away redundance metal and produce emitter metal 14 and collector electrode metal
15；
5th step overturns silicon wafer and deposits metal production underlayer electrode 1
Complete the preparation of transversal I GBT a kind of.
In above scheme, the corresponding x-axis direction in coordinate system shown in Fig. 2 of the device transverse direction, device
The corresponding z-axis direction in coordinate system shown in Fig. 2 of part longitudinal direction.
The working principle of the invention:
Separate gate electrodes 11 and emitter metal 14 of the invention are shorted, when gate electrode 14 connects higher than device threshold voltage
When high potential, collector electrode metal 15 connect high potential, emitter metal and separate gate electrodes and connect low potential, device work and positive guide
Logical state, since the hole barrier effect of the offer of N-type charge storage layer 16 and the doping concentration of superjunction N column are higher, device
There are a large amount of carrier, the drift regions of device very strong conductivity modulation effect for the drift region of part, this greatly reduces
The conduction voltage drop of device, and PMOS structure makes NMOS groove potential by clamped firmly so that anode current will not be with anode voltage
Increase and increase, to reduce the saturation current of device；When gate electrode 14, separate gate electrodes 19, emitter metal 14 connect
Low potential, when collector electrode metal 15 connects high potential, device works in reverse blocking state, separate gate electrodes 19, p-type base area 8, N
The PMOS structure that type charge storage layer 16 and P+ buried layer 17 are constituted provides additional access for the extraction in hole, accelerates drift
The extraction speed of carrier, while mutually being exhausted between superjunction P column 42 and superjunction N column 41, it is that drift region electric field is presented trapezoidal point
Cloth, while separate gate electrodes 19 can shield influence of the N-type charge storage layer 16 to device pressure resistance, and separate gate structures draw
The grid capacitance especially Miller capacitance for entering to reduce device, improves the switching speed of device, further reduced device
Switching loss.
Beneficial effects of the present invention are shown:
The present invention can be dropped by introducing super-junction structure in device drift region under conditions of not influencing device electric breakdown strength
The forward conduction voltage drop of low device, simultaneously because the introducing of separate gate structures can effectively shield N-type charge storage layer to device
The grid capacitance especially Miller capacitance that breakdown and the introducing of separate gate structures reduce device improves the switch speed of device
Degree, and the PMOS structure that separate gate structures and p-type base area, N-type charge storage layer, p type buried layer are constituted is in device forward conduction
When make NMOS groove potential by it is clamped live so that the anode current of device will not increase with the increase of anode voltage
Greatly, to reduce the saturation current of device.Additional access is provided for the extraction in hole when device shutdown, therefore
The extraction speed for accelerating carrier improves the switching speed of device and reduces the switching loss of device.
Detailed description of the invention
Fig. 1 is traditional transversal I GBT structural schematic diagram, wherein 1 is substrate metal electrode, and 2 be P type substrate, and 3 be to bury oxygen
Layer, 4 be N-type drift region, and 5 be N-type field stop layer, and 6 be p-type collecting zone, and 7 be p-type base area, and 8 be N-type emitter region, and 9 be p-type
Emitter region, 10 be gate dielectric layer, and 11 be grid polycrystalline electrodes, and 12 be dielectric layer, and 13 be dielectric layer, and 14 be emitter metal electrode,
15 be collector electrode metal electrode.
Fig. 2 is a kind of transversal I GBT structural schematic diagram of the embodiment of the present invention 1；
Fig. 3 is a kind of diagrammatic cross-section of transversal I GBT along AB line of the embodiment of the present invention 1；
Fig. 4 is a kind of diagrammatic cross-section of transversal I GBT along CD line of the embodiment of the present invention 1；
Fig. 5 is a kind of diagrammatic cross-section of transversal I GBT along EF line of the embodiment of the present invention 1；
Fig. 6 is a kind of transversal I GBT structural schematic diagram of the embodiment of the present invention 2；
Fig. 7 is a kind of diagrammatic cross-section of transversal I GBT along AB line of the embodiment of the present invention 2；
Fig. 8 is a kind of diagrammatic cross-section of transversal I GBT along CD line of the embodiment of the present invention 2；
Fig. 9 is a kind of diagrammatic cross-section of transversal I GBT along EF line of the embodiment of the present invention 2；
Figure 10 is a kind of transversal I GBT structural schematic diagram of the embodiment of the present invention 3；
Figure 11 is a kind of diagrammatic cross-section of transversal I GBT along AB line of the embodiment of the present invention 3；
Figure 12 is a kind of diagrammatic cross-section of transversal I GBT along CD line of the embodiment of the present invention 3；
Figure 13 is a kind of diagrammatic cross-section of transversal I GBT along EF line of the embodiment of the present invention 3；
Figure 14 is a kind of transversal I GBT structural schematic diagram of the embodiment of the present invention 4；
Figure 15 is a kind of diagrammatic cross-section of transversal I GBT along AB line of the embodiment of the present invention 4；
Figure 16 is a kind of diagrammatic cross-section of transversal I GBT along CD line of the embodiment of the present invention 4；
Figure 17 is a kind of diagrammatic cross-section of transversal I GBT along EF line of the embodiment of the present invention 4；
Figure 18 is a kind of transversal I GBT structural schematic diagram of the embodiment of the present invention 5；
Figure 19 is a kind of diagrammatic cross-section of transversal I GBT along AB line of the embodiment of the present invention 5；
Figure 20 is a kind of diagrammatic cross-section of transversal I GBT along CD line of the embodiment of the present invention 5；
Figure 21 is a kind of diagrammatic cross-section of transversal I GBT along EF line of the embodiment of the present invention 5；
Fig. 2 is into Figure 21, and 1 is underlayer electrode, and 2 be P type substrate, and 3 be buried oxide layer, and 41 be superjunction N column, and 42 be superjunction P
Column, 5 be N-type field stop layer, and 6 be p-type collecting zone, and 7 be p-type base area, and 8 be N+ emitter region, and 9 be P+ emitter region, and 10 be gate medium
Layer, 11 be grid polycrystalline electrodes, and 12 be dielectric layer, and 13 be dielectric layer, and 14 be emitter metal electrode, and 15 be collector electrode metal electricity
Pole, 16 be N-type field stop layer, and 17 be p type buried layer, and 18 be dielectric layer, and 19 be separate gate polycrystalline electrodes.
Specific embodiment
Below in conjunction with attached drawing, the principle of the present invention and characteristic are described further, example is served only for explaining this
Invention, is not intended to limit the scope of the present invention.
Embodiment 1
A kind of transversal I GBT device embodiments, (it such as schemes respectively along the sectional view of AB line, CD line and EF line as shown in Figure 2
3, shown in Fig. 4 and Fig. 5), comprising: P-type semiconductor substrate 2, the underlayer electrode 1 positioned at 2 lower surface of P-type semiconductor substrate are located at P
The buried oxide layer 3 of 2 upper surface of type semiconductor substrate, it is characterised in that being arranged side by side in buried oxide layer upper surface has p-type base area 7, N-type
Charge storage layer 16, superjunction N column 41, the junction depth of the p-type base area 7 are 1~2 μm, the width of the superjunction N column 41 in X direction
It is 30~50 μm, the superjunction N column 41 runs through along Z-direction, and the doping concentration of the superjunction N column 41 is 1015~1017cm-3；In
Be provided in the p-type base area 7 side by side and mutually independent N+ emitter region 8, P+ emitter region 9, P+ transmitting, 9 with N+ emitter region 8
Junction depth be 0.2~0.5 μm, the p-type emitter region 9 runs through along Z-direction；Inside the superjunction N column 41 be arranged side by side have it is super
P column 42, N-type field stop layer 5 are tied, the superjunction P column 42 is contacted with N-type charge storage layer 16, and the superjunction P column adulterates 42 concentration
It is 1015~1017cm-3, the doping concentration of the N-type field stop layer 5 is 1015~1017cm-3, the knot of the N-type field stop layer 5
The deep junction depth for being greater than or equal to superjunction P column 42, less than or equal to the junction depth of superjunction N column 41, more than or equal to the knot of p-type base area 7
Deep, the superjunction P column 42, N-type field stop layer 5 run through along the direction Z；It is internally provided with p type buried layer 17 in the superjunction P column 42,
The doping concentration of the p type buried layer 17 is 1016~1018cm-3, the p type buried layer 17 contacts with N-type charge storage layer 16, institute
The junction depth for stating p type buried layer 17 is less than or equal to the junction depth of superjunction P column 42, and the p type buried layer 17 runs through along Z-direction or only separating
Exist below gate electrode 19；P-type collecting zone 6, the junction depth of the p-type collecting zone 6 are internally provided in the N-type field stop layer 5
Less than or equal to the junction depth of N-type field stop layer 5, the p-type collecting zone 6 runs through along Z-direction；It is sent out in the p-type emitter region 9, N-type
It penetrates 8 upper surface of area and is provided with emitter metal 14；In the N-type emitter region, p-type base area, N-type charge storage layer 16, p type buried layer
17 upper surfaces are provided with gate dielectric layer 10；The gate dielectric layer upper surface is provided with polycrystalline gate electrode 11, dielectric layer 18, more
Crystalline substance separation gate dielectric layer 19, the effect of dielectric layer 19 are that polycrystalline gate electrode 11 and polycrystalline separate gate electrodes 19 are isolated,；It is described
N+ emitter region upper surface has dielectric layer 13, and the effect of the dielectric layer 13 is isolation emitter metal and polycrystalline gate electrode；In
The p type buried layer 9, superjunction P column 42,5 upper surface of N-type field stop layer have dielectric layer 12；The N-type emitter region is cut along the direction Z
It only arrives below gate electrode, the separate gate electrodes 19 are connected directly with emitter metal 14.
Embodiment 2
A kind of transversal I GBT device embodiments, as Fig. 6 (its along AB line, CD line and EF line sectional view respectively such as Fig. 7, Fig. 8
And shown in Fig. 9), comprising: P-type semiconductor substrate 2, the underlayer electrode 1 positioned at 2 lower surface of P-type semiconductor substrate are located at p-type half
The buried oxide layer 3 of 2 upper surface of conductor substrate, it is characterised in that being arranged side by side in buried oxide layer upper surface has p-type base area 7, N-type charge
Accumulation layer 16, superjunction N column 41, the junction depth of the p-type base area 7 are 1~2 μm, and the width of the superjunction N column 41 in X direction is 30
~50 μm, the superjunction N column 41 runs through along Z-direction, and the doping concentration of the superjunction N column 41 is 1015~1017cm-3；In the P
Be provided in type base area 7 side by side and mutually independent N+ emitter region 8, P+ emitter region 9, P+ transmitting, 9 with the junction depth of N+ emitter region 8
It is 0.2~0.5 μm, the p-type emitter region 9 runs through along Z-direction；Being arranged side by side inside the superjunction N column 41 has superjunction P column
42, N-type field stop layer 5, the superjunction P column 42 are contacted with N-type charge storage layer 16, and it is 10 that the superjunction P column, which adulterates 42 concentration,15
~1017cm-3, the doping concentration of the N-type field stop layer is 1015~1017cm-3, the junction depth of the N-type field stop layer 5 is greater than
Or the junction depth equal to superjunction P column 42, institute's superjunction P column 42, N-type field stop layer 5 run through along Z-direction；In the superjunction P column 42
Portion is provided with p type buried layer 17, and the doping concentration of the p type buried layer 17 is 1016~1018cm-3, the p type buried layer 17 and N-type are electric
Lotus accumulation layer 16 contacts, and the junction depth of the p type buried layer 17 is less than or equal to the junction depth of superjunction P column 42, and the p type buried layer 17 is along Z
Direction is run through；It is internally provided with p-type collecting zone 6 in the N-type field stop layer 5, the junction depth of the p-type collecting zone 6 is less than or waits
In the junction depth of N-type field stop layer 5, the p-type collecting zone 6 runs through along Z-direction；In the p-type emitter region 9, N-type emitter region 8
Surface is provided with emitter metal 14；The table on the N-type emitter region, p-type base area, N-type charge storage layer 16, p type buried layer 17
Face is provided with gate dielectric layer 10；The gate dielectric layer upper surface is provided with polycrystalline gate electrode 11, dielectric layer 18, polycrystalline separate gate
Dielectric layer 19, the effect of dielectric layer 19 are that polycrystalline gate electrode 11 and polycrystalline separate gate electrodes 19 are isolated,；The N+ emitter region
Upper surface has dielectric layer 13, and the effect of the dielectric layer 13 is isolation emitter metal and polycrystalline gate electrode and polycrystalline separate gate
Electrode；There is dielectric layer 12 in the p type buried layer 9, superjunction P column 42,5 upper surface of N-type field stop layer；The N-type emitter region is along Z
Direction is below gate electrode.
Embodiment 3
A kind of transversal I GBT device embodiments, as Figure 10 (its along AB line, CD line and EF line sectional view respectively as Figure 11,
Shown in Figure 12 and Figure 13), it is walked on the basis of embodiment 1 by opening and photoetching, etching, the filling polycrystalline etc. that adjust mask plate
Suddenly make separate gate electrodes 19 and emitter metal 14 is connected directly and the L-shaped encirclement gate electrode 11 of separate gate electrodes 19.
So that separate gate electrodes make device not need to carry out on separate gate electrodes with the direct equipotential of emitter metal
Additional metal routing, and the separate gate electrodes of the shape can further subtract lower grid capacitance especially Miller capacitance, mention
The switching speed of high device, and can further shield influence of the N-type charge storage layer to device electric breakdown strength.
Embodiment 4
A kind of transversal I GBT device embodiments, as Figure 14 (its along AB line, CD line and EF line sectional view respectively as Figure 15,
Shown in Figure 16 and Figure 17), make p-type base by adjusting dosage, energy and the time of ion implanting on the basis of embodiment 2
The junction depth in area 7 is less than the junction depth of N-type charge storage layer 16 and p-type base area 7 is lived by 16 semi-surrounding of N-type charge storage layer.
By allowing N-type Electronic saving layer 16 to surround p-type base area 7, the hole barrier resistance of N-type Electronic saving layer 16 is enhanced
Gear effect improves drift region carrier concentration distribution, improves the tradeoff between the forward conduction of device and turn-off power loss.
Embodiment 5
A kind of transversal I GBT device embodiments, as Figure 18 (its along AB line, CD line and EF line sectional view respectively as Figure 19,
Shown in Figure 20 and Figure 21), superjunction junction structure is removed on the basis of embodiment 1.
Illustrate that the present invention can equally be well applied to the transversal I GBT of no super-junction structure by removing super-junction structure.
Claims (6)
1. a kind of transversal I GBT device, comprising: P-type semiconductor substrate (2) is located at the substrate of P-type semiconductor substrate (2) lower surface
Electrode (1) is located at the buried oxide layer (3) of P-type semiconductor substrate (2) upper surface, with three-dimensional cartesian coordinate system to the three-dimensional side of device
To being defined: defining that device transverse direction is x-axis direction, device vertical direction is y-axis direction, device longitudinal direction i.e. third
Dimension direction is z-axis direction；It is characterized in that, along the x-axis direction, being successively set side by side with p-type base area in buried oxide layer (3) upper surface
(7), N-type charge storage layer (16), superjunction N column (41), the junction depth of the p-type base area (7) are 1~2 μm, the superjunction N column
It (41) is 30~50 μm along the width of x-axis, the doping concentration of superjunction N column (41) is 1015~1017cm-3；In the p-type base area
(7) upper layer is set side by side and mutually independent N+ emitter region (8), P+ emitter region (9), P+ emit (9) and N+ emitter region (8)
Junction depth is 0.2~0.5 μm；Being arranged side by side inside the superjunction N column (41) has superjunction P column (42), N-type field stop layer (5), institute
It states superjunction P column (42) to contact with N-type charge storage layer (16), the doping concentration of superjunction P column (42) is 1015~1017cm-3, described
The doping concentration of N-type field stop layer (5) is 1015~1017cm-3, the junction depth of N-type field stop layer (5) is more than or equal to superjunction P column
(42) junction depth, the junction depth of N-type field stop layer (5) are less than or equal to the junction depth of superjunction N column (41), the knot of N-type field stop layer (5)
The deep junction depth for being greater than or equal to p-type base area (7)；Superjunction P column (42) upper layer is provided with p type buried layer (17), the p-type is buried
The doping concentration of layer (17) is 1016~1018cm-3, p type buried layer (17) contacts with N-type charge storage layer (16), the p type buried layer
(17) junction depth is less than or equal to the junction depth of superjunction P column (42)；N-type field stop layer (5) upper layer is provided with p-type collecting zone
(6), the junction depth of the p-type collecting zone (6) is less than or equal to the junction depth of N-type field stop layer (5)；The p-type emitter region (9),
Part N-type emitter region (8) upper surface is provided with emitter metal (14)；The part N-type emitter region (8), p-type base area (7),
N-type charge storage layer (16), p type buried layer (17) upper surface are provided with gate dielectric layer (10)；Along the z-axis direction, in the gate medium
Layer (10) upper surface is disposed with polycrystalline gate electrode (11), dielectric layer (18), polycrystalline separate gate electrodes (19), dielectric layer
(18) effect is isolation polycrystalline gate electrode (11) and polycrystalline separate gate electrodes (19)；Emitter metal (14) passes through dielectric layer
(13) it is isolated with polycrystalline gate electrode (11)；Have in the p type buried layer (9), superjunction P column (42), N-type field stop layer (5) upper surface
There are dielectric layer (12)；Along the z-axis direction, the N+ emitter region (8) is only located at below gate electrode (11), the separate gate electrodes (19)
It is connected directly with emitter metal (14)；P-type collecting zone (6) upper surface has collector electrode metal (15).
2. a kind of transversal I GBT, comprising: P-type semiconductor substrate (2) is located at the underlayer electrode of P-type semiconductor substrate (2) lower surface
(1), it is located at the buried oxide layer (3) of P-type semiconductor substrate (2) upper surface, it is characterised in that being arranged side by side in buried oxide layer upper surface has P
Type base area (7), N-type charge storage layer (16), superjunction N column (41), the junction depth of the p-type base area (7) are 1~2 μm, the superjunction
The width of N column (41) in X direction is 30~50 μm, and the superjunction N column (41) is run through along Z-direction, and superjunction N column (41) are mixed
Miscellaneous concentration is 1015~1017cm-3；The p-type base area (7) it is inner be provided with side by side and mutually independent N+ emitter region (8), P+ hair
It penetrates area (9), the junction depth of P+ emitter region (9) and N+ emitter region (8) is 0.2~0.5 μm, and the p-type emitter region (9) is passed through along Z-direction
It wears；Being arranged side by side inside the superjunction N column (41) has superjunction P column (42), N-type field stop layer (5), the superjunction P column (42)
It is contacted with N-type charge storage layer (16), superjunction P column (42) doping concentration is 1015~1017cm-3, the N-type field stop layer
Doping concentration be 1015~1017cm-3, the junction depth of the N-type field stop layer (5) is greater than or equal to the junction depth of superjunction P column (42),
Institute's superjunction P column (42), N-type field stop layer (5) run through along Z-direction；P type buried layer is internally provided in the superjunction P column (42)
(17), the doping concentration of the p type buried layer (17) is 1016~1018cm-3, the p type buried layer (17) and N-type charge storage layer
(16) it contacts, the junction depth of the p type buried layer (17) is less than or equal to the junction depth of superjunction P column (42), and the p type buried layer (17) is along Z
Direction is run through；It is internally provided with p-type collecting zone (6) in the N-type field stop layer (5), the junction depth of the p-type collecting zone (6) is small
In or be equal to the junction depth of N-type field stop layer (5), the p-type collecting zone (6) runs through along Z-direction；In the p-type emitter region (9), N
Type emitter region (8) upper surface is provided with emitter metal (14)；In the N-type emitter region, p-type base area, N-type charge storage layer
(16), p type buried layer (17) upper surface is provided with gate dielectric layer 10；The gate dielectric layer upper surface is provided with polycrystalline gate electrode
(11), dielectric layer 18, polycrystalline separation gate dielectric layer (19), the effect of dielectric layer (19) be isolation polycrystalline gate electrode (11) with
Polycrystalline separate gate electrodes (19)；N+ emitter region upper surface have dielectric layer (13), the effect of the dielectric layer (13) be every
From emitter metal and polycrystalline gate electrode and polycrystalline separate gate electrodes；It is hindered in the p type buried layer (9), superjunction P column (42), N-type field
Only layer (5) upper surface has dielectric layer (12)；The N-type emitter region is along Z-direction below gate electrode.
3. a kind of transversal I GBT according to claim 1, it is characterised in that by the opening and photoetching, quarter that adjust mask plate
Erosion, filling polycrystalline and etc. make separate gate electrodes (19) and emitter metal (14) are connected directly and separate gate electrodes (19)
L-shaped encirclement gate electrode (114), a kind of transversal I GBT according to claim 2, it is characterised in that by adjusting ion note
Dosage, energy and the time entered makes junction depth of the junction depth of p-type base area (7) less than N-type charge storage layer (16) and p-type base area
(7) it is lived by N-type charge storage layer (16) semi-surrounding.
4. a kind of transversal I GBT according to claim 1, it is characterised in that remove superjunction junction structure.
5. a kind of transversal I GBT according to claim 1, which is characterized in that the semiconductor material of IGBT device using Si,
SiC, GaAs or GaN.
6. a kind of production method of transversal I GBT characterized by comprising
The first step, chooses certain thickness SOI material, and SOI material has n type semiconductor layer, buried oxide layer, P type substrate three parts structure
At n type semiconductor layer doping concentration is 1015~1017A/cm3；The doped layer concentration of P type substrate is 1014~1015A/cm3；
Second step deposits one layer of polycrystalline in oxide layer and passes through light in N-type semiconductor surface oxidation growth layer of oxide layer
It carves, etching forms gate electrode and separate gate electrodes；
Third step grows one layer of pre-oxidation layer, passes through ion implanting N-type impurity using self-registered technology and obtained N-type electricity of annealing
Lotus accumulation layer, the energy of ion implanting are 200~500KeV, implantation dosage 1013~1014A/cm2, annealing temperature 1100
~1200 DEG C, annealing time 10~30 minutes；Ion implanting p type impurity and anneal be made p-type base area, Implantation Energy be 60~
300KeV, implantation dosage 1013~1014A/cm2, annealing temperature is 1100 DEG C~1200 DEG C, and annealing time is 10~30 points
Clock；The energy of ion implanting N-type impurity and p type impurity respectively, ion implanting N-type impurity is 30~60keV, and implantation dosage is
1015~1016A/cm2, the energy of ion implanting p type impurity is 60~80keV, implantation dosage 1015~1016A/cm2, move back
Fiery temperature is 900 DEG C, and the time is 20~30 minutes, and the N+ emitter region and P+ emitter region for contacting with each other and being arranged side by side is made；From
Superjunction P column is made in sub- injecting p-type impurity and annealing, and Implantation Energy is 100~400KeV, implantation dosage 1012~1013A/
cm2, annealing temperature is 1100 DEG C~1200 DEG C, and annealing time is 10~40 minutes；P type buried layer is made in ion implanting p type impurity,
Ion implantation energy is 30~60keV, implantation dosage 1013~1015A/cm2, ion implanting N-type impurity and anneal be made N-type
Field stop layer, ion implantation energy are 200~500KeV, implantation dosage 1013~1014A/cm2, annealing temperature be 1100~
1200 DEG C, annealing time 10~50 minutes；P-type collecting zone is made in ion implanting p type impurity, and Implantation Energy is 40~60KeV, note
Entering dosage is 1012~1013A/cm2。
4th step, positive dielectric layer deposited and by photoetching, etching and etc. etch emitter metal contact zone and current collection
Pole metal contact zone simultaneously deposits metal and etches away redundance metal and produce emitter metal and collector electrode metal；
5th step overturns silicon wafer and deposits metal production underlayer electrode.
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| CN114937689A (en) * | 2022-06-06 | 2022-08-23 | 电子科技大学 | Planar SiC IGBT and manufacturing method thereof |
| CN117497579A (en) * | 2023-12-28 | 2024-02-02 | 深圳天狼芯半导体有限公司 | Silicon carbide IGBT structure, manufacturing method and electronic equipment |
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