CN106847884A - The SOI LIGBT device architectures of low turn-off power loss - Google Patents
The SOI LIGBT device architectures of low turn-off power loss Download PDFInfo
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- CN106847884A CN106847884A CN201710110296.6A CN201710110296A CN106847884A CN 106847884 A CN106847884 A CN 106847884A CN 201710110296 A CN201710110296 A CN 201710110296A CN 106847884 A CN106847884 A CN 106847884A
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 7
- 239000001301 oxygen Substances 0.000 claims abstract description 7
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 230000008859 change Effects 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 230000011218 segmentation Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 4
- 206010019133 Hangover Diseases 0.000 abstract description 3
- 230000000630 rising effect Effects 0.000 abstract description 3
- 230000009467 reduction Effects 0.000 abstract description 2
- 230000005684 electric field Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of SOI LIGBT device architectures of low turn-off power loss, including P type substrate, oxygen buried layer silica, N-type drift region, P type trap zone, N buffer layers, the oxide layer for setting gradually from bottom to up；P type trap zone inner upper is provided with N-type source and p-type contact zone；N buffer layers of inner upper is provided with N-type anode region；N type buried layer, and/or p type buried layer are provided with the inside of N-type drift region；The present invention is reduced the conducting resistance of device architecture；V is caused in turn off processAThe speed of rising is slower before p type buried layer is not depleted, the V when P-type layer exhausts completeAIncrease severely；At border of the depletion region near p type buried layer, a good leakage path is provided to the hole stored in drift region, cause the holoe carrier of storage to exclude speed and accelerate, hangover time reduction；Based on the two effects, the turn-off power loss of structure of the present invention is significantly reduced.
Description
Technical field
The invention belongs to technical field of semiconductors, more particularly to a kind of SOI-LIGBT device junctions of low turn-off power loss
Structure.
Background technology
High voltage power device is basis and the core of Power Electronic Technique, and it has high pressure resistant, conducting current density big
Feature.The voltage endurance capability of power device is improved, it is the key for designing device to reduce power device turn-off power loss.IGBT device is (absolutely
Edge grid bipolar transistor device) as the important power semiconductor of a class, it is widely used in field of power electronics.But
It is that IGBT device is relatively low with N- drift regions intersection hole injection efficiency due to P-body areas, and carrier concentration profile is very low, leads
Cause the saturation voltage drop of device to raise, when off, substantial amounts of minority carrier is stored in N- drift regions, cause device to turn off electricity
Stream conditions of streaking is serious, and turn-off power loss is big.Generally improving the mode of turn-off power loss has two kinds, and one kind is to reduce carrier lifetime,
Another kind is the Buffer resistance layer of increase near anode.First way is very high to technological requirement, although and second work
Difficulty is little in skill, but it is not ideal enough to reduce the effect of turn-off power loss.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to solve problem, there is provided a kind of low shut-off is damaged
SOI-LIGBT the device architectures of consumption.
For achieving the above object, technical solution of the present invention is as follows：
A kind of SOI-LIGBT device architectures of low turn-off power loss, including set gradually from bottom to up P type substrate, bury oxygen
Layer silica, N-type drift region, be arranged at N-type drift region inside one end P type trap zone, be arranged at N-type drift region inside it is another
N-buffer layers of end, the oxide layer above N-type drift region；The P type trap zone inner upper is provided with N-type source and and N-type
The adjacent p-type contact zone of source；The N-buffer layers of inner upper is provided with N-type anode region；The N-type source, p-type contact zone
And N-type anode region top is respectively equipped with metal level；Raceway groove top between the N-type source and P type trap zone is grid oxide layer, grid oxygen
Layer top is polysilicon；It is characterized in that：N type buried layer, and/or p type buried layer are provided with the inside of N-type drift region, the p-type is buried
Layer is located at n type buried layer lower section, and the n type buried layer, p type buried layer are not directly connected to P type trap zone and N-buffer areas.
It is preferred that, at least 2 n type buried layers, at least 2 p type buried layers are provided with the inside of N-type drift region, N-type is buried
Layer and p type buried layer are arranged alternately.Being arranged alternately can reduce conducting resistance, and introduces multiple carrier leakage paths thus can subtract
Few turn-off power loss.
It is preferred that, the distance of p type buried layer and P type trap zone is d, and d values are 0.4 μm, apart from d and p type buried layer
Length LPBSum is less than drift region length Ld.When d values are 0.4 μm, turn-off power loss is minimum.
It is preferred that, adjacent n type buried layer and p type buried layer connects up and down, each n type buried layer and p type buried layer left end
Distance to P type trap zone is equal, and each n type buried layer and p type buried layer right-hand member to N-buffer layers of distance are equal.Apart from it is equal when
The uniform cross of PN junction, causes that Electric Field Distribution more optimizes during pressurization, so that the pressure-resistant performance of device is more preferable.
It is preferred that, n type buried layer and p type buried layer change opposite types material into simultaneously.
It is preferred that, it is provided only with a n type buried layer and a p type buried layer.
It is preferred that, p type buried layer is the buried regions of segmentation.
Beneficial effects of the present invention are：Compared with the conventional SOI-LIGBT devices, because n type buried layer, p type buried layer draw
Enter, the conducting resistance of device architecture is reduced；Due to the introducing of p type buried layer, bulky capacitor effect is produced in turn off process, made
Obtain VAThe speed of rising is slower before p type buried layer is not depleted, the V when P-type layer exhausts completeAIncrease severely；It is close in depletion region
During the border of p type buried layer, due to the introducing of p type buried layer, to the hole stored in drift region provide one it is good release it is logical
Road, causes the holoe carrier of storage to exclude speed and accelerates, hangover time reduction；So the two effects are based on, present invention knot
The turn-off power loss of structure is significantly reduced.
Brief description of the drawings
Fig. 1 is traditional SOI-LIGBT device architecture profiles.
Fig. 2 is the device architecture profile of embodiment 2.
Fig. 3 is the device architecture profile of embodiment 1.
Fig. 4 is the device architecture profile of embodiment 3.
Fig. 5 is the turn-off characteristic comparison diagram of embodiment 1 and traditional structure.
Fig. 6 is the E of embodiment 1 and traditional structureoff-VonRelation comparison diagram.
Fig. 7 is the device architecture profile of embodiment 4.
Wherein, 1 is N-type anode region, and 2 is N-buffer layers, and 3 is N-type drift region, and 4 is P type trap zone, and 5 is N-type source, 6
It is p-type contact zone, 7 is polysilicon, and 8 is oxygen buried layer silica, and 9 is P type substrate, and 10 is oxide layer, and 11 is n type buried layer, 21
It is p type buried layer.
Specific embodiment
Embodiments of the present invention are illustrated below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages of the invention and effect easily.The present invention can also be by specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Embodiment 1
As shown in figure 3, a kind of SOI-LIGBT device architectures of low turn-off power loss, including the p-type for setting gradually from bottom to up
Substrate 9, oxygen buried layer silica 8, N-type drift region 3, the P type trap zone 4 for being arranged at the inside one end of N-type drift region 3, it is arranged at N-type
N-buffer layers 2, the oxide layer 10 of the top of N-type drift region 3 of the inside other end of drift region 3；The inner upper of the P type trap zone 4
It is provided with N-type source 5 and the p-type contact zone 6 adjacent with N-type source 5；N-buffer layers of 2 inner upper are provided with N-type anode
Area 1；The N-type source 5, p-type contact zone 6 and the top of N-type anode region 1 are respectively equipped with metal level；The N-type source 5 and p-type
Raceway groove top between well region 4 is grid oxide layer, and grid oxide layer top is polysilicon 7；A N-type is provided with the inside of N-type drift region 3 to bury
Layer 11, the lower section of n type buried layer 11 is provided with a p type buried layer 21, and the n type buried layer 11, p type buried layer 21 not with P type trap zone 4
It is directly connected to N-buffer areas 2.
P type buried layer 21 is d with the distance of P type trap zone 4, and d values are 0.4 μm, apart from the d and length L of p type buried layer 21PBIt
With less than drift region length Ld.When d values are 0.4 μm, turn-off power loss is minimum.
Adjacent n type buried layer 11 and p type buried layer connects about 21, each n type buried layer 11 and the left end of p type buried layer 21 to p-type
The distance of well region 4 is equal, and each distance of n type buried layer 11 with the right-hand member of p type buried layer 21 to N-buffer layers 2 is equal.Apart from equal
When PN junction uniform cross, cause that Electric Field Distribution more optimizes during pressurization, so that the pressure-resistant performance of device is more preferable.
N type buried layer 11 and p type buried layer 21 can simultaneously change opposite types material into.
Specifically, the thickness t of oxygen buried layer silica 8oxIt is 3 μm, the thickness t of silicon layer thickness namely N-type drift region 3sIt is 6
Micron, the length L of N-type drift region 3dIt is 30 μm, doping concentration NdIt is 1e16cm-3, gate oxide thickness is 20nm, and P type trap zone 4 is mixed
Miscellaneous concentration NpwellIt is 2e17cm-3, N-buffer layers 2 of doping concentration is 8e17cm-3, p type buried layer 21 is apart from silicon surface
DPB1.8 μm, be 0.6 μm, its length L with the interval of P type trap zone 4 dPBIt is 29 μm, thickness TPBIt is 2 μm.
The operation principle of the present embodiment is：Due to the introducing of n type buried layer 11, the conducting resistance of device architecture is reduced；
Due to the introducing of p type buried layer 21, bulky capacitor effect is produced in turn off process so that VAThe speed of rising p type buried layer not by
It is slower before exhausting, the V when P-type layer exhausts completeAIncrease sharply to applied voltage VDD；In depletion region near the side of p type buried layer 21
During boundary, due to the introducing of p type buried layer, a good leakage path is provided to the hole stored in drift region, cause storage
Holoe carrier exclude speed it is very fast, hangover time is substantially reduced；It is 2 μ H to use inductive load L, by the imitative of embodiment
True Comparative result, in 100A/cm2Under current density, the turn-off time of the invention is 20ns, turn-off power loss reduces nearly 80%.
Embodiment 2
As shown in Fig. 2 the difference of the present embodiment and embodiment 1 is：At least 2 N are provided with the inside of N-type drift region 3
Type buried regions 11, at least 2 p type buried layers 21, n type buried layer 11 and p type buried layer 21 are arranged alternately.Being arranged alternately can reduce electric conduction
Resistance, and introduce and multiple carrier leakage paths thus turn-off power loss can be reduced.
Adjacent n type buried layer 11 and p type buried layer connects about 21, each n type buried layer 11 and the left end of p type buried layer 21 to p-type
The distance of well region 4 is equal, and each distance of n type buried layer 11 with the right-hand member of p type buried layer 21 to N-buffer layers 2 is equal.Apart from equal
When PN junction uniform cross, cause that Electric Field Distribution more optimizes during pressurization, so that the pressure-resistant performance of device is more preferable.
Embodiment 3
As shown in figure 4, the difference of the present embodiment and embodiment 1 is：Buried in the inside only one of which p-type of N-type drift region 3
Layer 21, does not have n type buried layer 11.Can also only one of which n type buried layer 11, there is no p type buried layer 21.
Embodiment 4
As shown in fig. 7, the difference of the present embodiment and embodiment 1 is：Buried in the inside only one of which N-type of N-type drift region 3
Layer 11, does not have p type buried layer 21.And p type buried layer 21 is the buried regions of segmentation.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
The personage for knowing this technology all can carry out modifications and changes under without prejudice to spirit and scope of the invention to above-described embodiment.Cause
This, all those of ordinary skill in the art are completed under without departing from disclosed spiritual and technological thought
All equivalent modifications or change, should be covered by claim of the invention.
Claims (7)
1. a kind of SOI-LIGBT device architectures of low turn-off power loss, including set gradually from bottom to up P type substrate (9), bury oxygen
Layer silica (8), N-type drift region (3), the P type trap zone (4) for being arranged at the internal one end of N-type drift region (3), it is arranged at N-type drift
Move the oxide layer (10) above the N-buffer floor (2) of the other end, N-type drift region (3) inside area (3)；The P type trap zone (4)
Inner upper is provided with N-type source (5) and the p-type contact zone (6) adjacent with N-type source (5)；In described N-buffer layers (2)
Portion top is provided with N-type anode region (1)；The N-type source (5), p-type contact zone (6) and N-type anode region (1) top set respectively
There is metal level；Raceway groove top between the N-type source (5) and P type trap zone (4) is grid oxide layer, and grid oxide layer top is polysilicon
(7)；It is characterized in that：N type buried layer (11), and/or p type buried layer (21) are provided with the inside of N-type drift region (3), the p-type is buried
Layer (21) positioned at n type buried layer (11) lower section, and the n type buried layer (11), p type buried layer (21) not with P type trap zone (4) and N-
Buffer areas (2) are directly connected to.
2. SOI-LIGBT device architectures of a kind of low turn-off power loss according to claim 1, it is characterised in that：In N-type drift
The inside for moving area (3) is provided with least 2 n type buried layers (11), at least 2 p type buried layers (21), n type buried layer (11) and p type buried layer
(21) it is arranged alternately.
3. SOI-LIGBT device architectures of a kind of low turn-off power loss according to claim 1, it is characterised in that：P type buried layer
(21) it is d with the distance of P type trap zone (4), d values are 0.4 μm, apart from the d and length L of p type buried layer (21)PBSum is less than drift
Section length Ld。
4. SOI-LIGBT device architectures of a kind of low turn-off power loss according to claim 1, it is characterised in that：Adjacent N
Type buried regions (11) and p type buried layer (21) connect up and down, each n type buried layer (11) and p type buried layer (21) left end to P type trap zone (4)
Distance it is equal, each distance of n type buried layer (11) and p type buried layer (21) right-hand member to N-buffer layers (2) is equal.
5. SOI-LIGBT device architectures of a kind of low turn-off power loss according to claim 1, it is characterised in that：N type buried layer
And p type buried layer (21) is while change opposite types material into (11).
6. SOI-LIGBT device architectures of a kind of low turn-off power loss according to claim 1, it is characterised in that：It is provided only with
One n type buried layer (11) and a p type buried layer (21).
7. SOI-LIGBT device architectures of a kind of low turn-off power loss according to claim 1, it is characterised in that：P type buried layer
(21) be segmentation buried regions.
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| CN201710110296.6A CN106847884A (en) | 2017-02-28 | 2017-02-28 | The SOI LIGBT device architectures of low turn-off power loss |
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| CN201710110296.6A CN106847884A (en) | 2017-02-28 | 2017-02-28 | The SOI LIGBT device architectures of low turn-off power loss |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110473917A (en) * | 2019-08-22 | 2019-11-19 | 电子科技大学 | A kind of transversal I GBT and preparation method thereof |
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2017
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| CN110473917A (en) * | 2019-08-22 | 2019-11-19 | 电子科技大学 | A kind of transversal I GBT and preparation method thereof |
| CN110473917B (en) * | 2019-08-22 | 2020-09-29 | 电子科技大学 | Transverse IGBT and manufacturing method thereof |
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Application publication date: 20170613 |