CN106449759A - Isolated LDMOS structure and manufacturing method thereof - Google Patents
Isolated LDMOS structure and manufacturing method thereof Download PDFInfo
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- CN106449759A CN106449759A CN201610995571.2A CN201610995571A CN106449759A CN 106449759 A CN106449759 A CN 106449759A CN 201610995571 A CN201610995571 A CN 201610995571A CN 106449759 A CN106449759 A CN 106449759A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000009792 diffusion process Methods 0.000 claims abstract description 37
- 238000002955 isolation Methods 0.000 claims abstract description 31
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 230000005684 electric field Effects 0.000 abstract description 7
- 230000003647 oxidation Effects 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 230000005764 inhibitory process Effects 0.000 abstract 1
- 230000008859 change Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000008094 contradictory effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention provides an isolated LDMOS structure and a manufacturing method thereof. The isolated LDMOS structure comprises an isolation trench structure and an LDMOS structure which are integrated on a P-type substrate, wherein the isolation trench structure is positioned inside a position, between a second P-type heavily-doped region and a P-type diffusion well region of the LDMOS structure, of the P-type substrate and comprises at least one trench, filling media inside the trench, a first P region at the bottom of the trench and a first oxidation layer at the edge of the trench, and a third oxidation layer of an LDMOS is disposed on the upper surface of the trench. The isolated LDMOS structure and the manufacturing method thereof have the advantages that the bottom of the isolation trench is injected with semiconductor impurities as same as substrate doped materials in type, so that the problem that the surface of a source end is subjected to breakdown in advance is solved, and breakdown voltage is further enhanced; trench isolation is beneficial to inhibition of lateral expansion of an LDMOS well region, so that the area and the size of a device are reduced; electric field distribution close to the source end is changed, and doping concentration of a drift region is increased, so that withstanding voltage of the device is enhanced, specific on-resistance of the device is reduced, and a relationship between the specific on-resistance and breakdown voltage is further optimized.
Description
Technical field
The invention belongs to technical field of semiconductors, and in particular to a kind of isolated form LDMOS structure and its manufacture method.
Background technology
LDMOS (Lateral Double-Diffused MOSFET) is a kind of conventional semiconductor device, with Gao Gong
The advantages of rate gain, high efficiency and low cost, in semiconductor technology using quite extensive.For improving LDMOS breakdown voltage, increase
Big output, generally using the method for increasing drift region length and reduce drift doping concentration, this will cause device ratio to be led
Energising resistance increases, and increases power consumption.Since proposing from RESURF technology and groove isolation technique, Single-RESURF LDMOS,
Double RESURF LDMOS、Triple RESURF LDMOS、Multiple RESURF LDMOS、3D RESURF
The improved structures such as LDMOS, SJ LDMOS have significant effect to reduction than conducting resistance.But this class formation can not change completely
Electric Field Distribution problem in kind device body, however it remains the problem of contradiction that device is pressure and conducting resistance between.
Content of the invention
The present invention is for LDMOS breakdown voltage and contradictory relation than conducting resistance, it is proposed that a kind of isolated form LDMOS knot
Structure and its manufacture method.
For achieving the above object, technical solution of the present invention is as follows：
A kind of isolated form LDMOS structure, the isolation moat structure and LDMOS including being integrated on same P type substrate substrate is tied
Structure；The isolation moat structure is located in the P type substrate between the second p-type heavily doped region of LDMOS structure and p-type diffusion well region
Portion, isolation moat structure includes the first oxidation of filled media inside at least one groove, groove, a P area of trench bottom, groove edge
Layer, first oxide layer is used for the semiconductor silicon material outside filled media and groove inside isolation channel, and groove upper surface is
3rd oxide layer of LDMOS.
It is preferred that, the LDMOS structure be Single-RESURF LDMOS, Double RESURF LDMOS,
Triple RESURF LDMOS, Multiple RESURF LDMOS, 3D RESURF LDMOS, SJ LDMOS one kind therein.
It is preferred that, the LDMOS structure includes P type substrate, N-type diffusion well region, p-type diffusion well region, the 2nd P
Area, the first p-type heavily doped region, the second p-type heavily doped region, the first N-type heavily doped region, the second N-type heavily doped region, the second oxidation
Layer, the 3rd oxide layer, grid, source electrode, drain electrode, underlayer electrode, body electrode；N-type diffusion well region be located in P type substrate and
Its upper surface is concordant with P type substrate upper surface, and the p-type diffusion well region, the 2nd P area, the second N-type heavily doped region are all located at N-type
Interior and its upper surface of diffusion well region is all concordant with the upper surface of N-type diffusion well region, and the 2nd P area is located at p-type diffusion well region and the 2nd N
Between type heavily doped region, the first p-type heavily doped region, the first N-type heavily doped region are located in p-type diffusion well region and its upper surface
All concordant with p-type diffusion well region upper surface, the second p-type heavily doped region is located in P type substrate and its upper surface and P type substrate
Upper surface is concordant, and the 3rd oxide layer is located between p-type diffusion well region and the second N-type heavily doped region and covers N-type diffusion trap
Area, the surface in the 2nd P area, second oxide layer Wei Yu the first N-type heavily doped region and the 3rd oxide layer between and covers p-type expansion
The surface of scattered well region, the grid is located at the second oxide layer upper surface, and the source electrode connects the first N-type heavily doped region current potential, institute
Drain electrode the second N-type heavily doped region current potential of connection is stated, the underlayer electrode connects the second p-type heavily doped region current potential, the body area electricity
Pole connects the first p-type heavily doped region current potential.
It is preferred that, the depth of the groove spreads the depth of well region more than N-type.
It is preferred that, the depth of the groove spreads 1 μm～3 μm of the depth of well region more than N-type.So preferably can enter
Row isolation, reduces substrate leakage, improves the electric field near source region.
It is preferred that, the dosage of the trench bottom implanting p-type impurity is more than 1012cm-2.So preferably can carry out
Isolation, reduces substrate leakage, improves the electric field near source region.
It is preferred that, the shape of the groove is that bar shaped, trapezoidal, inverted trapezoidal, stairstepping are therein one or more.
It is preferred that, side wall of the groove in LDMOS structure side injects N-type impurity by tiltedly note.
It is preferred that, in the device, each doping type is accordingly changed into contrary doping type, i.e. p-type doping is changed into
While n-type doping, n-type doping is changed into p-type doping.
For achieving the above object, the present invention also provides a kind of manufacture method of above-mentioned isolated form LDMOS structure, including
Following steps：
Step 1：Using P-type silicon piece as substrate；
Step 2：Form isolation channel, groove sidewall and bottom oxide；
Step 3：Trench bottom implanting p-type impurity；
Step 4：Filling slot medium；
Step 5：Pre- oxygen, photoetching N-type spreads well region window, carries out N-type diffusion well region injection, knot, etches unnecessary oxygen
Change layer；
Step 6：LDMOS manufacturing process.
The present invention is for LDMOS breakdown voltage and contradictory relation than conducting resistance, it is proposed that a kind of isolated form LDMOS knot
Structure and its manufacture method.Semiconductor device of the present invention is in the injection of isolation trench bottom and backing material doping type identical quasiconductor
Impurity, solves source surface and shifts to an earlier date breakdown problem, improves breakdown voltage further.Meanwhile, groove isolation contributes to suppressing LDMOS trap
The horizontal expansion in area, reduces device area size.The present invention changes the Electric Field Distribution near source, improves drift doping concentration, enters
And raising device is pressure and reduces than conducting resistance, optimized than conducting resistance and breakdown voltage relation further.
Beneficial effects of the present invention are：
1st, a kind of isolated form LDMOS structure of the present invention is in the injection of isolation trench bottom and substrate doping type identical quasiconductor
Material, auxiliary drift region exhausts, and reduces the surface field near source, prevents from puncturing near source surface in advance, and with tradition
Groove isolation LDMOS structure is compared, and groove depth is more shallow, and process implementing difficulty reduces and cost reduces；
2nd, a kind of isolation channel of isolated form LDMOS structure of the present invention can suppress the horizontal expansion of N-type well region, reduce sgare chain
Very little, meanwhile, N-type well region side is improved near isolation channel boundary concentration, lifting is longitudinally pressure near source region；
3rd, a kind of isolation channel of isolated form LDMOS structure of the present invention can prevent from mutually going here and there between high voltage integrated circuit device
Disturb, bottom injection reduces substrate leakage with substrate doping type identical semi-conducting material.
4th, a kind of isolation channel of isolated form LDMOS structure of the present invention can be integrated with the LDMOS of different structure, excellent further
Change breakdown voltage and relation than conducting resistance.
5th, a kind of isolation channel of isolated form LDMOS structure of the present invention is near the oblique injection N-type of LDMOS structure side side wall
Impurity, can optimize well region near groove boundary concentration, improve pressure.
Description of the drawings
A kind of isolated form LDMOS structure schematic diagram that Fig. 1 is provided for the present invention.
Fig. 2 is the process simulation schematic diagram of the embodiment of the present invention.
Fig. 3 (1)～Fig. 3 (6) is a kind of technique of the manufacture method of isolated form LDMOS structure provided in an embodiment of the present invention
Schematic flow sheet.
Fig. 4 (1)～Fig. 4 (6) is corresponding process simulation figure in Fig. 3 device manufacturing processes.
Fig. 5 is the variously-shaped schematic diagram of groove 2.
Fig. 6 passes through, for the side wall of LDMOS structure side, the schematic diagram that tiltedly note injects N-type impurity.
Wherein, 1 is a P area, and 2 is groove, and 3 is the first oxide layer, 4 is the 2nd P area, 5 is P type substrate, 6 is N-type diffusion
Well region, 7 be p-type diffusion well region, 8 be the first p-type heavily doped region, 9 be the first N-type heavily doped region, 10 be the second N-type heavy doping
Area, 11 be the second p-type heavily doped region, 12 be the second oxide layer, 13 be grid, 14 be the 3rd oxide layer, 15 be source electrode, 16 for leakage
Pole, 17 are underlayer electrode, and 18 is body electrode, and 20 is Xie Zhu N-type impurity area.
Specific embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art can be by this specification
Disclosed content understands other advantages of the present invention and effect easily.The present invention can also pass through in addition different concrete realities
The mode of applying is carried out or applies, and the every details in this specification can also be based on different viewpoints and application, without departing from
Various modifications and changes are carried out under the spirit of the present invention.
A kind of isolated form LDMOS structure, the isolation moat structure and LDMOS including being integrated on 5 substrate of same P type substrate is tied
Structure；The isolation moat structure is located at the P type substrate 5 between the second p-type heavily doped region 11 of LDMOS structure and p-type diffusion well region 7
Inside, isolation moat structure includes filled media inside at least one groove 2, groove 2, a P area 1 of 2 bottom of groove, 2 edge of groove
First oxide layer 3, first oxide layer 3 is used for the semiconductor silicon material outside filled media and groove 2 inside isolation channel 2,
2 upper surface of groove is the 3rd oxide layer 14 of LDMOS.
The LDMOS structure is Single-RESURF LDMOS, Double RESURF LDMOS, Triple RESURF
LDMOS, Multiple RESURF LDMOS, 3D RESURF LDMOS, SJ LDMOS one kind therein.
Preferably, the LDMOS structure include P type substrate 5, N-type diffusion well region 6, p-type diffusion well region 7, the 2nd P area 4,
First p-type heavily doped region 8, the second p-type heavily doped region 11, the first N-type heavily doped region 9, the second N-type heavily doped region 10, the second oxygen
Change layer 12, the 3rd oxide layer 14, grid 13, source electrode 15, drain electrode 16, underlayer electrode 17, body electrode 18；The N-type spreads trap
Area 6 is located in P type substrate 5 and its upper surface is concordant with 5 upper surface of P type substrate, the p-type spread well region 7, the 2nd P area 4, the
Two N-type heavily doped regions 10 are all located in N-type diffusion well region 6 and its upper surface is all concordant with the upper surface that N-type spreads well region 6, the
Two P areas 4 are located between p-type diffusion well region 7 and the second N-type heavily doped region 10, the first p-type heavily doped region 8, the first N-type weight
Doped region 9 is located in p-type diffusion well region 7 and its upper surface is all concordant with p-type diffusion 7 upper surface of well region, and second p-type is heavily doped
Miscellaneous area 11 is located in P type substrate 5 and its upper surface is concordant with 5 upper surface of P type substrate, and the 3rd oxide layer 14 expands positioned at p-type
Between scattered well region 7 and the second N-type heavily doped region 10 and cover N-type diffusion well region 6, the surface in the 2nd P area 4, described second oxidation
Layer 12 Wei Yu the first N-type heavily doped region 9 and the 3rd oxide layer 14 between and covers the surface that p-type spreads well region 7, the grid 13
Positioned at 12 upper surface of the second oxide layer, the source electrode 15 connects 9 current potential of the first N-type heavily doped region, and the drain electrode 16 connects the 2nd N
10 current potential of type heavily doped region, the underlayer electrode 17 connects 11 current potential of the second p-type heavily doped region, the connection of the body electrode 18 the
One p-type heavily doped region, 8 current potential.
Preferably, the depth of the groove 2 spreads 1 μm～3 μm of the depth of well region 6 more than N-type.So preferably can carry out every
From, reducing substrate leakage, improvement is near the electric field of source region.
The dosage of 2 bottom implanting p-type impurity of the groove is more than 1012cm-2.So can preferably be isolated, be reduced substrate
Electric leakage, improves the electric field near source region.
As shown in figure 5, the shape of the groove 2 is that bar shaped, inverted trapezoidal, trapezoidal, stairstepping are therein one or more.
Preferably, as shown in fig. 6, side wall of the groove 2 in LDMOS structure side injects N-type impurity by tiltedly note, formed
Xie Zhu N-type impurity area 20.
The manufacture method of above-mentioned isolated form LDMOS structure, comprises the following steps：
Step 1：Using P-type silicon piece as substrate；
Step 2：Form isolation channel, groove sidewall and bottom oxide；
Step 3：Trench bottom implanting p-type impurity；Groove sidewall injection N-type impurity forms Xie Zhu N-type impurity area 20；
Step 4：Filling slot medium；
Step 5：Pre- oxygen, photoetching N-type spreads well region window, carries out N-type diffusion well region injection, knot, etches unnecessary oxygen
Change layer；
Step 6：LDMOS manufacturing process.
Used as mode of texturing, in the device, each doping type is accordingly changed into contrary doping type, i.e. p-type doping is changed into
While n-type doping, n-type doping is changed into p-type doping.
Above-described embodiment only principle of the illustrative present invention and its effect, not for the restriction present invention.Any ripe
The personage for knowing this technology all can carry out modifications and changes without prejudice under the spirit and the scope of the present invention to above-described embodiment.Cause
This, all those of ordinary skill in the art are completed under without departing from disclosed spirit and technological thought
All equivalent modifications or change, must be covered by the claim of the present invention.
Claims (10)
1. a kind of isolated form LDMOS structure, it is characterised in that：Including the isolation channel knot being integrated on same P type substrate (5) substrate
Structure and LDMOS structure；
The isolation moat structure is located at the p-type between the second p-type heavily doped region (11) of LDMOS structure and p-type diffusion well region (7)
Substrate (5) is internal, and isolation moat structure includes the internal filled media of at least one groove (2), groove (2), a P of groove (2) bottom
Area (1), first oxide layer (3) at groove (2) edge, described first oxide layer (3) be used for the internal filled media of isolation channel (2) with
The outside semiconductor silicon material of groove (2), groove (2) upper surface is the 3rd oxide layer (14) of LDMOS.
2. isolated form LDMOS structure according to claim 1, it is characterised in that：The LDMOS structure is Single-
RESURF LDMOS、Double RESURF LDMOS、Triple RESURF LDMOS、Multiple RESURF LDMOS、3D
RESURF LDMOS, SJ LDMOS one kind therein.
3. isolated form LDMOS structure according to claim 2, it is characterised in that：The LDMOS structure includes P type substrate
(5), N-type diffusion well region (6), p-type diffusion well region (7), the 2nd P area (4), the first p-type heavily doped region (8), the second p-type heavy doping
Area (11), the first N-type heavily doped region (9), the second N-type heavily doped region (10), the second oxide layer (12), the 3rd oxide layer (14),
Grid (13), source electrode (15), drain electrode (16), underlayer electrode (17), body electrode (18)；N-type diffusion well region (6) is located at P
In type substrate (5) and its upper surface is concordant with P type substrate (5) upper surface, the p-type spread well region (7), the 2nd P area (4), the
Two N-type heavily doped regions (10) are all located in N-type diffusion well region (6) and its upper surface is all put down with the upper surface of N-type diffusion well region (6)
Together, the 2nd P area (4) is located between p-type diffusion well region (7) and the second N-type heavily doped region (10), the first p-type heavily doped region
(8), the first N-type heavily doped region (9) is located in p-type diffusion well region (7) and its upper surface all spreads well region (7) upper surface with p-type
Concordantly, described second p-type heavily doped region (11) be located at P type substrate (5) in and its upper surface is concordant with P type substrate (5) upper surface,
3rd oxide layer (14) is located between p-type diffusion well region (7) and the second N-type heavily doped region (10) and covers N-type diffusion trap
Area (6), the surface in the 2nd P area (4), described second oxide layer (12) are located at the first N-type heavily doped region (9) and the 3rd oxide layer
(14) between and cover p-type diffusion well region (7) surface, described grid (13) be located at the second oxide layer (12) upper surface, described
Source electrode (15) connects the first N-type heavily doped region (9) current potential, and described drain electrode (16) connect the second N-type heavily doped region (10) current potential, institute
State underlayer electrode (17) and connect the second p-type heavily doped region (11) current potential, described body electrode (18) connect the first p-type heavily doped region
(8) current potential.
4. isolated form LDMOS structure according to claim 1, it is characterised in that：The depth of groove (2) expands more than N-type
The depth of scattered well region (6).
5. isolated form LDMOS structure according to claim 4, it is characterised in that：The depth of groove (2) expands more than N-type
1 μm～3 μm of the depth of scattered well region (6).
6. isolated form LDMOS structure according to claim 1, it is characterised in that：Groove (2) bottom implanting p-type impurity
Dosage be more than 1012cm-2.
7. isolated form LDMOS structure according to claim 1, it is characterised in that：The shape of groove (2) is bar shaped, ladder
Shape, inverted trapezoidal, stairstepping are therein one or more.
8. isolated form LDMOS structure according to claim 1, it is characterised in that：Groove (2) are in LDMOS structure side
Side wall by tiltedly note injection N-type impurity.
9. isolated form LDMOS structure according to claim 1, it is characterised in that：In the device, each doping type is corresponding
It is changed into contrary doping type, i.e., while p-type doping is changed into n-type doping, n-type doping is changed into p-type doping.
10. the manufacture method of the isolated form LDMOS structure according to claim 1 to 9 any one, it is characterised in that include
Following steps：
Step 1：Using P-type silicon piece as substrate；
Step 2：Form isolation channel, groove sidewall and bottom oxide；
Step 3：Trench bottom implanting p-type impurity；
Step 4：Filling slot medium；
Step 5：Pre- oxygen, photoetching N-type spreads well region window, carries out N-type diffusion well region injection, knot, etches unnecessary oxide layer；
Step 6：LDMOS manufacturing process.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108074966A (en) * | 2017-12-27 | 2018-05-25 | 电子科技大学 | Constant current device and its manufacturing method |
| CN114823856A (en) * | 2022-04-26 | 2022-07-29 | 电子科技大学 | High-voltage integrated power semiconductor device and manufacturing method thereof |
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| US5789769A (en) * | 1995-01-24 | 1998-08-04 | Nec Corporation | Semiconductor device having an improved trench isolation |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108074966A (en) * | 2017-12-27 | 2018-05-25 | 电子科技大学 | Constant current device and its manufacturing method |
| CN114823856A (en) * | 2022-04-26 | 2022-07-29 | 电子科技大学 | High-voltage integrated power semiconductor device and manufacturing method thereof |
| CN114823856B (en) * | 2022-04-26 | 2023-10-27 | 电子科技大学 | High-voltage integrated power semiconductor device and manufacturing method thereof |
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