CN104103694A - Trench type insulated gate field effect transistor and manufacture method thereof - Google Patents
Trench type insulated gate field effect transistor and manufacture method thereof Download PDFInfo
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- CN104103694A CN104103694A CN201410357032.7A CN201410357032A CN104103694A CN 104103694 A CN104103694 A CN 104103694A CN 201410357032 A CN201410357032 A CN 201410357032A CN 104103694 A CN104103694 A CN 104103694A
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- 230000005669 field effect Effects 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 230000003647 oxidation Effects 0.000 claims abstract description 19
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 29
- 238000000407 epitaxy Methods 0.000 claims description 27
- 238000009413 insulation Methods 0.000 claims description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000002513 implantation Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 241000293849 Cordylanthus Species 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 230000003139 buffering effect Effects 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 7
- 230000007704 transition Effects 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 210000004027 cell Anatomy 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000012913 prioritisation Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention belongs to the technical field of insulated gate field effect transistors and particularly relates to a trench type insulated gate field effect transistor and a manufacture method thereof. According to the trench type insulated gate field effect transistor, a thick insulating medium layer is arranged at the bottom of a grid trench so as to increase breakdown voltage of the insulated gate field effect transistor and reduce stray capacitance of the insulated gate field effect transistor; meanwhile, a small groove is formed in the bottom of the grid trench, so that a field oxidation stress transition area is extended, the problem of current leakage caused by field oxidation stress is well solved, and reliability of devices is improved. According to the trench type insulated gate field effect transistor and the manufacture method thereof, by means of a self-alignment process, the groove in the bottom of the grid trench is formed, the process is simple, and the trench type insulated gate field effect transistor is easy to control.
Description
Technical field
The invention belongs to isolated-gate field effect transistor (IGFET) (IGBT) technical field, particularly relate to a kind of groove-shaped isolated-gate field effect transistor (IGFET) and manufacture method thereof.
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Background technology
Isolated-gate field effect transistor (IGFET) (IGBT) is a kind of device being composited by MOS transistor and bipolar transistor, it inputs very MOS transistor, export very PNP(or NPN) transistor, it has merged the advantage of these two kinds of devices, both had advantages of that MOS transistor driving power was little and switching speed is fast, having again bipolar device saturation pressure reduces and advantage capacious, its frequency characteristic is between MOS transistor and power transistor, can normally work in tens kHz frequency ranges, in modern power electronics technology, obtain application more and more widely, particularly occupy the large of upper frequency, the leading position of middle power tube application.
Known groove-shaped isolated-gate field effect transistor (IGFET) device architecture as shown in Figure 1, on drain region 54, be formed with resilient coating 26 and drift region 100, the bottom of U-shaped groove extends in drift region 100, and cover U-shaped groove and be formed with gate oxide 31 and grid 35, the IGBT device of this structure is to reduce conducting resistance need to improve the doping content of drift region 100, but this can reduce the puncture voltage of IGBT device.For the problems referred to above, Chinese patent application 201210148320.2 has proposed one and has improved one's methods, its cross-section structure as shown in Figure 2, in U-shaped groove, fill the polysilicon with the contrary doping type in drift region, thereby in drift region, form super-junction structure, to improve the puncture voltage of device, the IGBT device of this structure, after need to digging deep trouth, recharge polysilicon, technology difficulty is large; Meanwhile, the IGBT device of prior art is all the gate oxide that forms even thickness on the surface of U-shaped groove, need to increase gate oxide thickness, but gate oxide thickness increase can improve again the operating voltage of device for reducing grid oxygen electric capacity.
Summary of the invention
The object of the invention is provides a kind of groove-shaped isolated-gate field effect transistor (IGFET) and manufacture method thereof for overcoming the deficiencies in the prior art, the present invention passes through at the preset little groove in the bottom of U-shaped groove, carry out again the oxidation of field oxide, guarantee that an oxidation stress transition region is extended, greatly to reduce the leakage current that oxidation stress causes and to improve the reliability of device, also can reduce grid oxygen electric capacity simultaneously, improve the operating rate of device.
The groove-shaped isolated-gate field effect transistor (IGFET) of one proposing according to the present invention, it comprises:
The drain region of the second doping type of Semiconductor substrate bottom, and the drift region that is positioned at the first doping type on described drain region forming in Semiconductor substrate;
A U-shaped groove in Semiconductor substrate, the bottom of this U-shaped groove extends into described drift region;
The channel region of the second doping type in Semiconductor substrate and the source region of the first doping type, this channel region and source region lay respectively at the sidewall both sides of U-shaped groove, and this source region is positioned at this top, channel region;
On two sidewalls of described U-shaped groove, be provided with the gate oxide that covers described channel region;
Characterized by further comprising:
The field oxide forming in the bottom of described U-shaped groove, the both sides of this field oxide are bird's beak shape, and the thickness of this field oxide is greater than the thickness of described gate oxide;
In described U-shaped groove, be provided with the polysilicon gate that covers described gate oxide and field oxide.
The further prioritization scheme of a kind of groove-shaped isolated-gate field effect transistor (IGFET) of the present invention is:
The bottom of U-shaped groove of the present invention is provided with the groove that an A/F is less than described U-shaped groove opening width, and the degree of depth of this groove is 10-100 nanometer, and described field oxide fills up this groove.
The first doping type of the present invention is N-shaped doping, and described the second doping type is p-type doping; Or described the first doping type is p-type doping, described the second doping type is N-shaped doping.
Between drain region of the present invention and drift region, be provided with the buffering area of the first doping type.
The manufacture method that the present invention is based on above-mentioned a kind of groove-shaped isolated-gate field effect transistor (IGFET), it comprises initial step:
(1) silicon epitaxy layer of extension the first doping type on the drain region of described the second doping type;
(2) in described silicon epitaxy layer, form a U-shaped groove;
(3) form successively ground floor insulation film and second layer insulation film on the surface of described U-shaped groove;
Characterized by further comprising following continuation step:
(4) etch away the second layer insulation film of U-shaped channel bottom by anisotropic lithographic method;
(5) etch away the ground floor insulation film of the U-shaped channel bottom of exposure, and continue to carry out at the bottom position of U-shaped groove the etching of the silicon epitaxy layer of 10-100 nano thickness;
(6) form field oxide by oxidation technology in the bottom of U-shaped groove;
(7) etch away ground floor insulation film and the hard mask layer of described second layer insulation film, exposure completely;
(8) carry out thermal oxidation, on two sidewalls of U-shaped groove, form respectively gate oxide, the thickness of this gate oxide is less than the field oxide thickness that this U-shaped channel bottom forms;
(9) carry out polysilicon deposit and isotropic etching, form the polysilicon gate that covers field oxide and gate oxide in U-shaped groove, the top of this polysilicon gate is lower than the upper surface of silicon epitaxy layer;
(10) carry out Implantation, in the silicon epitaxy layer of U-shaped groove both sides, form the channel region of the second doping type;
(11) carry out source electrode photoetching and Implantation, form the source region of the first doping type at top, channel region.
The further preferred version of the manufacture method of a kind of groove-shaped isolated-gate field effect transistor (IGFET) of the present invention is:
The material of ground floor insulation film of the present invention is silica.
The material of second layer insulation film of the present invention is silicon nitride or silicon oxynitride.
The described Implantation of step of the present invention (10) can then carry out afterwards in step (1), in formation doped region, the top of whole described silicon epitaxy layer, carries out afterwards the etching of U-shaped groove again.
The present invention compared with prior art its remarkable advantage is: first, thick field oxide is formed on the bottom that groove-shaped isolated-gate field effect transistor (IGFET) of the present invention is is gate trench at U-shaped groove, can improve the puncture voltage of isolated-gate field effect transistor (IGFET) and reduce its parasitic capacitance, to improve the operating rate of device; The second, the present invention arranges a little groove in the bottom of U-shaped groove, an oxidation stress is extended in transition region, has solved well the leakage problem that an oxidation stress causes, and has improved the reliability of device; The 3rd, the present invention forms the groove of U-shaped channel bottom by self-registered technology, and technical process is simple, is easy to control.
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Brief description of the drawings
Fig. 1 is the cross-sectional view of a kind of groove-shaped isolated-gate field effect transistor (IGFET) of prior art.
Fig. 2 is the cross-sectional view of the groove-shaped isolated-gate field effect transistor (IGFET) of another kind of prior art.
Fig. 3 is the cross-sectional view of an embodiment of a kind of groove-shaped isolated-gate field effect transistor (IGFET) of the present invention.
Fig. 4 is the cross-sectional view of another embodiment of a kind of groove-shaped isolated-gate field effect transistor (IGFET) of the present invention.
Fig. 5 to Figure 14 is the process flow diagram of an embodiment of the manufacture method of a kind of groove-shaped isolated-gate field effect transistor (IGFET) of the present invention.
Figure 15 is the schematic top plan view of an embodiment of a kind of groove-shaped isolated-gate field effect transistor (IGFET) of the present invention.
Figure 16 is the vertical view schematic diagram of another embodiment of a kind of groove-shaped isolated-gate field effect transistor (IGFET) of the present invention.
Embodiment
For the specific embodiment of the present invention is clearly described, listed diagram in Figure of description, has amplified the thickness in layer of the present invention and region, and shown in feature size do not represent actual size; Accompanying drawing is schematically, should not limit scope of the present invention.In specification, listed embodiment should not only limit to the given shape in region shown in accompanying drawing, but comprise obtained shape as manufactured the deviation that causes etc., etching obtains for another example curve has bending or mellow and full feature conventionally, but all represent with rectangle in embodiments of the present invention; In the following description, the term Semiconductor substrate using can be regarded as and comprises the just semiconductor wafer in processes, also comprises other prepared thin layer thereon simultaneously.
The following stated cross-section structure of the present invention, if no special instructions, is along the cross-section structure of the orientation of employing strip structure cell.
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.
Fig. 3 is the cross-sectional view of an embodiment of a kind of groove-shaped isolated-gate field effect transistor (IGFET) of the present invention, and it is by three parallel-connection structures that groove-shaped isolated-gate field effect transistor (IGFET) forms of the present invention.As shown in Figure 3, groove-shaped isolated-gate field effect transistor (IGFET) of the present invention is included in the drain region 200 of the second doping type in Semiconductor substrate, on drain region 200, be formed with silicon epitaxy layer, in this silicon epitaxy layer, be formed with the drift region 201 of the first doping type, the U-shaped groove forming in silicon epitaxy layer, the bottom of this U-shaped groove extends into drift region 201, the channel region 209 of the second doping type forming respectively in the silicon epitaxy layer of the sidewall both sides of U-shaped groove; The first doping type and the second doping type are contrary doping type, if the first doping type is N-shaped doping, the second doping type is p-type doping; Corresponding, if the first doping type is p-type doping, the second doping type is N-shaped doping.
The gate oxide 207 of the covering channel region 209 forming respectively on two sidewalls of described U-shaped groove, be provided with the groove 400 that A/F is less than U-shaped groove opening width in the bottom of U-shaped groove, the degree of depth of this groove 400 is 10-100 nanometer, the bottom that covers this groove 400 and U-shaped groove is formed with field oxide 206, the both sides of this field oxide 206 are bird's beak shape, and the thickness of this field oxide 206 is greater than the thickness of described gate oxide 207.
Structure detail display in Fig. 3 in corresponding dotted line frame carry out the groove structure of the U-shaped channel bottom before an oxidation, groove 400 is to be the field oxidation stress transition region extending between field oxide 206 and gate oxide 206, solved well leakage problem that an oxidation stress causes and improved device reliability.
As required, also can not form the degree of depth of U-shaped channel bottom be the groove 400 of 10-100 nanometer in the present invention.
The covering gate oxide layer 207 forming in U-shaped groove and the polysilicon gate 208 of field oxide 206, the top of this polysilicon gate 208 is lower than the top of this U-shaped groove, this is to fill insulating barrier for the top at U-shaped groove, makes polysilicon gate 208 and outer electrode insulation; In silicon epitaxy layer, 209 tops, described two channel regions are respectively equipped with the source region 210 of the first doping type; In channel region 209, be also provided with the doped region, channel region 213 of heavily doped the second doping type, this channel doping district 213 is the contact zone with outer electrode as channel region 209.
On source region 210, be formed with the source metal contacting with source region 210 and channel region 209, because the multiple way of contact between source metal and source region 210 and channel region 209 is the known technology of industry, do not describing in detail in the present embodiment.
As required, groove-shaped isolated-gate field effect transistor (IGFET) of the present invention can also be provided with the resilient coating 301 of one deck the first doping type, as shown in Figure 4 between drain region 200 and drift region 201.
Fig. 5 to Figure 14 is the process flow diagram of an embodiment of the manufacture method of a kind of groove-shaped isolated-gate field effect transistor (IGFET) of proposing of the present invention, this embodiment manufactures three groove-shaped isolated-gate field effect transistor (IGFET)s in parallel of the present invention simultaneously, and its concrete implementation step is as follows successively:
In conjunction with Fig. 5, first on the drain region 200 of the second doping type of Semiconductor substrate, extension forms the silicon epitaxy layer 201 of one deck the first doping type, then on silicon epitaxy layer 210, form hard mask layer 202, carry out afterwards photoetching and be etched in a U-shaped groove of formation in silicon epitaxy layer, this hard mask layer 202 generally includes cushion oxide layer that one deck is thin and the silicon nitride medium layer of thick layer, and thin oxide layer is for improving the stress between silicon nitride layer and silicon epitaxy layer.
As required, on drain region 200, also can first form the resilient coating of one deck the first doping type, and then form silicon epitaxy layer 201.
Next, in conjunction with Fig. 6, form ground floor insulation film 203 at the surface oxidation of U-shaped groove, the material of this ground floor insulation film 203 is silica, and its thickness range is 10～20 nanometers; Next, continue to form second layer insulation film 204 on the surface of ground floor insulation film 203, the material of this second layer insulation film 204 is silicon nitride or silicon oxynitride, and its thickness range is 10～20 nanometers preferably.Adopt anisotropic lithographic method, as selected the method for plasma etching, etch away the second layer insulation film 204 of U-shaped channel bottom.
Next, in conjunction with Fig. 7, oxidation processes of the present invention is to form thick field oxide 206 in the bottom of U-shaped groove, and the both sides of this field oxide 206 are bird's beak shape, remove afterwards second layer insulation film 204.
As required, fall at plasma etching after the second layer insulation film 204 of U-shaped channel bottom, can continue to etch away the ground floor insulation film 203 of U-shaped channel bottom, then carry out the etching of the silicon epitaxy layer of 10-100 nano thickness, thereby the groove that an A/F is less than U-shaped groove opening width is formed on the bottom at U-shaped groove, as shown in Figure 8; Carry out again afterwards the oxidation of field oxide 206, form structure as shown in Figure 9; From Fig. 9 and Fig. 7, after a groove is formed on the bottom of U-shaped groove, carry out again field oxide oxidation, can make an oxidation stress transition region be extended.
Next, continue to describe the manufacturing process of a kind of groove-shaped isolated-gate field effect transistor (IGFET) of the present invention with structure shown in Fig. 7.
In conjunction with Figure 10, eating away hard mask layer 202 completely, and wash the ground floor insulation film 203 on two sidewalls of U-shaped groove, then carry out thermal oxidation and form thin gate oxide 207 on two sidewalls of U-shaped groove.
Next, in conjunction with Figure 11, deposit one deck polysilicon also returns and carves, and to form the polysilicon gate 208 of covering gate oxide layer 207 and field oxide 206 in U-shaped groove, the top of the polysilicon gate after etching should be lower than the top of U-shaped groove; Then carry out Implantation, in silicon epitaxy layer, form the channel region 209 of the second doping type; Carry out afterwards photoetching and Implantation, form the source region 210 of the first doping type at 209 tops, channel region.
Finally, in conjunction with Figure 12, carry out a photoetching and Implantation, in contact zone, formation channel region, the top of channel region 209 213, then deposition insulating layer 211 this insulating barrier 211 is returned to quarter, makes insulating barrier 211 after etching be positioned at the top of polysilicon gate and fills up the top of U-shaped groove; The material of this insulating barrier 211 is silica or silicon nitride, and its thickness range is 50～500 nanometers; Last deposited metal forms the source metal 212 contacting with source region 210 and channel region 209.
The specific embodiment of the present invention need to further illustrate:
As required, the Implantation in channel region 209 and source region 210 also can then carry out after silicon epitaxy layer 201 forms, obtain the doped region at whole silicon epitaxy layer top, the U-shaped groove of follow-up formation can separate this doped region and form channel region 209 and the source region 210 of device, to form structure as shown in figure 13, then carry out photoetching, being etched in formation contact hole in silicon epitaxy layer comes out channel region 209, carry out again the Implantation of the second doping type to form contact zone, channel region 213, then deposit layer of metal is to form the source metal 212 contacting with source region 210 and channel region 209, its structure as shown in figure 14.
The device cellular structure into strips of a kind of groove-shaped isolated-gate field effect transistor (IGFET) of the present invention can be also well shape structure.Wherein, as shown in figure 15, the schematic top plan view of well shape structure cell as shown in figure 16 for the schematic top plan view of strip structure cell.
In the specific embodiment of the present invention, all explanations not relating to belong to the known technology of this area, can be implemented with reference to known technology.
Above embodiment and embodiment be to the present invention propose a kind of groove-shaped isolated-gate field effect transistor (IGFET) and the concrete support of manufacture method technological thought; can not limit protection scope of the present invention with this; every technological thought proposing according to the present invention; the change of any equivalent variations of doing on the technical program basis or equivalence, all still belongs to the scope that technical solution of the present invention is protected.
Claims (9)
1. a groove-shaped isolated-gate field effect transistor (IGFET), it comprises:
The drain region of the second doping type of Semiconductor substrate bottom, and the drift region that is positioned at the first doping type on described drain region forming in Semiconductor substrate;
A U-shaped groove in Semiconductor substrate, the bottom of this U-shaped groove extends into described drift region;
The channel region of the second doping type in Semiconductor substrate and the source region of the first doping type, this channel region and source region lay respectively at the sidewall both sides of U-shaped groove, and this source region is positioned at this top, channel region;
On two sidewalls of described U-shaped groove, be provided with the gate oxide that covers described channel region;
Characterized by further comprising:
Bottom at described U-shaped groove is provided with field oxide, and the both sides of this field oxide are bird's beak shape, and the thickness of this field oxide is greater than the thickness of described gate oxide;
In described U-shaped groove, be provided with the polysilicon gate that covers described gate oxide and field oxide.
2. the groove-shaped isolated-gate field effect transistor (IGFET) of one according to claim 1, the bottom that it is characterized in that described U-shaped groove is provided with the groove that an A/F is less than described U-shaped groove opening width, the degree of depth of this groove is 10-100 nanometer, and described field oxide fills up this groove.
3. the groove-shaped isolated-gate field effect transistor (IGFET) of one according to claim 1, is characterized in that described the first doping type is N-shaped doping, and described the second doping type is p-type doping; Or described the first doping type is p-type doping, described the second doping type is N-shaped doping.
4. the groove-shaped isolated-gate field effect transistor (IGFET) of one according to claim 1, is characterized in that being provided with the buffering area of the first doping type between described drain region and drift region.
5. the manufacture method based on a kind of groove-shaped isolated-gate field effect transistor (IGFET) claimed in claim 1, it comprises initial step:
(1) silicon epitaxy layer of extension the first doping type on the drain region of described the second doping type;
(2) in described silicon epitaxy layer, form a U-shaped groove;
(3) form successively ground floor insulation film and second layer insulation film on the surface of described U-shaped groove;
Characterized by further comprising following continuation step:
(4) etch away the second layer insulation film of U-shaped channel bottom by anisotropic lithographic method;
(5) etch away the ground floor insulation film of the U-shaped channel bottom of exposure, and continue to carry out at the bottom position of U-shaped groove the etching of the silicon epitaxy layer of 10-100 nano thickness;
(6) form field oxide by oxidation technology in the bottom of U-shaped groove;
(7) etch away ground floor insulation film and the hard mask layer of described second layer insulation film, exposure completely;
(8) carry out thermal oxidation, on two sidewalls of U-shaped groove, form respectively gate oxide, the thickness of this gate oxide is less than the field oxide thickness that this U-shaped channel bottom forms;
(9) carry out polysilicon deposit and isotropic etching, form the polysilicon gate that covers field oxide and gate oxide in U-shaped groove, the top of this polysilicon gate is lower than the upper surface of silicon epitaxy layer;
(10) carry out Implantation, in the silicon epitaxy layer of U-shaped groove both sides, form the channel region of the second doping type;
(11) carry out source electrode photoetching and Implantation, form the source region of the first doping type at top, channel region.
6. the manufacture method of a kind of groove-shaped isolated-gate field effect transistor (IGFET) according to claim 5, the material that it is characterized in that described ground floor insulation film is silica.
7. the manufacture method of a kind of groove-shaped isolated-gate field effect transistor (IGFET) according to claim 5, the material that it is characterized in that described second layer insulation film is silicon nitride or silicon oxynitride.
8. the manufacture method of a kind of groove-shaped isolated-gate field effect transistor (IGFET) according to claim 5, it is characterized in that the described Implantation of step (10) can then carry out afterwards in step (1), in formation doped region, the top of whole described silicon epitaxy layer, carry out again afterwards the etching of U-shaped groove.
9. the manufacture method of a kind of groove-shaped isolated-gate field effect transistor (IGFET) according to claim 5, is characterized in that step (5) is alternative step.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410357032.7A CN104103694A (en) | 2014-07-25 | 2014-07-25 | Trench type insulated gate field effect transistor and manufacture method thereof |
| PCT/CN2014/083642 WO2016011674A1 (en) | 2014-07-25 | 2014-08-04 | Power mos transistor and manufacturing method therefor |
| US15/028,718 US9698248B2 (en) | 2014-07-25 | 2014-08-04 | Power MOS transistor and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410357032.7A CN104103694A (en) | 2014-07-25 | 2014-07-25 | Trench type insulated gate field effect transistor and manufacture method thereof |
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| CN104465780A (en) * | 2014-12-24 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Groove type field effect transistor and manufacturing method thereof |
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| CN109473474A (en) * | 2018-11-09 | 2019-03-15 | 上海擎茂微电子科技有限公司 | Insulated trench gate electrode bipolar type transistor device and its generation method |
| CN110400847A (en) * | 2019-08-19 | 2019-11-01 | 无锡橙芯微电子科技有限公司 | Trench grate MOS structure and manufacture craft with bottom thick oxide layer |
| CN111883584A (en) * | 2020-08-06 | 2020-11-03 | 苏州华太电子技术有限公司 | Trench gate power device and method for improving gate breakdown voltage of trench gate device |
| CN112349785A (en) * | 2020-11-06 | 2021-02-09 | 中国电子科技集团公司第二十四研究所 | Resistance field plate conductance modulation field effect MOS device and preparation method thereof |
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