CN112701164A - Trench gate semiconductor device and method of manufacturing the same - Google Patents
Trench gate semiconductor device and method of manufacturing the same Download PDFInfo
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- CN112701164A CN112701164A CN202110160130.1A CN202110160130A CN112701164A CN 112701164 A CN112701164 A CN 112701164A CN 202110160130 A CN202110160130 A CN 202110160130A CN 112701164 A CN112701164 A CN 112701164A
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Abstract
The invention discloses a trench gate semiconductor device, comprising: a body region formed in the first epitaxial layer, the gate trench passing through the body region, the gate conductive material layer completely filling a bottom region of the gate trench, the source region being formed on a side of a top region of the gate trench by angled ion implantation self-aligned; a top dielectric layer is formed on the surface of the grid conductive material layer, and first grooves are formed at the vertex angles on the two sides of the top dielectric layer; the bottom of the source contact hole is self-aligned to the surface of the top medium layer formed in the first groove and between the first grooves, and the top surface of the source region in the first groove is in contact with the side face of the source contact hole to achieve the leading-out of the source region. The invention also discloses a manufacturing method of the trench gate semiconductor device. The invention does not need to meet the alignment of lateral isolation between the source contact hole and the trench gate, can reduce the step of the device and the base resistance of the parasitic triode, and simultaneously improves the process window and the producibility.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a trench gate semiconductor device. The invention also relates to a manufacturing method of the trench gate semiconductor device.
Background
The conduction of the parasitic triode of the MOSFET easily causes the MOSFET to be burnt, and has great influence on the durability of the MOSFET. The main method for inhibiting the conduction of the parasitic triode is to reduce the base parasitic resistance (Rb) of the parasitic triode and ensure that the device can endure larger avalanche energy under the condition of a non-clamped Inductive Switching (UIS).
The first trench gate semiconductor device is available:
one way to reduce Rb is to increase the doping concentration in the Rb path, as shown in fig. 1, which is a schematic structural diagram of a first trench gate semiconductor device; taking an N-type trench gate MOSFET as an example, a first conventional trench gate semiconductor device includes:
a P-type base region (base), which is a P-type body region 102, is formed on the N-type epitaxial layer 101, and an N + -doped source region 103 is formed on the surface of the P-type body region 102. The trench gate includes a gate dielectric layer such as a gate oxide layer 104 and a filled polysilicon gate 105 formed in a gate trench. The polysilicon gate 105 in fig. 1 also extends to the surface of the source region 103 outside the gate trench and is isolated from the source region 103 by an oxide layer 104.
A contact hole (CT)107 is also formed through the interlayer film 106 on top of the source region 103 and the P-type body region 102, and the top of the contact hole 107 is connected to a source electrode composed of a front metal layer 108.
The parasitic triode is composed of a source region 103, a P-type body region 102 and an N-type drift region and a drain region, wherein the P-type body region 102 is used as a base region of the parasitic triode. To reduce Rb, a P-type implant region 102a is added, which P-type implant region 102 can increase the doping concentration of the base region to reduce Rb. The P-type implantation region 102 is doped P +, and the depth of the P-type implantation region 102 is required not to affect the threshold voltage, i.e., Vth, of the device, and the Rb value is reduced as much as possible without affecting Vth. This method requires an additional Mask (Mask) to be added.
A second type of trench gate semiconductor device is available:
another way to reduce Rb is to reduce the effective length of Rb; this can be achieved by reducing the distance from the contact hole to the Gate, i.e., the trench Gate (CT to Gate), or can be achieved alone or in combination with a CT silicon recess (silicon access).
The bottleneck of reducing the distance from the contact hole to the trench gate is the photolithography alignment process, and if the distance is very small, the small Overlay (OVL) deviation has a great influence on the in-plane uniformity of the device, which is not favorable for enhancing the durability of the device. Fig. 2 is a schematic structural diagram of a second trench gate semiconductor device of the prior art; also taking an N-type MOSFET as an example, fig. 2 includes a plurality of device unit structures, and a second conventional trench gate semiconductor device includes:
the N-type epitaxial layer 201 and the P-type body region 202 formed on the surface of the N-type epitaxial layer 201, and the N + -doped source region 203 is formed on the surface of the P-type body region 202. The trench gate includes a gate dielectric layer such as a gate oxide layer 204 and a filled polysilicon gate 205 formed in a gate trench.
A contact hole 208 is also formed through the interlayer film 206 on top of the source region 203, and the top of the contact hole 208 is connected to a source electrode composed of a front metal layer 209. The bottom of the contact hole 208 at the top of the source region 203 is also formed with a body pull-out region 207 composed of a P + region, the body pull-out region 207 enabling the connection of the P-type body region 202 and the contact hole 208 through the source region 203.
The epitaxial layer 201 at the bottom of the P-type body region 202 serves as a drift region, and a drain region 210 composed of an N + region is formed at the bottom of the drift region.
As shown in FIG. 2, the distance CT to Gate is d2, and reducing d2 reduces Rb.
However, when Rb is lowered by reducing d2 in the structure shown in fig. 2, a new problem arises: that is, as the step (pitch) of the trench Gate semiconductor device is continuously reduced, the step is the sum of the width d1 and the pitch of the Gate trench in fig. 2, and as the step is continuously reduced, the design rule (design rule) from the contact hole to the trench Gate is increasingly tightened, for example, when the pitch is reduced to be within 1 μm, the Critical Dimension (CD) of the Gate (Gate), i.e., d1 in fig. 2, the CT CD, i.e., d3 in fig. 2, and the CT to Gate distance in the design rule have great challenges, e.g., 0.3 μm, and 0.3 μm are respectively used to meet the requirement of 0.9 μm, and the manufacturing difficulty is great.
Therefore, when Rb is reduced by the method of reducing d2 in the structure shown in fig. 2, there is a Trade-off (Trade off) between the three dimensions of Gate CD, CT CD and CT to Gate in the device structure shown in fig. 2, and as Pitch continues to shrink, the challenges of the lithography process, the etching process and the filling process become greater. Thereby limiting further process development as well.
A third type of trench-gate semiconductor device is available:
there is currently a solution to alleviate the tension of design Rule described above, i.e. using the CT self-alignment process. Fig. 3 is a schematic structural diagram of a third trench gate semiconductor device in the prior art;
also taking an N-type MOSFET as an example, fig. 2 includes a plurality of device unit structures, and a second conventional trench gate semiconductor device includes:
the epitaxial layer 301 of N type and the P type body region 302 that forms in the epitaxial layer 301 surface of N type, there is source region 303 of N + doping at the surface of P type body region 302. The trench gate includes a gate dielectric layer such as a gate oxide 304 and a filled polysilicon gate 305 formed in a gate trench.
The top of the polysilicon gate 305 is also etched back so that the top surface of the polysilicon gate 305 is below the top surface of the N-type epitaxial layer 301.
The opening of the contact hole 308 is etched by using a dielectric layer 306 such as an oxide layer filled on the top of the polysilicon gate 305 as a self-aligned condition and etching the material of the N-type epitaxial layer 301, usually the material of the N-type epitaxial layer 301 is silicon, and the etched opening is a silicon groove. After the opening of the contact hole 308 is formed, a body pull-out region 307 composed of a P + region is formed at the bottom of the opening, and then the opening is filled with a metal to form the contact hole 308. The top of the contact hole 308 is connected to a source electrode composed of a front metal layer 309. Body pull region 307 connects P-type body region 302 to contact hole 308 through source region 303.
The epitaxial layer 301 at the bottom of the P-type body region 302 serves as a drift region, and a drain region 310 composed of an N + region is also formed at the bottom of the drift region.
In the structure shown in fig. 3, since the opening etching of the contact hole 308 is performed in the forming process, the etching includes the inclined etching of the material of the N-type epitaxial layer 301, i.e., the silicon recess etching, the control of the etching angle is critical, and if the control of the etching angle is not good, the contact hole 308 is too close to the trench gate and the channel, which affects the Vth and reliability of the device.
A method for improving the process controllability of the silicon recess etching of the contact hole 308 is to increase the width of the dielectric layer 306 by a thermal oxidation process when the dielectric layer 306 composed of an oxide layer is formed.
Disclosure of Invention
The invention aims to provide a trench gate semiconductor device, which can reduce the step of the device, reduce the base resistance of a parasitic triode and improve the process window and the producibility at the same time. Therefore, the invention also provides a manufacturing method of the trench gate semiconductor device.
In order to solve the above technical problem, the trench gate semiconductor device provided by the present invention includes:
a body region of a second conductivity type is formed in a first conductivity type doped epitaxial layer, the body region extending downwardly from a top surface of the first epitaxial layer.
The trench gate comprises a gate trench, a gate dielectric layer and a gate conductive material layer.
The gate trench penetrates through the body region, and the top surface of the gate trench is flush with the top surface of the first epitaxial layer. The surface of the body region laterally covered by the layer of gate conductive material is used to form a channel.
The gate dielectric layer is formed on the inner side surface of the gate trench, the gate conductive material layer completely fills the bottom region of the gate trench, the top surface of the gate conductive material layer is lower than the top surface of the first epitaxial layer, and the top region of the gate trench is a region from the top surface of the gate conductive material layer to the top surface of the first epitaxial layer.
A source region of heavily doped first conductivity type is formed in the first epitaxial layer laterally of a top region of the gate trench, the source region being formed by angled ion implantation self-aligned.
A top dielectric layer is formed on the surface of the gate conductive material layer in the top region of the gate trench, and the top surface of the top dielectric layer is lower than the top surface of the first epitaxial layer.
First grooves are formed at the top corners of the two sides of the top dielectric layer, and the first grooves remove the top area of the source region so as to enable the top surface of the source region to be lowered between the bottom surface and the top surface of the top dielectric layer.
The bottom of the source contact hole is formed in the first groove in a self-alignment mode and on the surface of the top medium layer between the first grooves, and the top surface of the source region in the first groove is in contact with the side face of the source contact hole to achieve the leading-out of the source region.
The isolation structure between the source contact hole and the grid conductive material layer is a longitudinal isolation structure consisting of the top dielectric layer, and the isolation distance between the source contact hole and the grid conductive material layer is determined by the thickness of the top dielectric layer.
In a further improvement, a body lead-out region heavily doped with the second conductivity type is formed in the body region located above the bottom surface of the first groove, and a body contact hole is formed at the top of the body lead-out region.
In a further refinement, the body contact hole passes through an interlayer film, and the top of the source contact hole and the body contact hole merge together and are connected to a source electrode composed of a front metal layer.
The further improvement is that the trench gate semiconductor device is a trench gate MOSFET, and a drain region composed of a first conductive type heavily doped region is formed at the bottom of the first epitaxial layer.
The further improvement is that the trench gate semiconductor device is a trench gate IGBT, and a collector region composed of a second conductive type heavily doped region is formed at the bottom of the first epitaxial layer.
In a further improvement, a super junction structure is formed in the first epitaxial layer, and the super junction structure is formed by alternately arranging first conductivity type columns and second conductivity type columns.
In a further improvement, the first recess is formed by isotropic etching self-alignment of the first epitaxial layer.
In a further improvement, the gate dielectric layer comprises a gate oxide layer; the gate conductive material layer includes a polysilicon gate.
In order to solve the above technical problem, the method for manufacturing a trench gate semiconductor device provided by the present invention comprises the following steps:
step one, forming a body region doped with a second conduction type in a first epitaxial layer doped with a first conduction type, wherein the body region extends downwards from the top surface of the first epitaxial layer.
And secondly, forming a hard mask layer on the surface of the first epitaxial layer, and selectively etching the hard mask layer to open a forming area of the grid groove.
And step three, etching the first epitaxial layer by taking the hard mask layer as a mask to form the gate groove, wherein the gate groove penetrates through the body region, and the top surface of the gate groove is flush with the top surface of the first epitaxial layer.
And fourthly, forming a gate dielectric layer on the inner side surface of the gate groove.
And fifthly, filling a grid conductive material layer in the grid groove, etching the grid conductive material layer back to a position lower than the top surface of the grid groove and completely filling the bottom area of the grid groove, wherein the top area of the grid groove is an area between the top surface of the grid conductive material layer and the top surface of the first epitaxial layer.
Sixthly, implanting first conductive type heavily doped angled ions into the first epitaxial layer on the side face of the top area of the grid groove to form a source area in a self-alignment manner; and removing the hard mask layer.
And seventhly, forming a top dielectric layer to completely fill the gate groove above the surface of the gate conductive material layer.
And step eight, forming an interlayer film, and etching to form an opening of the contact hole.
The contact hole comprises the source contact hole, the source contact hole is positioned at the top of the grid groove, and the etching process of the opening of the source contact hole further comprises the following steps after the interlayer film is etched:
and removing part of the thickness of the top dielectric layer.
And carrying out isotropic etching on the first epitaxial layer to form first grooves at the top corners of the two sides of the top dielectric layer in a self-alignment manner, and removing the top area of the source region by the first grooves to enable the top surface of the source region to be lowered between the bottom surface and the top surface of the top dielectric layer.
And step nine, filling metal in the opening of the contact hole to form the contact hole.
The bottom of the source contact hole is formed in the first groove in a self-alignment mode and on the surface of the top medium layer between the first grooves, and the top surface of the source region in the first groove is in contact with the side face of the source contact hole to achieve the leading-out of the source region.
The isolation structure between the source contact hole and the grid conductive material layer is a longitudinal isolation structure consisting of the top dielectric layer, and the isolation distance between the source contact hole and the grid conductive material layer is determined by the thickness of the top dielectric layer.
In a further improvement, in the eighth step, the contact hole further includes a body contact hole, and an opening of the body contact hole penetrates through the interlayer film.
After the etching of the opening of the contact hole penetrating through the interlayer film is completed and before the partial thickness of the top dielectric layer of the opening of the source contact hole is removed, the method also comprises the step of carrying out second conductive type heavily doped ion implantation to form a second conductive type heavily doped body leading-out region on the body region exposed by the opening of the body contact hole and the surface of the source region, wherein the junction depth of the body leading-out region is smaller than that of the source region.
After forming the first recess, the body lead-out region is located in the body region above a bottom surface of the first recess; the body contact hole contacts the body pull-out region.
In a further refinement, the top of the source contact hole and the body contact hole merge together and are connected to a source electrode comprised of a front side metal layer.
The further improvement is that the trench gate semiconductor device is a trench gate MOSFET, and the step of forming a drain region composed of a first conductive type heavily doped region at the bottom of the first epitaxial layer by performing a back surface process is further included after the front surface process is completed.
The further improvement is that the trench gate semiconductor device is a trench gate IGBT, and the step of forming a collector region composed of a second conductive type heavily doped region at the bottom of the first epitaxial layer by performing a back surface process is also included after the front surface process is completed.
In a further improvement, a super junction structure is formed in the first epitaxial layer, and the super junction structure is formed by alternately arranging first conductivity type columns and second conductivity type columns.
In a further refinement, the first conductivity type pillars are comprised of the first epitaxial layer between the second conductivity type pillars.
The super junction structure is formed by multiple times of epitaxial growth and ion implantation, and the second conduction type column is composed of a second conduction type ion implantation area.
The super-junction structure is formed by adopting a trench filling process, and the second conductive type column is composed of a second epitaxial layer which is filled in the super-junction trench and is doped with a second conductive type.
The structure of the trench gate semiconductor device is specially designed, a source contact hole in contact with a source region is not arranged on the top surface of a source region any more, but the top surface of a gate conductive material layer is arranged to be lower than the top surface of a gate groove in a combined manner, so that the source region can be formed in a first epitaxial layer on the side surface of the top region of the gate groove in a self-aligning manner from the top region of the gate groove, the bottom of the source contact hole is formed in the gate groove on the top of the gate conductive material layer in a self-aligning manner, and the source contact hole and the gate conductive material layer are longitudinally isolated through a top dielectric layer; meanwhile, the first grooves are formed at the top corners of the two sides of the top dielectric layer, and the top surface of the source region is reduced to be between the bottom surface and the top surface of the top dielectric layer through the first grooves, so that the source contact hole is in contact with the top surface of the source region in the first grooves to lead out the source region; moreover, as the source contact hole and the grid conductive material layer have no transverse spacing, the limitation of the transverse spacing between the source contact hole and the grid conductive material layer on the stepping of the device can be eliminated, so that the stepping of the device can be reduced to the maximum extent; meanwhile, as the source contact hole and the grid conductive material layer are not transversely spaced, an isolation structure is not required to be arranged between the source contact hole and the grid conductive material layer in the transverse direction, so that the alignment requirement is not required, and the source contact hole and the grid conductive material layer are only longitudinally isolated and the longitudinal isolation can be realized by adjusting the top dielectric layer, so that the process difficulty can be greatly reduced, and the process window and the producibility can be improved.
In addition, the contact part of the source contact hole and the source region can be positioned below the top surface of the top dielectric layer through the arrangement of the first groove, so that the size of the source region can be further reduced, the space between the source contact hole and the channel can be further reduced, the path of the base resistance of the parasitic triode can be further reduced, and the base resistance can be further reduced; in addition, a fin body structure is formed in the body region positioned on the bottom surface of the first groove, and the body leading-out region is formed in the fin body, so that the doping concentration of the second conduction type on a path from the body contact hole to the channel can be increased, the resistance of the base region can be further reduced, and the ohmic contact performance between the body contact hole and the body leading-out region can be further improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a schematic structural diagram of a prior art first trench gate semiconductor device;
fig. 2 is a schematic structural diagram of a second trench gate semiconductor device of the prior art;
fig. 3 is a schematic structural diagram of a third trench gate semiconductor device of the prior art;
fig. 4 is a schematic structural view of a trench gate semiconductor device according to a first embodiment of the present invention;
fig. 5 is a schematic structural view of a trench-gate semiconductor device according to a second embodiment of the present invention;
fig. 6A to 6F are schematic structural views of steps of a method for manufacturing a trench-gate semiconductor device according to a first embodiment of the present invention.
Detailed Description
The trench gate semiconductor device of the first embodiment of the present invention:
fig. 4 is a schematic structural diagram of a trench gate semiconductor device according to a first embodiment of the present invention; the trench gate semiconductor device of the embodiment of the invention comprises:
a body region 2 doped with a second conductivity type is formed in the first epitaxial layer 1 doped with the first conductivity type, the body region 2 extending downward from the top surface of the first epitaxial layer 1.
The trench gate comprises a gate trench 4, a gate dielectric layer 5 and a gate conductive material layer 6. In the first embodiment of the present invention, the gate dielectric layer 5 includes a gate oxide layer; the layer of gate conductive material 6 comprises a polysilicon gate.
The gate trench 4 penetrates through the body region 2, and the top surface of the gate trench 4 is flush with the top surface of the first epitaxial layer 1. The surface of the body region 2 laterally covered by the layer 6 of gate conductive material is used to form a channel.
The gate dielectric layer 5 is formed on the inner side surface of the gate trench 4, the gate conductive material layer 6 completely fills the bottom region of the gate trench 4, the top surface of the gate conductive material layer 6 is lower than the top surface of the first epitaxial layer 1, and the top region of the gate trench 4 is a region between the top surface of the gate conductive material layer 6 and the top surface of the first epitaxial layer 1.
A source region 3 of heavily doped first conductivity type is formed in the first epitaxial layer 1 at the side of the top region of the gate trench 4, the source region 3 being formed by angled ion implantation self-aligned.
A top dielectric layer 7 is formed on the surface of the gate conductive material layer 6 in the top region of the gate trench 4, and the top surface of the top dielectric layer 7 is lower than the top surface of the first epitaxial layer 1.
The bottom of the source contact hole 9a is formed in the first groove 11 in a self-alignment mode and on the surface of the top dielectric layer 7 between the first grooves 11, and the source region 3 is led out by contacting the top surface of the source region 3 in the first groove 11 with the side face of the source contact hole 9 a.
The isolation structure between the source contact hole 9a and the gate conductive material layer 6 is a longitudinal isolation structure consisting of the top dielectric layer 7, and the isolation distance between the source contact hole 9a and the gate conductive material layer 6 is determined by the thickness of the top dielectric layer 7.
A body escape region 8 heavily doped with the second conductivity type is formed in the body region 2 over the bottom surface of the first groove 11, and a body contact hole 9b is formed at the top of the body escape region 8.
The body contact hole 9b passes through an interlayer film (not shown), and the top of the source contact hole 9a and the body contact hole 9b are merged together and connected to a source electrode composed of a front metal layer (not shown).
In the first embodiment of the present invention, the trench gate semiconductor device is a trench gate MOSFET, and a drain region 10 formed of a heavily doped region of the first conductivity type is formed at the bottom of the first epitaxial layer 1. In other embodiments can also be: the trench gate semiconductor device is a trench gate IGBT, and a collector region composed of a second conductive type heavily doped region is formed at the bottom of the first epitaxial layer 1.
In the first embodiment of the present invention, the trench gate semiconductor device is an N-type device, the first conductivity type is an N-type device, and the second conductivity type is a P-type device. In other embodiments can also be: the trench gate semiconductor device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
The first embodiment of the present invention makes a special design for the structure of the trench gate semiconductor device, the source contact hole 9a contacting the source region 3 is no longer disposed on the top surface of the source region 3, but the top surface of the gate conductive material layer 6 is set lower than the top surface of the gate trench 4, so that the source region 3 can be formed in the first epitaxial layer 1 on the side of the top region of the gate trench 4 by self-alignment from the top region of the gate trench 4, the bottom of the source contact hole 9a is formed in the gate trench 4 on the top of the gate conductive material layer 6 by self-alignment, and the source contact hole 9a and the gate conductive material layer 6 are longitudinally isolated by the top dielectric layer 7; meanwhile, the first grooves 11 are formed at the top corners of the two sides of the top dielectric layer 7, the top surface of the source region 3 is lowered to a position between the bottom surface and the top surface of the top dielectric layer 7 through the first grooves 11, and therefore the source contact hole 9a is in contact with the top surface of the source region 3 in the first groove 11 to lead out the source region 3, so that the source contact hole 9a is located at the top of the grid conductive material layer 6 in the first embodiment of the invention, the influence of the transverse distance between the source contact hole 9a and the grid conductive material layer 6 on the base resistance of the parasitic triode can be eliminated, and the base resistance of the parasitic triode can be reduced to the maximum extent; moreover, as the source contact hole 9a and the grid conductive material layer 6 have no transverse spacing, the limitation of the transverse spacing between the source contact hole 9a and the grid conductive material layer 6 on the stepping of the device can be eliminated, so that the stepping of the device can be reduced to the maximum extent; meanwhile, as the source contact hole 9a and the grid conductive material layer 6 are not transversely spaced, an isolation structure is not required to be arranged between the source contact hole 9a and the grid conductive material layer 6 in the transverse direction, so that the alignment requirement is not required, and the source contact hole 9a and the grid conductive material layer 6 are only longitudinally isolated and the longitudinal isolation can be realized by adjusting the top dielectric layer 7, so that the process difficulty can be greatly reduced, and the process window and the producibility can be improved.
In addition, the contact part of the source contact hole 9a and the source region 3 is positioned below the top surface of the top dielectric layer 7 through the arrangement of the first groove 11, so that the size of the source region 3 can be further reduced, the space between the source contact hole 9a and a channel can be further reduced, the path of the base resistance of the parasitic triode can be further reduced, and the base resistance can be further reduced; in addition, the body region 2 located on the bottom surface of the first groove 11 forms a fin body structure, and the body lead-out region 8 is formed in the fin body, so that the doping concentration of the second conduction type on a path from the body contact hole 9b to a channel can be increased, the base resistance can be further reduced, and the ohmic contact performance between the body contact hole 9b and the body lead-out region 8 can be increased.
The trench gate semiconductor device according to the second embodiment of the present invention:
fig. 5 is a schematic structural diagram of a trench gate semiconductor device according to a second embodiment of the present invention; the difference between the trench gate semiconductor device according to the second embodiment of the present invention and the trench gate semiconductor device according to the first embodiment of the present invention is:
a super junction structure is formed in the first epitaxial layer 1, and the super junction structure is formed by alternately arranging first conductive type columns and second conductive type columns 12.
The first conductivity type pillars are composed of the first epitaxial layer 1 between the second conductivity type pillars 12; the second conductive type column 12 is composed of a second conductive type ion implantation region or a second conductive type doped epitaxial layer filled in the super junction trench.
The manufacturing method of the trench gate semiconductor device according to the first embodiment of the present invention:
fig. 6A to 6F are schematic structural views of steps of a method for manufacturing a trench-gate semiconductor device according to a first embodiment of the present invention; the method for manufacturing the trench gate semiconductor device according to the first embodiment of the present invention includes the steps of:
step one, as shown in fig. 6A, a body region 2 doped with a second conductivity type is formed in a first epitaxial layer 1 doped with a first conductivity type, and the body region 2 extends downward from the top surface of the first epitaxial layer 1.
The body region 2 is formed by an ion implantation plus drive-trap process.
Step two, as shown in fig. 6A, a hard mask layer 401 is formed on the surface of the first epitaxial layer 1, and the hard mask layer 401 is selectively etched to open the formation region of the gate trench 4.
The hard mask layer 401 is typically a stack of oxide and nitride layers.
Step three, as shown in fig. 6B, the first epitaxial layer 1 is etched by using the hard mask layer 401 as a mask to form the gate trench 4, the gate trench 4 penetrates through the body region 2, and the top surface of the gate trench 4 is flush with the top surface of the first epitaxial layer 1.
Step four, as shown in fig. 6B, a gate dielectric layer 5 is formed on the inner side surface of the gate trench 4.
In the method of the first embodiment of the present invention, the gate dielectric layer 5 is a gate oxide layer and is formed by a thermal oxidation process.
Step five, as shown in fig. 6B, filling a gate conductive material layer 6 in the gate trench 4, etching back the gate conductive material layer 6 to a position lower than the top surface of the gate trench 4 and completely filling the bottom region of the gate trench 4, where the top region of the gate trench 4 is a region between the top surface of the gate conductive material layer 6 and the top surface of the first epitaxial layer 1.
In the method according to the first embodiment of the present invention, the gate conductive material layer 6 is a polysilicon gate, and the forming process includes: and depositing polysilicon, performing chemical mechanical polishing on the polysilicon to remove the polysilicon outside the gate trench 4, and performing polysilicon back etching to enable the gate conductive material layer 6 to be back etched to be lower than the top surface of the gate trench 4.
Sixthly, as shown in fig. 6C, performing first conductivity type heavily doped angled ion implantation to form a source region 3 in a self-aligned manner in the first epitaxial layer 1 on the side surface of the top region of the gate trench 4.
Since the gate dielectric layer 5 is formed on the side surface of the top region of the gate trench 4, a process of thinning the gate dielectric layer 5 is further included before the angled ion implantation of the source 3.
The hard mask layer 401 is then removed.
Step seven, as shown in fig. 6D, a top dielectric layer 7 is formed to fill the gate trench 4 above the surface of the gate conductive material layer 6.
The top dielectric layer 7 is formed by deposition and chemical mechanical polishing processes, and the chemical mechanical polishing processes are stopped on the surface of the first epitaxial layer 1. Usually, the top dielectric layer 7 is an oxide layer, the material of the first epitaxial layer 1 is silicon, and the chemical mechanical polishing directly stops on the silicon surface.
And step eight, as shown in fig. 4, forming an interlayer film, and etching to form an opening of the contact hole.
The contact holes include the source contact hole 9a, the source contact hole 9a is located at the top of the gate trench 4, and the etching process of the opening of the source contact hole 9a further includes, after etching the interlayer film:
as shown in fig. 6E, a portion of the thickness of the top dielectric layer 7 is removed.
As shown in fig. 6F, the first epitaxial layer 1 is isotropically etched to form a first groove 11 at the top corners of the top dielectric layer 7 in a self-aligned manner, and the first groove 11 removes the top region of the source region 3 so as to lower the top surface of the source region 3 to a position between the bottom surface and the top surface of the top dielectric layer 7. As can be seen from fig. 6F, since the top surface and the side surface of the first epitaxial layer 1 at the top corner of the top dielectric layer 7 are simultaneously exposed, the etching rate at the top corner of the top dielectric layer 7 is faster, and finally the first groove 11 can be formed; after the first recess 11 is formed, the top surface of the first epitaxial layer 1 is also lowered.
The contact hole further includes a body contact hole 9b, and an opening of the body contact hole 9b passes through the interlayer film.
After the etching of the opening of the contact hole penetrating through the interlayer film is completed and before the partial thickness removal of the top dielectric layer 7 of the opening of the source contact hole 9a is performed, as shown in fig. 6E, the method further comprises performing second-conductivity-type heavily-doped ion implantation to form a second-conductivity-type heavily-doped body extraction region 8 on the surfaces of the body region 2 exposed by the opening of the body contact hole 9b and the source region 3, wherein the junction depth of the body extraction region 8 is smaller than that of the source region 3.
As shown in fig. 6F, after the first groove 11 is formed, the body lead-out region 8 is located in the body region 2 above the bottom surface of the first groove 11.
In the method of the first embodiment of the present invention, the top of the source contact hole 9a and the body contact hole 9b are merged together, that is, the opening of the source contact hole 9a and the opening of the body contact hole 9b passing through the portion of the interlayer film are an integrated structure.
Step nine, as shown in fig. 4, filling metal in the opening of the contact hole to form the contact hole.
The bottom of the source contact hole 9a is formed in the first groove 11 in a self-alignment mode and on the surface of the top dielectric layer 7 between the first grooves 11, and the top surface of the source region 3 in the first groove 11 is in contact with the side face of the source contact hole 9a to enable the source region 3 to be led out.
The body contact hole 9b is in contact with the body lead-out region 8. The top of the source contact hole 9a and the body contact hole 9b are merged together and connected to a source electrode composed of a front metal layer.
The isolation structure between the source contact hole 9a and the gate conductive material layer 6 is a longitudinal isolation structure consisting of the top dielectric layer 7, and the isolation distance between the source contact hole 9a and the gate conductive material layer 6 is determined by the thickness of the top dielectric layer 7.
The contact surface of the source contact hole 9a and the source region 3 is lower than the top surface of the top dielectric layer 7, so that the distance from the source contact hole 9a to a channel can be reduced, namely the path length of a base resistance Rb of a parasitic triode can be reduced, and the base resistance can be further reduced on the basis of longitudinal isolation.
Meanwhile, as the body region 2 between the first grooves 11 forms an upward protruding Fin body (Fin) structure and the body pull-out region 8 is positioned in the Fin body, the influence of the doping of the body pull-out region 8 on the threshold voltage of the channel can be reduced, so that the doping concentration of the body pull-out region 8 can be increased, and the base resistance can be further reduced.
In the method according to the first embodiment of the present invention, the trench gate semiconductor device is a trench gate MOSFET, and the method further includes a step of performing a back process to form a drain region 10 composed of a first conductivity type heavily doped region at the bottom of the first epitaxial layer 1 after the front process is completed. Generally, the first epitaxial layer 1 is formed on the surface of a semiconductor substrate, and the drain region 10 is formed by directly forming the semiconductor substrate heavily doped with the first conductivity type after back thinning the semiconductor substrate or by performing back ion implantation heavily doped with the first conductivity type after back thinning the semiconductor substrate.
In other embodiments the method can also be: the trench gate semiconductor device is a trench gate IGBT, and the method further comprises the step of forming a collector region composed of a second conduction type heavily doped region at the bottom of the first epitaxial layer 1 by performing a back surface process after the front surface process is completed.
In the method according to the first embodiment of the present invention, the trench gate semiconductor device is an N-type device, the first conductivity type is an N-type device, and the second conductivity type is a P-type device. In other embodiments the method can also be: the trench gate semiconductor device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
A method for manufacturing a trench gate semiconductor device according to a second embodiment of the present invention:
the manufacturing method of the trench gate semiconductor device according to the second embodiment of the present invention is different from the manufacturing method of the trench gate semiconductor device according to the first embodiment of the present invention in that:
in the first step, a super junction structure is formed in the first epitaxial layer 1, and the super junction structure is formed by alternately arranging first conductive type columns and second conductive type columns 12.
The first conductive type pillars are composed of the first epitaxial layer 1 between the second conductive type pillars 12.
The super junction structure is formed by multiple times of epitaxial growth and ion implantation, and the second conductive type column 12 is composed of a second conductive type ion implantation region.
The super junction structure is formed by a trench filling process, and the second conductive type column 12 is composed of a second epitaxial layer doped with a second conductive type and filled in the super junction trench.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A trench-gate semiconductor device, comprising:
forming a body region doped with a second conductivity type in a first epitaxial layer doped with a first conductivity type, the body region extending downward from a top surface of the first epitaxial layer;
the trench gate comprises a gate trench, a gate dielectric layer and a gate conductive material layer;
the gate trench penetrates through the body region, and the top surface of the gate trench is flush with the top surface of the first epitaxial layer;
the grid dielectric layer is formed on the inner side surface of the grid groove, the grid conductive material layer completely fills the bottom area of the grid groove, the top surface of the grid conductive material layer is lower than the top surface of the first epitaxial layer, and the top area of the grid groove is an area between the top surface of the grid conductive material layer and the top surface of the first epitaxial layer;
a source region heavily doped with a first conductivity type is formed in the first epitaxial layer at the side of the top region of the gate trench, the source region being formed by angled ion implantation self-alignment;
a top dielectric layer is formed on the surface of the gate conductive material layer in the top area of the gate groove, and the top surface of the top dielectric layer is lower than the top surface of the first epitaxial layer;
first grooves are formed in the top corners of the two sides of the top dielectric layer, and the first grooves remove the top area of the source region so that the top surface of the source region is lowered between the bottom surface and the top surface of the top dielectric layer;
the bottom of the source contact hole is formed in the first groove in a self-alignment mode and on the surface of the top medium layer between the first grooves, and the top surface of the source region in the first groove is in contact with the side face of the source contact hole to achieve leading-out of the source region;
the isolation structure between the source contact hole and the grid conductive material layer is a longitudinal isolation structure consisting of the top dielectric layer, and the isolation distance between the source contact hole and the grid conductive material layer is determined by the thickness of the top dielectric layer.
2. The trench-gate semiconductor device of claim 1 wherein: a body lead-out region heavily doped with the second conductivity type is formed in the body region over the bottom surface of the first groove, and a body contact hole is formed at the top of the body lead-out region.
3. The trench-gate semiconductor device of claim 2 wherein: the body contact hole penetrates through the interlayer film, and the top of the source contact hole and the body contact hole are merged together and connected to a source electrode composed of a front metal layer.
4. The trench-gate semiconductor device of claim 1 wherein: the trench gate semiconductor device is a trench gate MOSFET, and a drain region composed of a first conductive type heavily doped region is formed at the bottom of the first epitaxial layer.
5. The trench-gate semiconductor device of claim 1 wherein: the trench gate semiconductor device is a trench gate IGBT, and a collector region composed of a second conductive type heavily doped region is formed at the bottom of the first epitaxial layer.
6. The trench-gate semiconductor device of claim 1 wherein: a super-junction structure is formed in the first epitaxial layer and is formed by alternately arranging first conductive type columns and second conductive type columns.
7. The trench-gate semiconductor device of claim 1 wherein: the first groove is formed by isotropic etching self-alignment of the first epitaxial layer.
8. The trench-gate semiconductor device of claim 1 wherein: the gate dielectric layer comprises a gate oxide layer; the gate conductive material layer includes a polysilicon gate.
9. A method for manufacturing a trench gate semiconductor device, comprising the steps of:
step one, forming a body region doped with a second conduction type in a first epitaxial layer doped with a first conduction type, wherein the body region extends downwards from the top surface of the first epitaxial layer;
secondly, forming a hard mask layer on the surface of the first epitaxial layer, and selectively etching the hard mask layer to open a forming area of the grid groove;
etching the first epitaxial layer by taking the hard mask layer as a mask to form the gate trench, wherein the gate trench penetrates through the body region, and the top surface of the gate trench is flush with the top surface of the first epitaxial layer;
forming a gate dielectric layer on the inner side surface of the gate groove;
fifthly, filling a grid conductive material layer in the grid groove, etching the grid conductive material layer back to a position lower than the top surface of the grid groove and completely filling the bottom area of the grid groove, wherein the top area of the grid groove is an area between the top surface of the grid conductive material layer and the top surface of the first epitaxial layer;
sixthly, implanting first conductive type heavily doped angled ions into the first epitaxial layer on the side face of the top area of the grid groove to form a source area in a self-alignment manner; then removing the hard mask layer;
step seven, forming a top dielectric layer to completely fill the grid groove on the surface of the grid conductive material layer;
step eight, forming an interlayer film, and etching to form an opening of the contact hole;
the contact hole comprises the source contact hole, the source contact hole is positioned at the top of the grid groove, and the etching process of the opening of the source contact hole further comprises the following steps after the interlayer film is etched:
removing part of the thickness of the top dielectric layer;
isotropic etching is carried out on the first epitaxial layer to form first grooves which are formed at the top corners of the two sides of the top dielectric layer in a self-aligning mode, and the first grooves remove the top area of the source region to enable the top surface of the source region to be lowered between the bottom surface and the top surface of the top dielectric layer;
filling metal into the opening of the contact hole to form the contact hole;
the bottom of the source contact hole is formed in the first groove in a self-alignment mode and on the surface of the top medium layer between the first grooves, and the top surface of the source region in the first groove is in contact with the side face of the source contact hole to achieve leading-out of the source region;
the isolation structure between the source contact hole and the grid conductive material layer is a longitudinal isolation structure consisting of the top dielectric layer, and the isolation distance between the source contact hole and the grid conductive material layer is determined by the thickness of the top dielectric layer.
10. The method of manufacturing a trench-gate semiconductor device according to claim 9, wherein: in the eighth step, the contact hole further comprises a body contact hole, and an opening of the body contact hole penetrates through the interlayer film;
after the etching of the opening of the contact hole penetrating through the interlayer film is completed and before the partial thickness of the top dielectric layer of the opening of the source contact hole is removed, carrying out second-conductivity-type heavily-doped ion implantation to form a second-conductivity-type heavily-doped body leading-out region on the body region exposed by the opening of the body contact hole and the surface of the source region, wherein the junction depth of the body leading-out region is smaller than that of the source region;
after forming the first recess, the body lead-out region is located in the body region above a bottom surface of the first recess; the body contact hole contacts the body pull-out region.
11. The method of manufacturing a trench-gate semiconductor device according to claim 10, wherein: the top of the source contact hole and the body contact hole merge together and are connected to a source electrode composed of a front metal layer.
12. The method of manufacturing a trench-gate semiconductor device according to claim 9, wherein: the trench gate semiconductor device is a trench gate MOSFET, and the method further comprises the step of forming a drain region consisting of a first conductive type heavily doped region at the bottom of the first epitaxial layer by performing a back surface process after the front surface process is finished.
13. The method of manufacturing a trench-gate semiconductor device according to claim 9, wherein: the trench gate semiconductor device is a trench gate IGBT, and the method further comprises the step of forming a collector region composed of a second conduction type heavily doped region at the bottom of the first epitaxial layer by performing a back surface process after the front surface process is completed.
14. The method of manufacturing a trench-gate semiconductor device according to claim 9, wherein: a super-junction structure is formed in the first epitaxial layer and is formed by alternately arranging first conductive type columns and second conductive type columns.
15. The method of manufacturing a trench-gate semiconductor device according to claim 14, wherein: the first conductivity type pillars are composed of the first epitaxial layer between the second conductivity type pillars;
the super junction structure is formed by multiple times of epitaxial growth and ion implantation, and the second conductive type column is composed of a second conductive type ion implantation area;
the super-junction structure is formed by adopting a trench filling process, and the second conductive type column is composed of a second epitaxial layer which is filled in the super-junction trench and is doped with a second conductive type.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114242596A (en) * | 2022-02-28 | 2022-03-25 | 深圳市美浦森半导体有限公司 | MOSFET device and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100176446A1 (en) * | 2009-01-13 | 2010-07-15 | Force Mos Technology Co. Ltd. | MOSFET with source contact in trench and integrated schottky diode |
| CN102270662A (en) * | 2010-06-01 | 2011-12-07 | 万国半导体股份有限公司 | Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts |
| CN104103694A (en) * | 2014-07-25 | 2014-10-15 | 苏州东微半导体有限公司 | Trench type insulated gate field effect transistor and manufacture method thereof |
| CN107527944A (en) * | 2017-07-28 | 2017-12-29 | 上海华虹宏力半导体制造有限公司 | Groove power MOSFET and its manufacture method |
| US20200144366A1 (en) * | 2018-01-30 | 2020-05-07 | Magnachip Semiconductor, Ltd. | Power semiconductor device and method for manufacturing the same |
-
2021
- 2021-02-05 CN CN202110160130.1A patent/CN112701164A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100176446A1 (en) * | 2009-01-13 | 2010-07-15 | Force Mos Technology Co. Ltd. | MOSFET with source contact in trench and integrated schottky diode |
| CN102270662A (en) * | 2010-06-01 | 2011-12-07 | 万国半导体股份有限公司 | Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts |
| CN104103694A (en) * | 2014-07-25 | 2014-10-15 | 苏州东微半导体有限公司 | Trench type insulated gate field effect transistor and manufacture method thereof |
| CN107527944A (en) * | 2017-07-28 | 2017-12-29 | 上海华虹宏力半导体制造有限公司 | Groove power MOSFET and its manufacture method |
| US20200144366A1 (en) * | 2018-01-30 | 2020-05-07 | Magnachip Semiconductor, Ltd. | Power semiconductor device and method for manufacturing the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114242596A (en) * | 2022-02-28 | 2022-03-25 | 深圳市美浦森半导体有限公司 | MOSFET device and manufacturing method thereof |
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Application publication date: 20210423 |