CN114242596A - MOSFET device and manufacturing method thereof - Google Patents
MOSFET device and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
A MOSFET device and a manufacturing method thereof are provided, the manufacturing method comprises providing a substrate, the substrate comprises a drift region; forming a trench gate structure on the drift region; forming a base region and a source region on the drift region; forming side walls on two sides of the trench gate structures, and defining a region between the two side walls between the two trench gate structures as a first region; under the masking of the side wall, patterning is carried out on the source region and part of the base region to form a source contact hole, a source electrode is formed on the source contact hole, and the source contact hole penetrates through the source region and part of the base region; a first electrode and a second electrode are formed. Because the side walls are formed on the two sides of the trench gate structure, the side walls can be used as a protection structure in the etching process of the source contact hole, the self-alignment effect is realized, and the source electrode and the grid polycrystalline silicon can not be in short circuit. Meanwhile, the area of the source contact hole is smaller than the minimum value controlled by the alignment energy of the machine, and the size of the device is further reduced.
Description
Technical Field
The invention relates to the field of MOSFET devices, in particular to a MOSFET device and a manufacturing method thereof.
Background
The trench gate power transistor is generally called a UMOSFET, and in order to reduce the cost and maintain the chip performance, the conventional trench power transistor can only continuously reduce the size of the cell to reduce the chip area. Due to the limitation of the photolithography technique, the capability of the equipment in the factory is not obviously improved, so the process window is continuously reduced, and the defective products are increased.
For example, when the source electrode adopts a trench structure, due to the small size and the high difficulty in photolithography and etching alignment, the trench (or called a source contact hole) corresponding to the source electrode is shifted from the designed position, which causes the short circuit between the source electrode and the gate polysilicon, and thus the product is poor.
Disclosure of Invention
The invention mainly solves the technical problem that the source electrode and the grid polysilicon are in short circuit in the existing small-size trench gate power tube.
According to a first aspect, there is provided in an embodiment a method of manufacturing a MOSFET device, comprising:
providing a substrate, wherein the substrate comprises a drift region; the drift region is used as a depletion layer in the forward voltage withstanding process of the MOSFET device;
forming a trench gate structure on the drift region, wherein the trench gate structure comprises a gate and a gate dielectric layer wrapping the gate, and the top of the gate is higher than the top surface of the drift region; the bottom of the grid extends into the drift region;
forming a base region and a source region on the drift region, wherein the source region is positioned between the two trench gate structures, and the bottom of the gate is lower than the bottom surface of the base region;
forming side walls on two sides of the trench gate structure, wherein the side walls are positioned above the drift region and on two sides of the trench gate structure, and defining a region between the two side walls between the two trench gate structures as a first region;
under the masking of the side wall, patterning is carried out on the source region and part of the base region to form a source contact hole, a source electrode is formed on the source contact hole, and the source contact hole penetrates through the source region and part of the base region;
forming a first electrode and a second electrode, wherein the source electrode is electrically connected with the first electrode, the first electrode is respectively and electrically connected with the base region and the source region through the source electrode, and the drift region is electrically connected with the second electrode; wherein the base region has a first conductivity type; the source region and the drift region have a second conductivity type, the first conductivity type and the second conductivity type being different semiconductor conductivity types; a first PN junction is formed between the source region and the base region, and a second PN junction is formed between the drift region and the base region.
According to a second aspect, an embodiment provides a MOSFET device made by the method of manufacturing described in the first aspect.
According to a third aspect, an embodiment provides a MOSFET device comprising a first electrode, a second electrode, and a semiconductor unit located between the first electrode and the second electrode, the semiconductor unit comprising:
a base region having a first conductivity type;
the semiconductor device comprises a source region, a base region and a drain region, wherein the source region has a second conductive type, the first conductive type and the second conductive type belong to different semiconductor conductive types, a first PN junction is formed between the source region and the base region, and the base region and the source region are respectively and electrically connected with a first electrode through a source electrode;
the drift region is positioned below the base region, has a second conduction type and is used as a depletion layer when the MOSFET device is in a forward voltage withstanding process; a second PN junction is formed between the drift region and the base region, and the drift region is electrically connected with the second electrode;
the trench gate structure comprises a gate and a gate dielectric layer wrapping the gate, the bottom of the gate penetrates through the base region and extends to the drift region, and the top of the gate is higher than the top surface of the source region; the two trench gate structures are respectively positioned at two sides of the source region;
the side walls are positioned above the source region and on two sides of the trench gate structures, and a region between the two side walls between the two trench gate structures is defined as a first region;
the source electrode penetrates through the source region and part of the base region after passing through the first region, and the source electrode is electrically connected with the first electrode.
According to the MOSFET device and the manufacturing method thereof in the embodiment, the side walls are formed on the two sides of the trench gate structure and can be used as a protection structure in the etching process of the source contact hole, and meanwhile, the self-alignment effect is realized, so that the source contact hole is formed between the two trench gate structures, and the source electrode and the grid polysilicon are prevented from being short-circuited. Meanwhile, the area of the source contact hole is smaller than the minimum value of the alignment control of the machine, and the size of the MOSFET device is further reduced.
Drawings
Fig. 1 is a schematic structural diagram of a MOSFET device according to an embodiment;
fig. 2 is a flow chart of a method for manufacturing a MOSFET device according to an embodiment;
FIG. 3 is a process diagram of a method of fabricating a MOSFET device according to an embodiment;
fig. 4 is a process diagram (two) of a method for manufacturing a MOSFET device according to an embodiment;
fig. 5 is a process schematic diagram (three) of a method for manufacturing a MOSFET device according to an embodiment;
fig. 6A is a process schematic diagram (four) of a method for manufacturing a MOSFET device according to an embodiment;
fig. 6B is a process diagram (five) of a method for manufacturing a MOSFET device according to an embodiment;
fig. 7 is a process schematic diagram (six) of a method for manufacturing a MOSFET device according to an embodiment;
fig. 8 is a process diagram (seven) of a method for manufacturing a MOSFET device according to an embodiment;
fig. 9 is a process schematic view (eight) of a method for manufacturing a MOSFET device according to an embodiment;
fig. 10 is a process diagram (nine) of a method for manufacturing a MOSFET device according to an embodiment;
fig. 11 is a process schematic diagram (ten) of a method for manufacturing a MOSFET device according to an embodiment;
fig. 12 is a process schematic diagram (eleven) of a method of manufacturing a MOSFET device according to an embodiment;
fig. 13 is a process schematic view (twelve) of a method for manufacturing a MOSFET device according to an embodiment;
fig. 14 is a process schematic view (thirteen) of a method for manufacturing a MOSFET device according to an embodiment;
fig. 15 is a schematic process diagram (fourteen) illustrating a method for manufacturing a MOSFET device according to an embodiment;
fig. 16 is a process schematic view (fifteen) of a method for manufacturing a MOSFET device according to an embodiment;
fig. 17 is a schematic process diagram (sixteen) illustrating a method for manufacturing a MOSFET device according to an embodiment.
Reference numerals: 1-a second electrode; 10-a drift region; 101-a first trench; 102-a second trench; 11-base region; 111-a first doped region; 12-a source region; 2-a first electrode; 3-a trench gate structure; 30-a gate; 31-a gate dielectric layer; 32-a second dielectric layer; 33-a third dielectric layer; 34-a first dielectric layer; 341-hard mask layer; 35-a first window; 4-side wall; 41-a fourth dielectric layer; 42-a first region; 5-a fifth dielectric layer; 51-a second window; 6-source electrode; 61-source contact hole.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
In the present application, the first conductivity type and the second conductivity type belong to different semiconductor conductivity types, and the first conductivity type and the second conductivity type are P-type and N-type, and when the first conductivity type is N-type, the second conductivity type is P-type, and vice versa.
In the embodiment of the invention, the side wall is formed by utilizing the trench gate structure, and the self-alignment formation of the source contact hole is realized by utilizing the side wall, so that even if the size of the source contact hole is smaller than the minimum value controlled by the alignment energy of a production machine, the source contact hole can be ensured not to be in short circuit with the polysilicon of the grid, and the production yield of the device is improved.
The first embodiment is as follows:
referring to fig. 1, the present embodiment provides a MOSFET device, specifically a trench gate power semiconductor device, which includes a first electrode 2, a second electrode 1, and a semiconductor unit located between the first electrode 2 and the second electrode 1, where the semiconductor unit includes a base region 11, a source region 12, a drift region 10, a trench gate structure 3, a sidewall 4, and a source electrode 6. The following description will be given taking MOSFET devices as N-channel devices as an example.
The base region 11 has a first conductivity type, for example, the base region 11 is a P-type base region; the source region 12 has a second conductivity type, e.g., the source region 12 is an N-type source region. As shown in fig. 1, a base region 11 is formed on a source region 12 between two trench gate structures 3. The first conduction type and the second conduction type belong to different semiconductor conduction types, a first PN junction is formed between the source region 12 and the base region 11, and the base region 11 and the source region 12 are respectively and electrically connected with the first electrode 2 through the source electrode 6.
The drift region 10 is located below the base region 11, and has a second conductivity type (for example, N type) for acting as a depletion layer in the forward withstand voltage process of the MOSFET device; a second PN junction is formed between the drift region 10 and the base region 11, and the second electrode 1 is electrically connected to the drift region 10.
For example, the MOSFET device may further comprise a substrate or buffer layer, the substrate being located below the drift region 10 and having the second conductivity type, the substrate being electrically connected to the second electrode 1 for providing carriers in the on-state of the MOSFET device. In addition, a buffer layer may be further disposed between the substrate and the drift region 10, the buffer layer having the second conductivity type. The details may vary depending on the actual type of device used.
The trench gate structure 3 comprises a gate 30 and a gate dielectric layer 31 wrapping the gate 30, the bottom of the gate 30 penetrates through the base region 11 and extends to the drift region 10, and the top of the gate 30 is higher than the top surface of the source region 12, so that when the fourth dielectric layer 41 is etched back, side walls 4 are formed on two sides of the trench gate structure 3; the two trench gate structures 3 are respectively located at two sides of the source region 12. The material of the gate 30 may be polysilicon or other available gate 30 materials, such as metal; the material of the gate dielectric layer 31 may be silicon dioxide, or other insulating dielectric, such as a high dielectric constant material or a silicon oxynitride gate dielectric structure, for example. The trench gate structure 3 is respectively contacted with the source region 12 and the base region 11, a channel can be formed in the base region 11 when the positive grid 30 is subjected to voltage drop, normal conduction of a device is guaranteed, meanwhile, the channel can be turned off by the negative voltage drop grid 30, the device is in an off state, high voltage is borne, and electric leakage is reduced.
The spacers 4 are located above the drift region 10 (corresponding to the base region 11 and the source region 12) and on two sides of the trench gate structures 3, and a region between the two spacers 4 between the two trench gate structures 3 is defined as a first region 42, where the first region 42 may refer to a dashed frame region shown in fig. 11. The material of the sidewall spacer 4 may be silicon nitride or silicon oxynitride or other available hard mask materials.
The source electrode 6 penetrates through the source region 12 and a part of the base region 11 after passing through the first region 42, and is electrically connected to the source region 12 and the base region 11, and the source electrode 6 is electrically connected to the first electrode 2.
In one practical application, the base region 11 may further include a first doped region 111, the first doped region 111 is formed around the bottom of the source contact hole 61, the first doped region 111 is used for electrically connecting with the source electrode 6 and forming an ohmic contact, the first doped region 111 has the first conductivity type, and the doping concentration of the first doped region 111 is greater than that of the base region 11. For example, after the source contact hole 61 is formed, ion implantation is performed to the base region 11 through the source contact hole 61, and first conductivity type doping, such as P-type ion implantation, may be boron element, is performed.
In a practical application, the semiconductor unit may further include a fifth dielectric layer 5, the fifth dielectric layer 5 covers the sidewall 4 and the trench gate structure 3, the source electrode 6 penetrates through the fifth dielectric layer 5, and the first electrode 2 is formed above the fifth dielectric layer 5. The fifth dielectric layer 5 may be made of the same material as the gate dielectric layer 31, for example, silicon dioxide. The fifth dielectric layer 5 is used for isolating the first electrode 2 from the trench gate structure 3, and can also play a role in passivation.
In the MOSFET device provided by the embodiment of the invention, the source contact hole 61 is formed by self-aligning the first region 42 formed by the side wall 4, so that the source electrode 6 is isolated from the gate 30, the phenomenon that the source contact hole 61 deviates from a preset position due to the precision of a machine tool to cause short circuit of the rest gate 30 of the source electrode 6 is avoided, and the yield of device manufacturing is improved. Meanwhile, the source electrode 6 with the precision smaller than that of a machine tool is formed by etching, and the size of the device is effectively reduced.
Example two:
next, a MOSFET device will be described as an example of an N-channel MOSFET device. In an embodiment, the first conductivity type is P-type and the second conductivity type is N-type.
Referring to fig. 2, the present embodiment provides a method for manufacturing a MOSFET device, including:
step 1: as shown in fig. 3, providing a base, wherein the base includes the drift region 10, or the base includes a substrate and the drift region 10 stacked from bottom to top; the drift region 10 is used as a depletion layer in the forward voltage withstanding process of the MOSFET device; the substrate is used to provide carriers when the MOSFET device is in an on-state. For example, the substrate has the second conductivity type and is an N-type silicon wafer, and the drift region 10 may be formed on the substrate by means of epitaxy. In this embodiment, the base may only include the drift region 10, and the drift region 10 may be formed by epitaxy on a substrate and then the substrate is removed, or a silicon wafer with a certain thickness is directly used as the drift region 10. In the present embodiment, the base region 11 has a first conductivity type; the substrate, the source region 12 and the drift region 10 have a second conductivity type, the first and second conductivity types being of different semiconductor conductivity types; a first PN junction is formed between the source region 12 and the base region 11, and a second PN junction is formed between the drift region 10 and the base region 11.
Step 2: as shown in fig. 4-10, a trench gate structure 3 is formed on the drift region 10, the trench gate structure 3 may include a gate 30 and a gate dielectric layer 31 wrapping the gate 30, and a top of the gate 30 is higher than a top surface of the drift region 10; the bottom of the gate 30 extends into the drift region 10.
Specifically, the step 2 may include:
as shown in fig. 3 and 4, a first dielectric layer 34 is formed on the drift region 10, the first dielectric layer 34 is patterned to obtain first windows 35 corresponding to the two trench gate structures 3, and a hard mask layer 341 may be further formed on the first dielectric layer 34.
For example, as shown in fig. 3, a first dielectric layer 34 and a hard mask layer 341 are sequentially deposited and formed on the drift region 10 by a thin film process, wherein the first dielectric layer 34 may be a silicon dioxide layer with a thickness of 200A-300A, and the hard mask layer 341 may be a silicon nitride layer with a thickness of 1500A-2000A.
As shown in fig. 4, a pattern corresponding to the first window 35 is formed by photolithography, and the hard mask layer 341 and the first dielectric layer 34 are etched by dry etching under the masking of the photoresist.
As shown in fig. 5, a first trench 101 corresponding to the trench gate structure 3 is then formed on the drift region 10 through the first window 35 by dry etching, and the region of the first trench 101 is shown as the dashed-line frame region shown in fig. 5; in one implementation, the depth of the first trench 101 may be 0.9um to 1.4 um.
As shown in fig. 6A and 6B, a second dielectric layer 32 is formed on the surface of the first trench 101, the second dielectric layer 32 and the first window 35 form a second trench 102, and the region of the second trench 102 is shown as the region indicated by the dashed line in fig. 6A and 6B; the gate dielectric layer 31 includes a second dielectric layer 32.
In practical applications, the second dielectric layer 32 may be formed by a diffusion process or a thin film process, for example, as shown in fig. 6A, the second dielectric layer 32 is formed on the first trench 101 by a diffusion process, specifically, by a thermal oxidation process, where the second dielectric layer 32 is a silicon dioxide layer. For another example, as shown in fig. 6B, a second dielectric layer 32 is deposited on the first trench 101 by using a thin film process, where the second dielectric layer 32 may be a silicon dioxide layer, or may be another usable dielectric layer, such as a high-k dielectric layer. In this embodiment, the second dielectric layer 32 shown in FIG. 6A is formed by a diffusion process, which may be 400A-600A thick.
As shown in fig. 7, the second trench 102 is filled with polysilicon to obtain the gate 30. For example, the second trench 102 is filled with polysilicon by a thin film process, and the polysilicon outside the second trench 102 may be removed by CMP or etching back, if necessary. Thus, the gate 30 in the trench gate structure 3 is completely manufactured, and the gate dielectric layer 31 of the trench gate structure 3 includes the second dielectric layer 32 and may further include a third dielectric layer 33 covering the gate 30 in a subsequent step.
Since the second trench 102 includes a region corresponding to the first window 35, the top of the gate 30 is higher than the top surface of the drift region 10, so as to provide a reference position for the subsequent formation of the sidewall spacer 4, in this embodiment, the height of the top of the gate 30 may be 800A-1400A.
And step 3: as shown in fig. 7 and 8, a base region 11 and a source region 12 are formed on the drift region 10, the source region 12 is located between two trench gate structures 3, and the bottom of the gate 30 is lower than the bottom of the base region 11. Of course, the source regions 12 may also be located on both sides of each trench gate structure 3.
The step 3 may include:
as shown in fig. 7 and 8, the first dielectric layer 34 is removed, and the drift region 10 is doped, so as to obtain the base region 11. For example, the hard mask layer 341 (if any) and the first dielectric layer 34 on the drift region 10 are removed by wet etching, and then P-type ions with a certain depth and concentration are implanted by means of ion implantation to form the base region 11.
Finally, doping is performed on the base region 11 to obtain the source region 12. For example, the source region 12 is formed by implanting N-type ions by means of ion implantation. When ion implantation is performed, the photolithography process involved is not described. And after ion implantation is completed, removing the photoresist on the surface.
And 4, step 4: as shown in fig. 10 and 11, side walls 4 are formed on two sides of the trench gate structure 3, where the side walls 4 are located above the drift region 10, and after the source electrode 12 and the base region 11 are formed, are correspondingly located above the source region 12 and the base region 11; and are located at two sides of the trench gate structures 3, and a region between the two sidewalls 4 between the two trench gate structures 3 is defined as a first region 42, as shown by the dashed frame region in fig. 11.
The step 4 may include:
as shown in fig. 10, a third dielectric layer 33 is formed to cover the gate 30, the source region 12 and the base region 11, and a fourth dielectric layer 41 is formed to cover the third dielectric layer 33; the third dielectric layer 33 and the second dielectric layer 32 are used for wrapping the gate 30, and the third dielectric layer 33 and the second dielectric layer 32 on the periphery of the gate 30 form a gate dielectric layer 31. At this time, the material of the third dielectric layer 33 is the same as that of the second dielectric layer 32, and when the second dielectric layer 32 is formed by thermal oxidation, the third dielectric layer 33 corresponds to a silicon dioxide layer. For example, the third dielectric layer 33 may be formed by deposition through a thin film process, and the thickness may be 200A-300A; the fourth dielectric layer 41 may be made of any hard mask material, such as silicon nitride or silicon oxynitride, and may be formed by depositing a silicon nitride layer with a thickness of 800A-1000A by a thin film process.
As shown in fig. 11, the fourth dielectric layer 41 is etched back, and portions on two sides of the trench gate structure 3 are retained, so as to obtain the sidewalls 4. The fourth dielectric layer 41 is etched by using a dry etching process, and since the gate 30 is higher than the surface of the base region 11 (by 800A-1400A in this embodiment), portions of the fourth dielectric layer 41 on both sides of the trench gate structure 3 are retained to serve as a protective film and a self-aligned structure for subsequent etching of the source contact hole 61.
And 5: as shown in fig. 12 to 16, the source region 12 and a part of the base region 11 are patterned under the mask of the sidewall 4 to form a source contact hole 61, and the source electrode 6 is formed on the source contact hole 61, and the source contact hole 61 penetrates through the source region 12 and a part of the base region 11.
The step 5 may include:
as shown in fig. 12 and 13, a fifth dielectric layer 5 is formed to cover the sidewall spacers 4 and the third dielectric layer 33, and the fifth dielectric layer 5 is patterned to obtain a second window 51 corresponding to the source electrode 6. For example, the fifth dielectric layer 5 (ILD) is formed by depositing oxygen-rich silicon dioxide (SRO) and boron-phosphorous doped silicon dioxide (BPSG) by a thin film process. Or directly depositing silicon dioxide to form the fifth dielectric layer 5.
Specifically, a photoresist is formed on the fifth dielectric layer 5, photolithography is performed to obtain a pattern corresponding to the second window 51, and the fifth dielectric layer 5 is etched under the masking of the photoresist layer to obtain the second window 51. As shown in fig. 12, when the minimum size of the second window 51 is larger than the size of the first region 42 of the sidewall 4 between two trench gate structures 3, the second window 51 similar to the illustration is formed, the size of the opening above the second window 51 is large, due to the precision limitation of the production machine, the opening portion is not necessarily centered with respect to the first region 42, but the lower portion of the second window 51 can only etch the first region 42 and the corresponding fifth dielectric layer 5 therebelow due to the effect of the hard mask (the fourth dielectric layer 41).
As shown in fig. 14, the source contact hole 61 is formed by patterning the source region 12 and a part of the base region 11 through the second window 51 and under the mask of the sidewall 4. For example, the source contact hole 61 is formed by wet etching, and in the present embodiment, the etching depth may be 0.4 um.
In one practical application, before forming the source electrode 6, the method may further include:
as shown in fig. 15, doping is performed on the base region 11 through the source contact hole 61 to form a first doping region 111, the first doping region 111 is used to be electrically connected to the source electrode 6 and to form an ohmic contact, the first doping region 111 has the first conductivity type, and the doping concentration of the first doping region 111 is greater than that of the base region 11. For example, the base region 11 is implanted with P-type ions by means of ion implantation.
As shown in fig. 16, the source electrode 6 is formed on the source contact hole 61. For example, a layer of titanium metal or titanium nitride is deposited as an adhesion layer. Tungsten metal is then deposited, filling the source contact hole 61, and the adhesion layer and tungsten metal outside the source contact hole 61 are removed by etching back.
Step 6: as shown in fig. 17, a first electrode 2 and a second electrode 1 are formed, a source electrode 6 is electrically connected to the first electrode 2, the first electrode 2 is electrically connected to a base region 11 and a source region 12 via the source electrode 6, respectively, and a substrate is electrically connected to the second electrode 1.
For example, a layer of al-si-cu metal is deposited as the first electrode 2, electrically connected to the source electrode 6, and covering the fifth dielectric layer 5. The drift region 10 or the back surface (bottom surface in the figure) of the substrate is thinned, and a layer of titanium-nickel-silver metal is deposited to be used as the second electrode 1, and the second electrode 1 is electrically connected with the drift region 10 or the substrate.
Because there is the protection of silicon nitride both sides of ditch groove gate structure 3, and when source contact hole 61 sculpture, select the plasma that silicon nitride and silicon dioxide selectivity are high to carry out the sculpture, source contact hole 61 can be along the silicon nitride (side wall 4) downward sculpture of polycrystalline silicon both sides, even like this the size of source contact hole 61 (second window 51) is less than the minimum that the board can be controlled to aim at, also can guarantee source contact hole 61 can not short circuit with polycrystalline silicon (grid 30), and then improved the window of current technology, and can further reduce the size of ditch groove type power tube, thereby improve product cost advantage.
It should be understood that the description of the material type, the depth dimension, the thickness dimension, etc. of each device structure given in the embodiments of the present invention is merely illustrated as an example of practical application, and is not intended to limit the MOSFET device and the manufacturing method thereof provided by the present invention. The shapes of the various structures shown in the drawings are illustrative only and do not show the actual shapes of the structures.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (10)
1. A method of fabricating a MOSFET device, comprising:
providing a substrate comprising a drift region (10); the drift region (10) is used as a depletion layer in the process that the MOSFET device is in forward voltage resistance;
forming a trench gate structure (3) on the drift region (10), wherein the trench gate structure (3) comprises a gate (30) and a gate dielectric layer (31) wrapping the gate (30), and the top of the gate (30) is higher than the top surface of the drift region (10); the bottom of the gate (30) extends into the drift region (10);
forming a base region (11) and a source region (12) on the drift region (10), wherein the source region (12) is positioned between the two trench gate structures (3), and the bottom of the gate (30) is lower than the bottom surface of the base region (11);
forming side walls (4) on two sides of the trench gate structure (3), wherein the side walls (4) are located above the drift region (10) and on two sides of the trench gate structure (3), and a region between the two side walls (4) between the two trench gate structures (3) is defined as a first region (42);
patterning the source region (12) and part of the base region (11) under the masking of the side wall (4) to form a source contact hole (61), forming a source electrode (6) on the source contact hole (61), wherein the source contact hole (61) penetrates through the source region (12) and part of the base region (11);
forming a first electrode (2) and a second electrode (1), wherein the source electrode (6) is electrically connected with the first electrode (2), the first electrode (2) is respectively and electrically connected with the base region (11) and the source region (12) through the source electrode (6), and the drift region (10) is electrically connected with the second electrode (1); wherein the base region (11) has a first conductivity type; the source region (12) and the drift region (10) have a second conductivity type, the first and second conductivity types being of different semiconductor conductivity types; a first PN junction is formed between the source region (12) and the base region (11), and a second PN junction is formed between the drift region (10) and the base region (11).
2. The manufacturing method according to claim 1, further comprising, before forming the source electrode (6):
and doping the base region (11) through the source contact hole (61) to form a first doping region (111), wherein the first doping region (111) is used for being electrically connected with the source electrode (6) and forming ohmic contact, the first doping region (111) has a first conductivity type, and the doping concentration of the first doping region (111) is greater than that of the base region (11).
3. The manufacturing method according to claim 1 or 2, wherein the forming of the trench-gate structure (3) on the drift region (10) comprises:
forming a first dielectric layer (34) on the drift region (10), and carrying out patterning treatment on the first dielectric layer (34) to obtain first windows (35) corresponding to the two trench gate structures (3);
forming a first trench (101) corresponding to the trench gate structure (3) on the drift region (10) through the first window (35);
forming a second dielectric layer (32) on the surface of the first groove (101), wherein the second dielectric layer (32) and the first window (35) form a second groove (102); the gate dielectric layer (31) comprises the second dielectric layer (32);
and filling polysilicon in the second groove (102) to obtain the gate (30).
4. A method of manufacturing according to claim 3, wherein the forming of a base region (11) and a source region (12) on the drift region (10) comprises:
removing the first dielectric layer (34), and doping the drift region (10) to obtain the base region (11);
and doping the base region (11) to obtain the source region (12).
5. A method according to claim 3, wherein forming side walls (4) on both sides of the trench-gate structure (3) comprises:
forming a third dielectric layer (33) covering the grid electrode (30), the source region (12) and the base region (11), and forming a fourth dielectric layer (41) covering the third dielectric layer (33); the third dielectric layer (33) and the second dielectric layer (32) are used for wrapping the grid electrode (30), and the third dielectric layer (33) and the second dielectric layer (32) form the grid dielectric layer (31);
and carrying out back etching on the fourth dielectric layer (41), and reserving parts on two sides of the trench gate structure (3) to obtain the side wall (4).
6. The manufacturing method according to claim 5, wherein the step of patterning the source region (12) and a part of the base region (11) under the masking of the side wall (4) to form a source contact hole (61) comprises:
forming a fifth dielectric layer (5) covering the side wall (4) and the third dielectric layer (33), and patterning the fifth dielectric layer (5) to obtain a second window (51) corresponding to the source electrode (6);
and patterning the source region (12) and part of the base region (11) through the second window (51) under the masking of the side wall (4) to form a source contact hole (61).
7. A MOSFET device, characterized by being manufactured with the manufacturing method of any one of claims 1-6.
8. A MOSFET device comprising a first electrode (2), a second electrode (1) and a semiconductor cell located between the first electrode (2) and the second electrode (1), the semiconductor cell comprising:
a base region (11) having a first conductivity type;
a source region (12) having a second conductivity type, the first conductivity type and the second conductivity type being different semiconductor conductivity types, a first PN junction being formed between the source region (12) and the base region (11), the base region (11) and the source region (12) being electrically connected to the first electrode (2) through a source electrode (6), respectively;
a drift region (10) located below the base region (11) and having a second conductivity type for acting as a depletion layer during forward withstand voltage of the MOSFET device; a second PN junction is formed between the drift region (10) and the base region (11), and the drift region (10) is electrically connected with the second electrode (1);
the trench gate structure (3) comprises a gate electrode (30) and a gate dielectric layer (31) wrapping the gate electrode (30), the bottom of the gate electrode (30) penetrates through the base region (11) and extends to the drift region (10), and the top of the gate electrode (30) is higher than the top surface of the source region (12); the two trench gate structures (3) are respectively positioned at two sides of the source region (12);
the side walls (4) are positioned above the source region (12) and on two sides of the trench gate structures (3), and a region between the two side walls (4) between the two trench gate structures (3) is defined as a first region (42);
a source electrode (6) passing through the first region (42) and then penetrating through the source region (12) and a portion of the base region (11), the source electrode (6) being electrically connected to the first electrode (2).
9. The MOSFET device according to claim 8, wherein the base region (11) further comprises a first doped region (111), the first doped region (111) being adapted to be electrically connected to the source electrode (6) and form an ohmic contact, the first doped region (111) having a first conductivity type, the first doped region (111) having a doping concentration which is greater than the doping concentration of the base region (11).
10. The MOSFET device according to claim 8 or 9, wherein the semiconductor unit further comprises a fifth dielectric layer (5), wherein the fifth dielectric layer (5) covers the sidewall spacers (4) and the trench gate structure (3), wherein the source electrode (6) penetrates through the fifth dielectric layer (5), and wherein the first electrode (2) is formed above the fifth dielectric layer (5).
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