KR960005249B1 - Dram manufacture method - Google Patents

Abstract

forming a trench(3) for forming a vertical MOSFET channel region in a semiconductor substrate(2); removing a photosensitive film(5) to form final fine gate electrode(6) and word line(7) by etching an exposed polysilicon; depositing an insulation oxide film(10) and BPSG film(11) of regular thickness to insulate elements from one another and performing a planarising process by etching the whole surface; depositing mask polysilicon using the bit line contact hole mask and forming a spacer polysilicon(13) by anisotropic etching process; forming bit line(14,14') by silicide and polysilicon in turn using the bit line mask, performing planarising process by etching BPSG film(16), and forming a etching barrier film(17), a sacrificial oxide film(18) and a mask polysilicon(19) in turn; forming a charge storage electrode(21); and forming a plate electrode(23) by depositing the polysilicon with implanted impurity ions and etching the polysilicon using the mask. The method decreases the area of unit cell of DRAM and short channel effect of MOSFET, and enhances reliability of element.

Description

DRAM manufacturing method of semiconductor integrated device

1 is a diagram showing the formation of a DRAM in one embodiment by a conventional method,

2 is a DRAM process diagram of one embodiment according to the present invention.

* Explanation of symbols for main parts of the drawings

1: semiconductor substrate 2: field oxide film

3: trench 4: gate oxide film

5 photosensitive film 6 gate electrode

7 word line 8 spacer oxide film

9, 9 ': MOSFET active region 10, 15: oxide film

11, 16: BPSG film 12, 19: mask polysilicon

13, 20: spacer polysilicon 14, 14 ': bit line

17 etching barrier film 18 sacrificial oxide film

21: charge preservation electrode 22: dielectric film

23: plate electrode

The present invention provides a semiconductor integrated device (DRAM) that solves a short channel problem of a MOSFET by easily adjusting a channel length of a MOSFET while reducing a unit area of a DRAM cell using a relatively easy process method. It relates to a manufacturing method.

In general, the main factors related to the integration of DRAM, which is a general-purpose semiconductor memory device, include a reduction in the cell area, consequent limitations in process capability, and deterioration in characteristics of MOSFET devices. However, in order to achieve high integration of semiconductor integrated circuits, the reduction of the unit area is an inevitable task. Accordingly, with the development of advanced process technology, securing the reliability of each unit device is also an urgent problem.

Conventional DRAM cells use a MOSFET that is a switch element parallel to the surface of a semiconductor substrate, and each cell is composed of one MOSFET and a capacitor. The manufacturing process will be described with reference to FIG. 1 is a semiconductor substrate, 2 is a field oxide film, 4 is a gate oxide film, 6 is a gate electrode, 7 is a word line, 8 is a spacer oxide film, 9, 9 'is a MOSFET active region, 10, 15 is an oxide film, 11, 16 represents a BPSG film, 13 and 20 are spacer polysilicon films, 14 and 14 'are bit lines, 21 is a charge storage electrode, 22 is a dielectric film, and 23 is a plate electrode.

First, the field oxide film 2 is formed on the semiconductor substrate 1, the gate oxide film 4 is grown, and then the impurity implantation process is performed by depositing the polysilicon for the gate electrode 6 and the word line 7 immediately. After forming the pattern, in order to improve the electrical characteristics of the MOSFET due to the high integration, an LDD structure MOSFET formation process having a spacer oxide film 8 and active regions 9 and 9 'was performed, followed by an insulating oxide film of a high temperature oxidation method. 10 and the BPSG film 11 are formed, and contact holes are formed on the active region 9 by a self-aligning method using the mask polysilicon 12 and the spacer polysilicon 13, and impurities are injected into the contact holes. Polysilicon is deposited and connected to the active region, silicide is deposited thereon, and then a bit line 14 pattern is formed. Subsequently, an oxide film 15 and a BPSG film for insulation are deposited, and contact holes are formed on the active region 9 'using a mask polysilicon 19 and a spacer polysilicon 20 in a self-aligning manner, and impurities are formed on the contact holes. The implanted polysilicon is deposited to be connected to the active region, the charge storage electrode 21 pattern is formed, and then an ON or ONO composite dielectric film is grown, and the plate electrode is made of polysilicon implanted with impurities thereon. Capacitor with (23) is configured to complete the main process of existing DRAM Cell. Given the current process capability, semiconductor integrated circuits manufactured in such a structure are increasingly difficult to solve the above-mentioned problems, and in order to solve them, cost rises such as expensive equipment support.

The present invention devised to solve the above problems is to provide a DRAM manufacturing method of a semiconductor integrated device to increase the efficiency of the process capability is relatively easy in realizing a structure corresponding to the reduction of the unit area due to the high integration of the semiconductor integrated circuit. There is this.

Therefore, in order to achieve the above object, the present invention provides a method for manufacturing a semiconductor integrated circuit (DRAM), wherein a field oxide film is grown on a semiconductor substrate on which an N-Well (N-type well) (or P-Well) is formed, In the first step of forming a trench for forming a vertical MOSFET channel region in a portion where no oxide film is formed, a gate oxide film, a gate electrode, and a polysilicon for the word line are deposited after the first step, and then an impurity implantation process is performed to form the polysilicon. Forming a predetermined Cree gate electrode to form a final fine gate electrode and a word line to remove the photosensitive film, and implanting impurity ions into the polysilicon film remaining after the second step; After the oxide film is formed, the MOSFET active region is formed, and an insulating oxide film and a BPSG film having a predetermined thickness are coated to insulate the devices. After the third step of performing the planarization process by surface etching, after the third step, a mask polysilicon having a predetermined thickness is deposited, and the mask polysilicon and some BPSG films are etched using a bit line contact hole mask, and then a predetermined thickness of poly A fourth step of forming silicon spacers by annealing by etching silicon to form a spacer polysilicon; after the fourth step, a contact hole is formed on the active region, and polysilicon implanted with impurities into the contact hole is deposited to form an active region. After the interconnection, silicide was deposited thereon, and then, by using a bit line mask, silicide and polysilicon were sequentially etched to form bit lines, followed by deposition of an insulating oxide film and a BPSG film, followed by planarization of the BPSG film by full etching. A fifth step of sequentially depositing an etch barrier layer, a sacrificial oxide layer, and a mask polysilicon layer; After the fifth step, the mask polysilicon, the sacrificial oxide layer, and the etch barrier layer are sequentially etched, and then spacer polysilicon is formed to form a contact hole in the active region of the MOSFET and deposit polysilicon implanted with impurities on the contact hole. A sixth step of connecting the active region to form a charge preservation electrode with a predetermined cree; after the sixth step, the sacrificial oxide film is etched to deposit a dielectric film along the surface of the charge preservation electrode, and then a polyimide implanted with And depositing silicon and etching polysilicon using a mask to form a plate electrode.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to FIG. 2. In the drawings, 3 is a trench, 5 is a photoresist film, 12, 19 is a mask polysilicon film, 17 is an etch barrier film, 18 is Each sacrificial oxide film is shown.

For convenience, the manufacturing process will be described in detail with reference to FIG. 2 showing only a cross section perpendicular to the gate electrode of the DRAM cell.

FIG. 2 (a) shows a portion where a field oxide film 2 is grown on a semiconductor substrate 1 on which an N-Well (or P-Well) is formed by a local oxidation of silicon (LOCOS) method, and the field oxide film 2 is absent. After forming the trench 3 for forming the vertical MOSFET channel region in the region, the gate oxide film 4 and the polysilicon for the gate electrode 6 and the word line 7 of the vertical structure are deposited without time delay, and then impurity implantation. A cross sectional view is performed in which the polysilicon is patterned to form a predetermined claw gate electrode 6 and the photosensitive film 5 is developed to form the final fine gate electrode 6 and the word line 7.

In FIG. 2 (b), polysilicon exposed to the photoresist film 5 is etched to form a final gate electrode 6 and a word line 7, and then the photoresist film is removed, and the N-type film remains on the remaining polysilicon film. (Or P-type) impurity ion implantation is carried out, an oxide film having a predetermined thickness is deposited and etched in an anisotropic manner to form a spacer oxide film 8, and then a relatively high concentration of N-type (or P-type) ion implantation is performed. The MOSFET active regions 9 and 9 'of the LDD structure are formed, and a cross-sectional view of the insulating oxide film 10 having a predetermined thickness is deposited by the high temperature oxidation method for inter-joint insulation.

FIG. 2 (c) shows the deposition of the BPSG film 11 having a predetermined thickness, the planarization process by etching the entire surface, and the deposition of the mask polysilicon 12 having a predetermined thickness thereon, using the bit line contact hole mask. After etching the mask polysilicon 12 and some BPSG film 11, polysilicon having a predetermined thickness is deposited and etched in an anisotropic manner to form the spacer polysilicon 13, and these polysilicon 12, 13 ) And a contact hole is formed on the active region 9 of the MOSFET by the self-aligning method using the etching selectivity of the BPSG film 11, and the polysilicon implanted with impurities is deposited on the contact hole and then connected to the active region. A silicide is deposited thereon, and a bit line 14 is used to sequentially etch silicide and polysilicon to form bits 14 and 14 '.

FIG. 2 (d) shows the deposition of an insulating oxide film 15 having a predetermined thickness by a high temperature oxidation method for inter-device insulation, and the BPSG film 16 having a predetermined thickness is coated on the insulating oxide film 15 to planarize the entire surface by etching. After the process, a silicon nitride film having a predetermined thickness is deposited on the etch barrier film 17, and a sacrificial oxide film 18 having a predetermined thickness is deposited. Subsequently, a mask polysilicon 19 having a predetermined thickness is deposited, and the mask polysilicon 19, the sacrificial oxide film 18, and the etch barrier film 17 are sequentially etched using a charge storage electrode contact hole mask, and then thereon. By depositing polysilicon of a certain thickness, the polysilicon is etched in an anisotropic manner to form spacer polysilicon 20, and self-alignment using the etching selectivity of these polysilicon 19, 20 and BPSG film 16 A contact hole is formed on the active region 9 'of the MOSFET, a polysilicon implanted with impurities is deposited on the contact hole, and is connected to the active region, and then the charge storage electrode 21 is formed to a predetermined size. to be.

FIG. 2 (e) shows that the sacrificial oxide film 18 is wet-etched using the etch barrier film 17 of FIG. 3d as a protective film to compensate for the decrease in charge storage capacity due to the reduction of the cell unit area. A dielectric film 22 of NO (nitride-oxide) or nitride-oxide-nitride (ONO) composite structure is grown along the surface of the charge storage electrode including the effective area of the charge storage electrode, and impurities are implanted therein. After the deposition, the polysilicon is etched using a mask to form a plate electrode 23.

As can be seen from FIG. 1 and FIG. 2 for fabricating a DRAM cell with the same structure and method as in the present invention, a fixed axis is shortened from A to A '(see FIGS. 1 and 2 (e)). By reducing the unit area of the cell, the trench depth can be arbitrarily adjusted to increase the reliability of the device, such as reducing the short channel effect of the MOSFET. There is an advantage that can form a pattern beyond the technical limit.

Claims (6)

In the DRAM manufacturing method of a semiconductor integrated device, a field oxide film 2 is grown on a semiconductor substrate 1 on which an N-Well (N type well) (or P-Well) is formed, and the field oxide film 2 is formed. In the first step of forming a trench 3 for the MOSFET channel region form in a partial region without a vertical region, a polysilicon for the gate oxide film 4, the gate electrode 6 and the word line 7 is formed after the first step. After the impurity implantation process is performed and the polysilicon is patterned to form the gate electrode 6 to a predetermined size, the photoresist film 5 is developed to form the final fine gate electrode 6 and the word line 7. A second step of removing the photoresist film 5 by etching the polysilicon exposed to the photoresist film 5 to form a final gate electrode 6 and a word line 7, and the polysilicon remaining after the second step Impurity ion implantation into the film to form a spacer oxide film 8 A third step of forming the negative MOSFET active regions 9 and 9 ', applying an insulating oxide film 10 and a BPSG film 11 having a predetermined thickness to insulate the devices, and performing a planarization process by etching the entire surface; A fourth step of depositing a mask polysilicon 12 having a predetermined thickness and etching the mask polysilicon by using a bit line contact hole mask to etch in an anisotropic manner to form the spacer polysilicon 13; After the step, a contact hole is formed on the active region 9, polysilicon in which impurities are injected into the contact hole is deposited and connected to the active region, and then silicide is deposited thereon and a silicide and polysilicon are formed using a bit line mask. After etching to form bit lines 14 and 14 ', the insulating oxide film 15 and the BPSG film 16 are sequentially deposited to planarize the BPSG film 16 by full etching. A fifth step of sequentially depositing an etch barrier layer 17, a sacrificial oxide layer 18, and a mask polysilicon 19, and after the fifth step, the mask polysilicon 19, a sacrificial oxide layer 18, and an etch barrier layer (17) is sequentially etched to form a spacer polysilicon 20 to form a contact hole over the active region 9 'of the MOSFET, and deposit polysilicon implanted with impurities on the contact hole to connect the active region. Next, the sacrificial oxide film 18 is etched after the sixth step of forming the charge preservation electrode 21 to a predetermined size, and the dielectric film 22 is deposited along the surface of the charge preservation electrode 21. And a seventh step of depositing polysilicon implanted with impurities and etching the polysilicon using a mask to form a plate electrode (23). The DRAM of claim 1, wherein the gate electrode 6 of the second step has a vertical structure, and the channel is formed by adjusting the depth of the trench 3 of the first step. ) Manufacturing method. The method of claim 1, wherein the formation of the bit line 14 in the fifth step is performed on the active region 9 of the MOSFET in a self-aligning manner using an etch selectivity of the polysilicon 12, 13 and the BPSG film 11. A DRAM manufacturing method of a semiconductor integrated device, which is deposited in the formed contact hole. The active region 9 'of the MOSFET according to claim 1, wherein the formation of the charge storage electrode 21 in the sixth step is performed using a magnetostatic method using an etching selectivity of the polysilicon 19, 20 and the BPSG film 16. A DRAM manufacturing method of a semiconductor integrated device, which is deposited on a contact hole formed thereon. The method of claim 1, wherein the etching obstacle (17) of the fifth step is a silicon nitride film. The DRAM of claim 1, wherein the dielectric layer 22 of the seventh step is formed of one of a complex structure of NO (nitride-oxide) or ONO (nitride-oxide-nitride). Manufacturing method.