KR100265370B1 - A method for fabricating dram device - Google Patents

A method for fabricating dram device Download PDF

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KR100265370B1
KR100265370B1 KR1019970029687A KR19970029687A KR100265370B1 KR 100265370 B1 KR100265370 B1 KR 100265370B1 KR 1019970029687 A KR1019970029687 A KR 1019970029687A KR 19970029687 A KR19970029687 A KR 19970029687A KR 100265370 B1 KR100265370 B1 KR 100265370B1
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South Korea
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bit line
charge storage
drain
storage electrode
source
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KR1019970029687A
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Korean (ko)
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KR19990005489A (en
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양정윤
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Abstract

PURPOSE: A method for manufacturing a DRAM is provided to prevent an etching damage of a source/drain by preventing mis-alignment due to a mask process. CONSTITUTION: A MOS transistor including a source/drain(35), a gate insulating layer, and a gate electrode(32) is formed on a semiconductor substrate(30). An epitaxial layer is grown selectively on the source/drain(35). A conductive layer for bit line and an insulating layer(33,38) are formed on an upper portion of the whole structure. A bit line(37) contacted with the epitaxial layer is formed by etching the insulating layer(33,38) and the conductive layer for bit line. A spacer insulating layer(34,39) is formed to cover a sidewall of the bit line(37). A conductive layer for charge storage electrode is deposited on the whole structures. A charge storage electrode(40) is formed by etching selectively the conductive layer for charge storage electrode.

Description

디램 제조방법{A METHOD FOR FABRICATING DRAM DEVICE}DRAM manufacturing method {A METHOD FOR FABRICATING DRAM DEVICE}

본 발명은 반도체 제조 기술에 관한 것으로, 특히 DRAM(dynamic random access memory) 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a dynamic random access memory (DRAM).

반도체 장치의 고집적화에 수반되는 디자인 룰(design rule)의 감소에 따라 작은 면적에서 보다 효율적인 비트라인 및 전하저장전극을 형성하는 기술이 요구되고 있다.As the design rule accompanying high integration of semiconductor devices decreases, a technique for forming more efficient bit lines and charge storage electrodes in a small area is required.

첨부된 도면 도 1a 내지 도 1d는 종래기술에 따른 DRAM 제조 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.1A to 1D illustrate a DRAM manufacturing process according to the prior art, which will be described with reference to the following.

종래기술에 따른 DRAM 제조 공정은, 우선 도 1a에 도시된 바와 같이 실리콘 기판(10) 상에 소자간의 전기적 격리를 위한 소자 분리막(11)을 형성한 후, 게이트 산화막(도시되지 않음), 게이트 전극(12) 및 마스크 절연막(13)을 형성한다. 계속하여, LDD(Lightly Doped Drain) 이온주입을 실시하고, 전체 구조 상부에 산화막을 증착한 후 이를 전면 식각하여 게이트 전극(12)의 측벽 부위에 스페이서 절연막(14)을 형성한다. 이어서, 고농도 불순물 이온주입 및 열처리를 실시하고 소오스/드레인(15)을 형성한다.According to the DRAM manufacturing process according to the related art, first, as shown in FIG. 1A, a device isolation layer 11 for electrical isolation between devices is formed on a silicon substrate 10, followed by a gate oxide film (not shown) and a gate electrode. 12 and a mask insulating film 13 are formed. Subsequently, LDD (Lightly Doped Drain) ion implantation is performed, an oxide film is deposited on the entire structure, and then the entire surface is etched to form a spacer insulating film 14 on the sidewall portion of the gate electrode 12. Subsequently, high concentration impurity ion implantation and heat treatment are performed to form the source / drain 15.

다음으로, 도 1b에 도시된 바와 같이 전체 구조 상부에 층간절연막(16)을 형성한 후, 이를 선택 식각하여 비트라인 콘택홀을 형성한다.Next, as shown in FIG. 1B, the interlayer insulating layer 16 is formed on the entire structure, and then selectively etched to form a bit line contact hole.

이어서, 도 1c에 도시된 바와 같이 전체 구조 상부에 전도막 및 절연막을 증착하고, 이를 패터닝하여 비트라인(17) 및 마스크 절연막(18)을 형성한다. 계속하여, 전체 구조 상부에 층간절연막(19)을 형성한 후, 이를 선택적 식각하여 전하저장전극 콘택홀을 형성한다.Subsequently, as illustrated in FIG. 1C, a conductive film and an insulating film are deposited on the entire structure, and patterned to form a bit line 17 and a mask insulating film 18. Subsequently, an interlayer insulating film 19 is formed over the entire structure, and then selectively etched to form a charge storage electrode contact hole.

끝으로, 도 1d에 도시된 바와 같이 전체 구조 상부에 전도막을 증착한 다음, 이를 패터닝하여 전하저장 전극(20)을 형성한다.Finally, a conductive film is deposited on the entire structure as shown in FIG. 1D and then patterned to form the charge storage electrode 20.

상기와 같은 종래기술은 비트라인 및 전하저장 전극을 콘택홀 식각 공정을 통해 하부층과 연결함으로써, 콘택홀 형성시 오정렬(misalign)에 의하여 워드라인(게이트 전극)의 스페이서 절연막이 식각되어 워드 라인과의 단락이 발생할 수 있는 문제점이 있다. 또한, 콘택홀 식각시 소오스/드레인(15)이 노출되므로 식각 손상에 의한 누설전류의 증가를 유발하게 된다. 이러한 문제점들은 DRAM의 고집적화에 따라 더욱 심각한 영향을 미치게 된다.As described above, the bit line and the charge storage electrode are connected to the lower layer through a contact hole etching process, so that a spacer insulating layer of the word line (gate electrode) is etched by misalignment when forming the contact hole, thereby forming a connection with the word line. There is a problem that a short circuit may occur. In addition, since the source / drain 15 is exposed during the contact hole etching, the leakage current may be increased due to the etching damage. These problems are more severely affected by the high integration of DRAM.

본 발명은 비트라인 및 전하저장 전극용 콘택홀 형성시 마스크 공정에 의한 오정렬을 방지함은 물론, 소오스/드레인의 식각 손상을 방지할 수 있는 디램 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for manufacturing a DRAM capable of preventing misalignment caused by a mask process when forming contact holes for bit lines and charge storage electrodes, and preventing etch damage of a source / drain.

도 1a 내지 도 1d는 종래기술에 따른 DRAM 제조 공정도.1A-1D illustrate a DRAM manufacturing process in accordance with the prior art.

도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 DRAM 제조 공정도.2A-2D illustrate a DRAM manufacturing process in accordance with one embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

30 : 실리콘 기판 31 : 소자분리막30: silicon substrate 31: device isolation film

32 : 게이트 전극(워드라인) 33, 38 : 마스크 절연막32: gate electrode (word line) 33, 38: mask insulating film

34, 39 : 스페이서 절연막 35 : 소오스/드레인34, 39: spacer insulating film 35: source / drain

36 : 에피택셜 실리콘층 37 : 비트라인36 epitaxial silicon layer 37 bit line

40 : 전하저장전극40: charge storage electrode

상기의 기술적 과제를 달성하기 위한 본 발명의 특징적인 디램 제조방법은, 반도체 기판 상에 소오스/드레인, 게이트 절연막 및 그 상부와 측벽이 절연된 게이트 전극으로 구비한 모스 트랜지스터를 형성하는 제1 단계; 상기 소오스/드레인 상에 선택적으로 전도성을 가진 에피택셜층을 성장시키는 제2 단계; 상기 제2 단계를 마친 전체 구조 상부에 비트라인용 전도막 및 절연막을 형성하는 제3 단계; 상기 절연막 및 상기 비트라인용 전도막을 선택 식각하여 상기 에피택셜층에 콘택되는 비트라인을 형성하는 제4 단계; 상기 비트라인의 측벽을 덮는 스페이서 절연막을 형성하는 제5 단계; 상기 제5 단계를 마친 전체 구조 상부에 전하저장 전극용 전도막을 증착하는 제6 단계; 및 상기 전하저장 전극용 전도막을 선택 식각하여 상기 에피택셜층에 콘택되는 전하저장 전극을 형성하는 제7 단계를 포함하여 이루어진다.According to another aspect of the present invention, there is provided a DRAM manufacturing method comprising: forming a MOS transistor including a source / drain, a gate insulating layer, and a gate electrode insulated from an upper side and a sidewall thereof on a semiconductor substrate; Growing a selectively conductive epitaxial layer on the source / drain; A third step of forming a bit line conductive film and an insulating film on the entire structure after the second step; A fourth step of selectively etching the insulating film and the conductive film for the bit line to form a bit line contacting the epitaxial layer; Forming a spacer insulating layer covering sidewalls of the bit line; A sixth step of depositing a conductive film for a charge storage electrode on the entire structure after the fifth step; And forming a charge storage electrode contacting the epitaxial layer by selectively etching the conductive film for the charge storage electrode.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

첨부된 도면 도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 DRAM 제조 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.2A to 2D illustrate a DRAM manufacturing process according to an exemplary embodiment of the present invention, which will be described with reference to the following.

본 실시예에 따른 DRAM 제조 공정은, 먼저, 도 2a에 도시된 바와 같이 실리콘 기판(30) 상에 소자간의 전기적 격리를 위한 소자 분리막(31)을 형성한 후, 게이트 산화막(도시되지 않음), 게이트 전극(32) 및 마스크 절연막(33)을 형성한다. 계속하여, LDD 이온주입을 실시하고, 전체 구조 상부에 산화막을 증착한 후 이를 전면 식각하여 게이트 전극(32)의 측벽 부위에 스페이서 절연막(34)을 형성한다. 이어서, 고농도 불순물 이온주입을 실시하여 소오스/드레인(35)을 형성한 다음, 이후의 비트라인 형성시 드레인을 보호하며, 소오스/드레인 전극 역할을 하는 에피택셜 실리콘막(36)을 노출된 소오스/드레인(35) 상에 선택적으로 성장시키고, 전도성을 가지도록 고농도의 불순물을 도핑한다. 여기서, 불순물의 도핑은 에피택셜 실리콘막(36)의 증착과 동시에 인-시츄(in-situ) 방식으로 수행할 수도 있다.In the DRAM fabrication process according to the present embodiment, first, as shown in FIG. 2A, a device isolation film 31 for electrical isolation between devices is formed on a silicon substrate 30, and then a gate oxide film (not shown), The gate electrode 32 and the mask insulating film 33 are formed. Subsequently, LDD ion implantation is performed, and an oxide film is deposited on the entire structure, and then the entire surface is etched to form a spacer insulating film 34 on the sidewall of the gate electrode 32. Subsequently, a high concentration of impurity ions are implanted to form a source / drain 35, and then a source / drain is exposed to protect the drain and subsequently expose the epitaxial silicon film 36 serving as a source / drain electrode. It is selectively grown on the drain 35 and doped with a high concentration of impurities to have conductivity. Here, the doping of the impurity may be performed in-situ at the same time as the deposition of the epitaxial silicon film 36.

다음으로, 도 2b에 도시된 바와 같이 전체 구조 상부에 비트라인 형성을 위한 전도막 및 절연막을 차례로 증착하고, 이를 차례로 선택 식각하여 비트라인(37) 및 그 상부의 마스크 절연막(38)을 형성한다. 이때, 비트라인(37)의 선폭은 적어도 이웃하는 접합부(드레인)와 오버랩 되지 않을 정도로 형성해야 한다. 여기서, 에피택셜 실리콘막(36)은 그 일부가 식각되면서 드레인을 보호하게 된다.Next, as illustrated in FIG. 2B, a conductive film and an insulating film for forming a bit line are sequentially deposited on the entire structure, and then selectively etched to form a bit line 37 and a mask insulating film 38 thereon. . At this time, the line width of the bit line 37 should be formed so that it does not overlap with at least a neighboring junction (drain). Here, the epitaxial silicon film 36 is partially etched to protect the drain.

계속하여, 도 2c에 도시된 바와 같이 이후 형성되는 전하저장 전극과의 단락을 방지하기 위하여 전체 구조 상부에 절연막을 증착하고 이를 전면 식각하여 비트라인(37)의 측벽을 덮는 스페이서 절연막(39)을 형성한다.Subsequently, as shown in FIG. 2C, an insulating film is deposited on the entire structure to prevent short-circuit with a subsequent charge storage electrode, and the entire surface is etched to form a spacer insulating film 39 covering the sidewall of the bit line 37. Form.

끝으로, 도 2d에 도시된 바와 같이 전체 구조 상부에 전하저장 전극 형성을 위한 전도막을 형성하고 이를 패터닝하여 전하저장 전극(40)을 형성한다.Finally, as illustrated in FIG. 2D, the conductive film for forming the charge storage electrode is formed on the entire structure and patterned to form the charge storage electrode 40.

상기와 같은 공정을 진행하는 경우, 비트라인과 전하저장 전극 형성시 층간절연막의 선택 식각에 의한 콘택홀 형성 공정을 배제함으로써 DRAM 등의 반도체 장치 제조 공정을 단순화하고 오정렬에 의한 단락 등의 소자 열화 현상을 방지할 수 있으며, 단차 측면에서도 종래기술에 비해 유리하여 후속 공정을 용이하게 진행할 수 있다. 한편, 에피택셜 실리콘막의 도입은 비트라인 패터닝시 소오스/드레인에 식각 손상이 유발되는 것을 방지하는 역할을 수행하여 누설전류를 감소시킨다.In the process described above, the process of forming a semiconductor device such as DRAM is simplified by eliminating the contact hole formation process by selective etching of the interlayer insulating layer when forming the bit line and the charge storage electrode, and deterioration of the device such as short circuit due to misalignment. It is possible to prevent, and even in terms of the step is advantageous compared to the prior art can easily proceed to the subsequent process. On the other hand, the introduction of the epitaxial silicon film serves to prevent the etching damage to the source / drain during bit line patterning to reduce the leakage current.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

이상에서 설명한 바와 같이 본 발명을 실시하면 비트라인 및 전하저장 전극 형성 공정이 종래기술에 비해 간단하면서도 보다 효율적으로 단락을 방지할 수 있으며, 전반적인 단차 감소에 의해 후속 공정을 보다 용이하게 실시할 수 있어 DRAM의 수율 향상을 기대할 수 있다. 또한, 본 발명은 소오스/드레인의 식각 손상을 근본적으로 방지하여 누설전류를 줄일 수 있는 효과가 있다.As described above, when the present invention is implemented, the process of forming the bit line and the charge storage electrode is simpler and more efficient than in the prior art, and short-circuit can be prevented more efficiently. DRAM yields are expected to improve. In addition, the present invention has the effect of reducing the leakage current by fundamentally preventing the etching damage of the source / drain.

Claims (1)

반도체 기판 상에 소오스/드레인, 게이트 절연막 및 그 상부와 측벽이 절연된 게이트 전극으로 구비한 모스 트랜지스터를 형성하는 제1 단계;Forming a MOS transistor including a source / drain, a gate insulating film, and a gate electrode having an upper sidewall and an insulated sidewall thereof on a semiconductor substrate; 상기 소오스/드레인 상에 선택적으로 전도성을 가진 에피택셜층을 성장시키는 제2 단계;Growing a selectively conductive epitaxial layer on the source / drain; 상기 제2 단계를 마친 전체 구조 상부에 비트라인용 전도막 및 절연막을 형성하는 제3 단계;A third step of forming a bit line conductive film and an insulating film on the entire structure after the second step; 상기 절연막 및 상기 비트라인용 전도막을 선택 식각하여 상기 에피택셜층에 콘택되는 비트라인을 형성하는 제4 단계;A fourth step of selectively etching the insulating film and the conductive film for the bit line to form a bit line contacting the epitaxial layer; 상기 비트라인의 측벽을 덮는 스페이서 절연막을 형성하는 제5 단계;Forming a spacer insulating layer covering sidewalls of the bit line; 상기 제5 단계를 마친 전체 구조 상부에 전하저장 전극용 전도막을 증착하는 제6 단계; 및A sixth step of depositing a conductive film for a charge storage electrode on the entire structure after the fifth step; And 상기 전하저장 전극용 전도막을 선택 식각하여 상기 에피택셜층에 콘택되는 전하저장 전극을 형성하는 제7 단계A seventh step of selectively etching the conductive film for the charge storage electrode to form a charge storage electrode contacting the epitaxial layer 를 포함하여 이루어진 디램 제조방법.DRAM manufacturing method comprising a.
KR1019970029687A 1997-06-30 1997-06-30 A method for fabricating dram device KR100265370B1 (en)

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JPH03188668A (en) * 1989-12-18 1991-08-16 Mitsubishi Electric Corp Semiconductor storage device

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JPH03188668A (en) * 1989-12-18 1991-08-16 Mitsubishi Electric Corp Semiconductor storage device

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