KR19990005489A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- KR19990005489A KR19990005489A KR1019970029687A KR19970029687A KR19990005489A KR 19990005489 A KR19990005489 A KR 19990005489A KR 1019970029687 A KR1019970029687 A KR 1019970029687A KR 19970029687 A KR19970029687 A KR 19970029687A KR 19990005489 A KR19990005489 A KR 19990005489A
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- bit line
- forming
- semiconductor device
- storage electrode
- charge storage
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 238000003860 storage Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 제조 분야에 관한 것임.Regarding the field of semiconductor manufacturing.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
본 발명은 반도체 장치의 고집적화에 수반되는 디자인 룰(design rule)의 감소에 따라 작은 면적에서 보다 효율적인 비트라인 및 전하저장전극을 형성하는 반도체 장치 제조방법을 제공하고자 함.The present invention is to provide a semiconductor device manufacturing method for forming a more efficient bit line and charge storage electrode in a small area in accordance with the reduction of design rules associated with high integration of the semiconductor device.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
본 발명은 게이트 전극 및 워드라인 상부 및 측벽을 절연함으로써 비트라인 및 전자저장전극 콘택홀 형성을 위한 선택적 식각 공정을 배제하고, 이로 인하여 오정렬을 방지하고, 전체적으로 단차를 감소시켜 후속 공정을 용이하게 함.The present invention eliminates the selective etching process for forming the bit line and electron storage electrode contact holes by insulating the gate electrode and the word line top and sidewalls, thereby preventing misalignment and reducing the step as a whole to facilitate subsequent processes. .
4. 발명의 중요한 용도4. Important uses of the invention
고집적 DRAM(Dynamic Random Access Memory) 제조에 이용됨.Used to manufacture highly integrated Dynamic Random Access Memory (DRAM).
Description
본 발명은 반도체 제조 분야에 관한 것으로, 특히 고집적 반도체 장치의 비트라인 및 전하저장 전극을 좁은 영역에서 보다 효율적으로 형성하는 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method for more efficiently forming bit lines and charge storage electrodes in a narrow region of a highly integrated semiconductor device.
반도체 장치의 고집적화에 수반되는 디자인 룰(design rule)의 감소에 따라 작은 면적에서 보다 효율적인 비트라인 및 전하저장전극을 형성하는 기술이 요구되고 있다.As the design rule accompanying high integration of semiconductor devices decreases, a technique for forming more efficient bit lines and charge storage electrodes in a small area is required.
첨부된 도면 도 1A 내지 도 1D는 종래 기술에 따른 반도체 장치 제조 공정도로써, 우선 도 1A에 도시된 바와 같이 실리콘 기판(10) 상에 소자 간의 전기적 격리를 위한 소자 분리막(11)을 형성한 후, 게이트 산화막(도시되지 않음), 게이트 전극(12) 및 마스크 절연막(13)을 형성한다. 계속하여, LDD(Lightly Doped Drain) 이온주입을 실시하고, 전체구조 상부에 산화막을 증착한 후 이를 전면성 식각하여 게이트 전극(12)의 측벽 부위에 스페이서 절연막(14)을 형성한다. 이어서, 고농도 불순물 이온주입을 실시하여 소오스/드레인(15)을 형성한다.1A to 1D are diagrams illustrating a manufacturing process of a semiconductor device according to the prior art. First, as shown in FIG. 1A, first, a device isolation layer 11 is formed on the silicon substrate 10 to electrically isolate devices. A gate oxide film (not shown), a gate electrode 12 and a mask insulating film 13 are formed. Subsequently, LDD (Lightly Doped Drain) ion implantation is performed, an oxide film is deposited on the entire structure, and the spacer insulating film 14 is formed on the sidewall of the gate electrode 12 by etching the entire surface. Subsequently, a high concentration of impurity ions are implanted to form the source / drain 15.
다음으로, 도 1B에 도시된 바와 같이 층간 절연막(16)을 형성한 후, 이를 선택적 식각하여 비트라인 콘택홀을 형성한다.Next, as shown in FIG. 1B, the interlayer insulating layer 16 is formed and then selectively etched to form bit line contact holes.
이어서, 도 1C에 도시된 바와 같이 전체구조 상부에 전도막 및 절연막을 증착하고, 이를 패터닝하여 비트라인(17) 및 마스크 절연막(18)을 형성한다. 계속하여, 전체구조 상부에 층간 절연막(19)을 형성한 후, 이를 선택적 식각하여 전하저장전극 콘택홀을 형성한다.Subsequently, as illustrated in FIG. 1C, a conductive film and an insulating film are deposited on the entire structure, and patterned to form a bit line 17 and a mask insulating film 18. Subsequently, an interlayer insulating film 19 is formed on the entire structure, and then selectively etched to form a charge storage electrode contact hole.
끝으로, 도 1D에 도시된 바와 같이 전체구조 상부에 전도막을 증착한 다음, 이를 패터닝하여 전하저장전극(20)을 형성한다.Finally, as illustrated in FIG. 1D, a conductive film is deposited on the entire structure, and then patterned to form the charge storage electrode 20.
상기와 같은 공정을 거치는 종래 기술에 따른 반도체 장치 제조 방법은 비트라인 및 전하저장전극을 콘택홀 식각 공정을 통해 하부층과 연결함으로써, 콘택홀 형성시 오정렬(misalign)에 의하여 워드라인(게이트 전극)의 스페이서 절연막이 식각되어 워드 라인과의 단락이 발생할 수 있는 문제점이 있다.In the semiconductor device manufacturing method according to the related art, the bit line and the charge storage electrode are connected to the lower layer through a contact hole etching process, thereby forming word holes (gate electrodes) by misalignment when forming contact holes. There is a problem in that the spacer insulating layer is etched to cause a short circuit with the word line.
이러한 오정렬에 의해 유발되는 문제점은 소자의 패일(fail)을 일으키는 요인이 되며, 이러한 문제점은 반도체 장치의 고집적화에 따라 더욱 심각하게 대두되고 있다.The problem caused by such misalignment is a factor causing a fail of the device, and this problem is more serious due to the high integration of semiconductor devices.
본 발명은 오정렬 등의 유발하는 비트라인 및 전하저장전극 콘택홀 공정을 배제하는 반도체 장치 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for fabricating a semiconductor device that eliminates bit line and charge storage electrode contact hole processes that cause misalignment and the like.
도 1A 내지 도 1D는 종래 기술에 따른 반도체 장치 제조 공정도.1A to 1D illustrate a semiconductor device manufacturing process in accordance with the prior art;
도 2A 내지 도 2D는 본 발명의 일실시예에 따른 반도체 장치 제조 공정도.2A to 2D illustrate a semiconductor device manufacturing process in accordance with an embodiment of the present invention.
도면의 주요부분에 대한 부호의 명칭Names of symbols on main parts of the drawings
30 : 실리콘 기판 31 : 소자분리막30: silicon substrate 31: device isolation film
32 : 게이트 전극(워드라인) 33, 38 : 마스크 절연막32: gate electrode (word line) 33, 38: mask insulating film
34, 39 : 스페이서 절연막 35 : 소오스/드레인34, 39: spacer insulating film 35: source / drain
36 : 에피택셜 실리콘층 37 : 비트라인36 epitaxial silicon layer 37 bit line
40 : 전하저장전극40: charge storage electrode
상기 목적을 달성하기 위하여 본 발명의 반도체 장치 제조방법은 반도체 기판 상에 소자 분리막, 소오스, 드레인, 게이트 절연막, 게이트 전극, 상기 게이트 전극 상부와 그 측벽 부위에 각각 제1 및 제2 절연막을 가지는 모스 트랜지스터를 형성하는 단계; 상기 소오스 및 드레인 상에 전도성을 가진 에피택셜층을 성장시키는 단계; 전체구조 상부에 제1 전도막 및 제3 절연막을 형성하는 단계; 상기 제3 절연막 및 제1 전도막을 선택적 식각하여 비트라인을 형성하는 단계; 전체구조 상부에 제4 절연막을 증착하고, 이를 전면성 식각하여 상기 비트라인의 측벽 부위를 절연하는 스페이서 절연막을 형성하는 단계; 및 전체구조 상부에 제2 전도막을 증착하고 이를 패터닝하여 전하저장전극을 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, a semiconductor device manufacturing method of the present invention includes a MOS having a first isolation layer, a source, a drain, a gate insulating layer, a gate electrode, a first insulating layer and a second insulating layer on the sidewalls of the gate electrode and the sidewalls of the gate electrode. Forming a transistor; Growing a conductive epitaxial layer on the source and drain; Forming a first conductive film and a third insulating film on the entire structure; Selectively etching the third insulating film and the first conductive film to form a bit line; Depositing a fourth insulating layer on the entire structure and etching the entire surface to form a spacer insulating layer which insulates sidewalls of the bit line; And depositing a second conductive layer on the entire structure and patterning the second conductive layer to form a charge storage electrode.
이하, 첨부된 도면 도 2A 내지 도 2D를 참조하여 본 발명의 일실시에를 상술한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings, FIGS. 2A to 2D.
먼저, 도 2A에 도시된 바와 같이 실리콘 기판(30) 상에 소자 간의 전기적 격리를 위한 소자 분리막(31)을 형성한 후, 게이트 산화막(도시되지 않음), 게이트 전극(32) 및 마스크 절연막(33)을 형성한다. 계속하여, LDD(Lightly Doped Drain) 이온주입을 실시하고, 전체구조 상부에 산화막을 증착한 후 이를 전면성 식각하여 게이트 전극(32)의 측벽 부위에 스페이서 절연막(34)을 형성한다. 이어서, 고농도 불순물 이온주입을 실시하여 소오스/드레인(35)을 형성한 다음, 이후의 비트라인 형성시 드레인을 보호하며, 소오스/드레인 전극 역할을 하는 에피택셜 실리콘막(36)을 성장시키고, 전도성을 가지도록 고농도의 불순물을 도핑시킨다. 여기서, 불순물의 도핑은 에피택셜 실리콘막(36)의 증착과 동시에 인-시츄(in-situ) 방식으로 수행할 수도 있다.First, as shown in FIG. 2A, the device isolation layer 31 is formed on the silicon substrate 30 to electrically isolate the devices. Then, the gate oxide film (not shown), the gate electrode 32, and the mask insulating film 33 are formed. ). Subsequently, LDD (Lightly Doped Drain) ion implantation is performed, and an oxide film is deposited on the entire structure, and then the entire surface is etched to form a spacer insulating film 34 on the sidewall of the gate electrode 32. Subsequently, a high concentration of impurity ions are implanted to form the source / drain 35, and then, the drain is protected during subsequent bit line formation, and the epitaxial silicon film 36 serving as the source / drain electrode is grown, and the conductive Doping a high concentration of impurities to have. Here, the doping of the impurity may be performed in-situ at the same time as the deposition of the epitaxial silicon film 36.
다음으로, 도 2B에 도시된 바와 같이 전체구조 상부에 비트라인 형성을 위한 전도막 및 절연막을 차례로 증착하고, 이를 차례로 선택적 식각하여 비트라인(37) 및 그 상부의 마스크 절연막(38)을 형성한다. 이때, 비트라인(37)의 선폭은 적어도 이웃하는 접합부(드레인)와 오버랩 되지 않을 정도로 형성해야 한다. 여기서, 에피택셜 실리콘막(36)은 그 일부가 식각되어지면서 드레인을 보호하게 된다.Next, as illustrated in FIG. 2B, a conductive film and an insulating film for forming a bit line are sequentially deposited on the entire structure, and then sequentially etched to form a bit line 37 and a mask insulating film 38 thereon. . At this time, the line width of the bit line 37 should be formed so that it does not overlap with at least a neighboring junction (drain). Here, the epitaxial silicon film 36 is partially etched to protect the drain.
계속하여, 도 2C에 도시된 바와 같이 이후 형성되는 전하저장전극과의 단락을 방지하기 위하여 전체구조 상부에 절연막을 증착하고 이를 선택적 식각함으로써 비트라인(37)의 측면에 스페이서 절연막(39)을 형성한다.Subsequently, as illustrated in FIG. 2C, a spacer insulating layer 39 is formed on the side of the bit line 37 by depositing an insulating layer over the entire structure and selectively etching the same to prevent short circuiting with the later formed charge storage electrode. do.
끝으로, 도 2D에 도시된 바와 같이 전체구조 상부에 전하저장전극 형성을 위한 전도막을 형성하고 이를 패터닝하여 전하저장전극(40)을 형성한다.Finally, as illustrated in FIG. 2D, the conductive film for forming the charge storage electrode is formed on the entire structure and patterned to form the charge storage electrode 40.
상기와 같은 일실시예에 나타난 바와 같이 본 발명은 비트라인과 전하저장전극 형성시 층간 절연막의 선택적 식각에 의한 콘택홀 형성 공정을 배제함으로써 DRAM 등의 반도체 장치 제조 공정을 단순화할 수 있으며, 단차 측변에서도 유리하여 후속 공정이 용이하게 된다.As shown in the above embodiment, the present invention can simplify the process of manufacturing a semiconductor device such as a DRAM by eliminating the contact hole forming process by the selective etching of the interlayer insulating layer when the bit line and the charge storage electrode are formed. It is also advantageous to facilitate the subsequent process.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
이상에서 설명한 바와 같이 본 발명을 실시하면 비트라인 및 전하저장전극 형성 공정이 종래의 기술에 비해 간단하면서도, 보다 효율적으로 단락을 방지할 수 있다. 또한, 전반적인 단차도 줄일 수 있어 후속 공정이 보다 용이하게 되어 고집적 반도체 장치의 제조시에 사용될 경우, 수율의 향상을 기대할 수 있다.As described above, when the present invention is implemented, the process of forming the bit line and the charge storage electrode is simpler than in the related art, and it is possible to prevent the short circuit more efficiently. In addition, the overall step can be reduced, so that subsequent processes become easier, and when used in the manufacture of highly integrated semiconductor devices, an improvement in yield can be expected.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970029687A KR100265370B1 (en) | 1997-06-30 | 1997-06-30 | A method for fabricating dram device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019970029687A KR100265370B1 (en) | 1997-06-30 | 1997-06-30 | A method for fabricating dram device |
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| KR19990005489A true KR19990005489A (en) | 1999-01-25 |
| KR100265370B1 KR100265370B1 (en) | 2000-10-02 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100323720B1 (en) * | 1999-12-31 | 2002-02-19 | 박종섭 | Elevated semiconductor layer and method for forming the same |
| KR100373354B1 (en) * | 2000-08-31 | 2003-02-25 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH03188668A (en) * | 1989-12-18 | 1991-08-16 | Mitsubishi Electric Corp | Semiconductor storage device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100323720B1 (en) * | 1999-12-31 | 2002-02-19 | 박종섭 | Elevated semiconductor layer and method for forming the same |
| KR100373354B1 (en) * | 2000-08-31 | 2003-02-25 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
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| KR100265370B1 (en) | 2000-10-02 |
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