KR100390891B1 - Method for manufacturing ic semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing an IC semiconductor device is provided to be capable of improving the design margin of a contact hole. CONSTITUTION: A plurality of gate electrodes(23) are formed on a semiconductor substrate(21). A source/drain region is formed in the substrate. The first contact hole is formed on the source/drain region by self-aligning. A bit line(28) is formed by depositing a polysilicon layer on the resultant structure. The second contact hole is formed not to be overlapped with the gate electrode by self-aligning. Then, a metal line is formed on the resultant structure.

Description

Manufacturing method of highly integrated semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated semiconductor device, and more particularly, to a method for manufacturing a highly integrated semiconductor device capable of manufacturing a more highly integrated semiconductor device by sufficiently securing a design margin of a contact hole.

Referring to the method of manufacturing a highly integrated semiconductor device according to the conventional method, as shown in FIG. 1, word lines 12 and 13 are formed on a semiconductor substrate 11, and bit lines 14 and source / drain regions are formed. A contact hole for connecting is formed.

As the semiconductor device is highly integrated, the gap between the word line 12 and the word line 13 is narrowed, and sufficient design margin for forming a contact hole connecting the source / drain region and the bit line 14 can be secured. In addition, the gap between the metal layer (17, 18) and the other conductive layer (15, 16) in the process of forming a contact hole for the interconnection of the bit line (14) and the metal layer (17, 18) There is a problem that can cause a short.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, the gate oxide film, the polysilicon, the first nitride film is sequentially formed on the semiconductor substrate and then the nitride film, polysilicon using a predetermined photolithography process After the gate oxide film is etched sequentially to form a gate electrode, a spacer is formed on sidewalls of the gate electrode, an interlayer insulating film and a second nitride film are sequentially formed on the entire structure, and then a self-aligned method. It is an object of the present invention to provide a method for manufacturing a highly integrated semiconductor device, which can be more integrated by forming contact holes with improved design margin by performing isotropic etching.

1 is a cross-sectional view of a highly integrated semiconductor device manufactured according to a conventional method.

2A and 2B are sectional views of the manufacturing process of the highly integrated semiconductor device according to the present invention;

(Code description of main parts of drawing)

21 semiconductor substrate 22 gate oxide film

23, 28, 30, 32: polysilicon 25: spacer

24, 27: nitride film

26, 29, 31, 33: interlayer insulating film

In order to achieve the above object, the present invention forms a gate oxide film, a first polysilicon, and a predetermined insulating film on a semiconductor substrate in which an active region and a field region are defined, and then performs a predetermined photolithography process for forming a gate electrode. Forming a gate electrode, forming a spacer on sidewalls of the low doping drain region and the gate electrode, forming a source / drain region, and then forming a first interlayer dielectric layer and a nitride layer on the entire structure; Forming a first contact hole by sequentially etching the nitride film and the first interlayer insulating film using a predetermined photolithography process for forming a junction with a source / drain region, and depositing a second polysilicon on the entire structure Defining a pattern of the second polysilicon by performing a predetermined photolithography process; a second interlayer insulating film and a third pole on the entire structure After forming silicon in order to define a pattern of the third polysilicon, and then forming a third interlayer insulating film and a fourth polysilicon on top of the entire structure, and then defining a pattern of the fourth polysilicon, and overall structure And forming a second contact hole for interconnection with the second polysilicon after forming a fourth interlayer insulating film thereon, and sequentially forming a metal barrier layer and a metal layer on the entire structure. .

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

For example, as shown in FIG. 2A, the gate oxide film 22, the first polysilicon film 23, and the first nitride film are formed on a semiconductor substrate 21 in which an active region and a field region are defined as shown in FIG. 2A. (24) are sequentially formed, and then the first nitride film 24, the first polysilicon 23, and the gate oxide film 22 are sequentially etched using a predetermined photolithography process for forming a gate electrode to form a gate electrode. do.

In this case, it is also possible to use an oxide film instead of the first nitride film 24, the thickness of the first nitride film or oxide film is preferably formed thick enough to perform the role of an etching barrier when forming a contact hole in a subsequent process. .

Next, a spacer 25 is formed on the sidewalls of the low doping drain region LDD and the gate electrode, and a source / drain region is formed, and then the first interlayer insulating layer 26 and the second nitride film ( 27) and isotropic etching using a predetermined photolithography process to form junctions with the source / drain regions, thereby sequentially etching the second nitride film 27 and the first interlayer insulating film 26 to form a first junction. A contact hole is formed.

In this case, etching is performed in a self-aligned manner in which a predetermined mask process is not required. The first nitride layer 24 on the second nitride layer 27 and the first polysilicon 23 is etched. It acts as a barrier to prevent the underlying layer from being etched.

Next, the second polysilicon 28 is deposited on the entire structure and a predetermined photolithography process is performed to define the pattern 28 of the second polysilicon to form a bit line.

Next, as shown in FIG. 2B, the second interlayer insulating layer 29 and the third polysilicon 30 are sequentially formed on the entire structure, and then the pattern 30 of the third polysilicon is defined, and the entire structure After the third interlayer insulating film 31 and the fourth polysilicon 32 are formed in this order, the pattern 32 of the fourth polysilicon is defined, and the fourth interlayer insulating film 33 is formed on the entire structure. And forming a second contact hole for interconnection with the second polysilicon 28 and forming a metal barrier layer 34 and a metal layer 35 on the entire structure.

As described above, according to the present invention, a self-aligned method can manufacture a contact hole having a small size that is difficult to form in a mask process, and the design margin between the bit line and the other conductive layer is sufficiently secured, so that the conductive layer It is possible to prevent the electrical defects of the semiconductor device due to the short of has the advantage that the integration and electrical properties of the semiconductor device can be stabilized.

On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (1)

Forming a plurality of gate electrodes on the semiconductor substrate; Forming a source / drain region by implanting impurities into the semiconductor substrate between the plurality of gate electrodes; Forming a first contact hole on the source / drain region in a self-aligned manner; Forming a bit line by applying polysilicon on top of the resultant product; Forming a second contact hole in a self-aligned manner on an upper portion of the bit line which does not overlap an upper portion of the gate electrode; And A method for manufacturing a highly integrated semiconductor device, characterized in that it comprises a step of forming a metal wiring on top of the resultant.