KR930007756B1 - Manufacturing method of self-alignment contact - Google Patents
Manufacturing method of self-alignment contact Download PDFInfo
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- KR930007756B1 KR930007756B1 KR1019900019045A KR900019045A KR930007756B1 KR 930007756 B1 KR930007756 B1 KR 930007756B1 KR 1019900019045 A KR1019900019045 A KR 1019900019045A KR 900019045 A KR900019045 A KR 900019045A KR 930007756 B1 KR930007756 B1 KR 930007756B1
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- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical group CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
내용없음.None.
Description
제1a도 내지 제1h도는 본 발명의 제1실시예에 의한 자기정렬된 콘택제조 단계를 도시한 단면도.1A to 1H are cross-sectional views illustrating a self-aligned contact manufacturing step according to a first embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판 2 : 필드산화막1: silicon substrate 2: field oxide film
3 : 게이트 산화막 4 : 게이트전극3: gate oxide film 4: gate electrode
5 : 절연층 6 : 스페이서 산화막5 insulating layer 6 spacer oxide film
7A : 드레인 7B : 소오스7A: Drain 7B: Source
8 : PSG층(또는 BPSG층) 9 : 제1포토레지스트 패턴8: PSG layer (or BPSG layer) 9: first photoresist pattern
10 : 콘택홀 11 : 제1도전층10 contact hole 11: first conductive layer
12 : 제2포토레지스트 패턴 13 : CVD 산화막 14 : 비트라인 콘택홀 15 : 비트라인12 second photoresist pattern 13 CVD oxide film 14 bit line contact hole 15 bit line
본 발명dms 고집적 반도체 소자의 자기정렬된(Self Aligned Contact) 제조방법에 관한 것으로, 특히, 소정물질층의 빠른 웨에치 비율(wet etch rate)을 이용하여 자기정렬된 콘택을 제조하는 방법에 관한 것이다.The present invention relates to a self-aligned manufacturing method of a dms highly integrated semiconductor device, and more particularly, to a method of manufacturing a self-aligned contact using a fast wet etch rate of a predetermined material layer. will be.
일반적으로 반도체 소자의 집적도가 높은 예를들어 16MDRAM 또는 64MDRAM급 소자에서는 종래의 방식과는 다른 셀면적이 축소된 셀구조가 요구되고 있다. 셀면적을 줄일 수 있는 방법은 액티브 영역을 축소하고, 게이트 선폭을 작게하거나 콘택면적을 작게 할 수가 있다. 따라서 콘텍면적을 작게하는 경우는 콘택저항이 매우증가하게 되는데 이것을 방지하기 위해서 동일한 콘택면적이 설계된 영역에 자기정렬된 콘택을 실시하여 가능한 콘택면적이 극대화되도록하는 제조방법이 연구되고 있다.In general, for example, a 16MDRAM or 64MDRAM class device having a high degree of integration of a semiconductor device requires a cell structure with a reduced cell area different from the conventional method. The method of reducing the cell area can reduce the active area, reduce the gate line width, or reduce the contact area. Therefore, in the case of reducing the contact area, the contact resistance is greatly increased. In order to prevent this, a manufacturing method for maximizing the possible contact area by applying self-aligned contacts to the designed area of the same contact area has been studied.
그러나, 이러한 자기정렬된 콘택 제조방법은 건식식각을 주로 이용함으로서 프로세서 제어에 어려움이 발생되며, 특히 고집적도를 가지며 단차가 큰 구조에서 건식식각으로 자기정렬된 콘택을 형서하는 기술은 포토레지스트 마스크 공정시 잘못 배열(Misalignment) 문제등으로 인하여 콘택되는 도전층의 단선 또는 단락등이 발생되는 문제점이 있다.However, such a self-aligned contact manufacturing method is difficult to control the processor by using dry etching mainly, and a technique of forming a self-aligned contact by dry etching in a structure having a high level of integration and a large step is a photoresist mask process. There is a problem in that disconnection or short circuit of the contacting conductive layer occurs due to misalignment.
따라서, 본 발명은 상기한 문제점을 해결하기 위해 콘택홀을 형성하는 단계에서 BPSG 또는 PSG층을 형성하고 빠른 웨에치 비율을 이용하여 소정의 BPSG 또는 PSG층을 제거하고 콘택홀을 형성하는 자기정렬된 콘택 제조방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problem, the present invention forms a BPSG or PSG layer in forming a contact hole, and removes a predetermined BPSG or PSG layer using a fast wet etch rate and forms a contact hole. It is an object of the present invention to provide a method for manufacturing a contact.
본 발명에 의하면 실리콘 기판 소정부분에 필드산화막 및 게이트 산화막을 형성한 다음, 게이트전극, 절연층, 스페이서 산화막, 소오스 및 드레인을 각각 형성하는 단계와, 전체적으로 PSG층을 예정된 두께로 형성한 다음, 소오스 상부에 콘택홀을 형성하기 위해 PSG층 상부에 제1포토레지스트 패턴을 형성하는 단계와, 상기 소오스 상부의 노출된 PSG층을 웨에치(Wet etch)로 제거한 다음, 상기 제1포토레지스트 패턴을 제거하고 노출된 소오스 및 남아있는 PSG층 상부 전체에 제1도전층을 형성하는 단계와, 상기 제1도전층을 패턴을 형성하기 위해 제1도전층 상부에 제2포토레지스트 패턴을 형성하고 건식식각으로 제1도전층 패턴을 형성한 다음, 그하부에 남아있는 PSG층을 웨에치로 모두 제거하는 단계로 이루어져 그로인하여 제1도전층이 소오스에 자기정렬된 콘택을 형성하는 것을 특징으로 한다.According to the present invention, a field oxide film and a gate oxide film are formed on a predetermined portion of a silicon substrate, followed by forming a gate electrode, an insulating layer, a spacer oxide film, a source, and a drain, respectively, and a PSG layer as a whole. Forming a first photoresist pattern on the PSG layer to form a contact hole thereon, removing the exposed PSG layer on the source with a wet etch, and then removing the first photoresist pattern. Removing and forming a first conductive layer over the exposed source and the remaining PSG layer, and forming a second photoresist pattern on the first conductive layer to dry-etch the first conductive layer. Forming a first conductive layer pattern, and then removing all of the PSG layer remaining in the lower portion thereof by using a wet-etched structure so that the first conductive layer is self-aligned to the source. Forming a contact.
이하, 첨부된 도면을 첨부하여 본 발명의 제1실시예를 상세히 설명하기로 한다.Hereinafter, the first embodiment of the present invention will be described in detail with reference to the accompanying drawings.
참고로 이하의 제1도 내지 제1h에서는 본 발명의 기술을 MOSFET의 소오스에 적용하여 자기정렬된 콘택 제종방법을 설명하였지만 반도체 소자의 또 다른 영역에 콘택을 형성하기 위해 적용할 수 있는 기술이다.For reference, in FIGS. 1 to 1h, the self-aligned contact termination method has been described by applying the technique of the present invention to a source of a MOSFET, but it is a technique that can be applied to form a contact in another region of a semiconductor device.
제1a도는 실리콘 기판(1) 소정부분에 필드산화막(2) 게이트 산화막(3)을 형성한 다음, 전체적으로 게이트 전극용 도전층(4A) 및 전연층(5)을 도포한 다음, 패턴공정으로 필드산화막(2) 및 게이트 산화막(3) 상부에 게이트 전극(4)을 형성한 상태의 단면도이다.FIG. 1A shows the formation of the field oxide film 2 and the gate oxide film 3 on a predetermined portion of the silicon substrate 1, followed by coating the conductive layer 4A and the leading edge layer 5 for the gate electrode as a whole. It is sectional drawing of the state in which the gate electrode 4 was formed in the oxide film 2 and the gate oxide film 3 upper part.
제1b도는 상기 게이트 전극(4) 및 절연층(5) 측벽에 스페이서 산화막(6)을 형성하고 이온주입 공정으로 실리콘기판(1)에 소오스(7A) 및 드레인(7B)을 형성한 상태의 단면도이다.FIG. 1B is a cross-sectional view of a spacer oxide film 6 formed on sidewalls of the gate electrode 4 and the insulating layer 5 and a source 7A and a drain 7B formed on the silicon substrate 1 by an ion implantation process. to be.
제1c도는 전체적으로 얇은 두께의 PSG층(8)(또는 BPSG층)을 침착하고 소오스(7A) 상부의 PSG층(8)을 제거하기 위해 제1포토레지스트 패턴(9)을 형성한 상태의 단면도이다. 여기에서 PSG의 Ph 농도는 0.1∼10중량%이며, BPSG의 B농도는 0.01∼8중량%이며 각각 두께는 100∼3000Å 정도이다.FIG. 1C is a cross-sectional view of a state in which the first photoresist pattern 9 is formed to deposit a PSG layer 8 (or BPSG layer) having a thin thickness as a whole and to remove the PSG layer 8 on the source 7A. . Here, the Ph concentration of PSG is 0.1 to 10% by weight, the B concentration of BPSG is 0.01 to 8% by weight and the thickness of each is about 100 to 3000 kPa.
제1d도는 상기 공정으로 노출된 PSG층(8)을 5 : 1∼150 : 1 HF용액 또는 5 : 1∼150 : 1 BOE 용액을 사용하여 웨에치로 제거하여 콘택홀(10)을 형성항 상태의 단면도이다.FIG. 1D is a diagram showing the formation of the contact hole 10 by removing the PSG layer 8 exposed by the above process by using a wet etching process using a 5: 1 to 150: 1 HF solution or a 5: 1 to 150: 1 BOE solution. It is a cross section of.
제1e도는 상기의 제1포토레지스트 패턴(9)을 제거한 다음 상기 PSG층(8)을 포함하는 전체 상부에 제1도전층(11) 예를들어 금속층, 폴리사이드 또는 폴리실리콘층을 형성한 다음, 제1도전층을 패턴시키기 위해 제2포토레지스트 패턴(12)을 형성한 상태의 단면도로서, 상기 제2포토레지스트 패턴(12)의 가장자리는 남아있는 상기 PSG층(8)과 겹치게 형성하여 제1도전층 패턴 형성시 상기 PSG층이 식각정치층으로 사용된다. 상기 폴리실리콘층의 형성방법은 인-시투도핑(In-Situ Doping) 또는 이온주입(Ion Implant)을 이용하여 도핑시킨다.In FIG. 1E, the first photoresist pattern 9 is removed, and then the first conductive layer 11, for example, a metal layer, a polyside, or a polysilicon layer is formed on the entire surface including the PSG layer 8. And a cross-sectional view of the second photoresist pattern 12 formed to pattern the first conductive layer, wherein an edge of the second photoresist pattern 12 overlaps the remaining PSG layer 8. When the conductive layer pattern is formed, the PSG layer is used as an etching layer. The method of forming the polysilicon layer is doped using In-Situ Doping or Ion Implant.
제1f도는 상기 공정으로 노출된 제1도전층(11)을 건식식각으로 남아있는 PSG층(8)을 웨에치로 제거한 상태의 단면도이다. 여기에서 제1도전층 패턴(11a)은 적층캐패시터의 전하보존전극으로 사용할 수 있다.FIG. 1F is a cross-sectional view of the PSG layer 8 in which dry etching is performed on the first conductive layer 11 exposed by the above process, by using a wet etching. The first conductive layer pattern 11a may be used as the charge storage electrode of the stacked capacitor.
제1g도는 상기 제2포토레지스트 패턴(8)을 제거한 다음, 전체적으로 CVD산화막(13)을 형성한 상태의 단면도이다.FIG. 1G is a cross-sectional view of the CVD oxide film 13 formed as a whole after the second photoresist pattern 8 is removed.
제1h도는 드레인(7B)상부의 CVD 산화막(7B)을 소정부분 제거하여 콘택홀(14)을 형성한 다음, 비트라인(15)을 드레인(7B)에 콘택한 상태의 단면도이다. 상기 CVD 산화막은 TEOS, LTO, MTO, HTO, BPSG, PSG 중에서 선택하거나, 서로 조합하여 사용한다.FIG. 1H is a cross-sectional view of a state in which the contact hole 14 is formed by removing a predetermined portion of the CVD oxide film 7B on the drain 7B, and then contacting the bit line 15 to the drain 7B. The CVD oxide film is selected from TEOS, LTO, MTO, HTO, BPSG, PSG, or used in combination with each other.
상기한 바와같이 본 발명은 PSG 또는 BPSG층의 바른 웨에치 비율을 이용하여 자기정렬콘택을 제조함으로서 고집적된 반도체 소자의 집적도를 향상시키고, 소자의 신뢰도를 향상시킬 수 있다.As described above, the present invention can improve the integration degree of highly integrated semiconductor devices and improve the reliability of the devices by fabricating self-aligned contacts using the correct weetch ratio of the PSG or BPSG layers.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900019045A KR930007756B1 (en) | 1990-11-23 | 1990-11-23 | Manufacturing method of self-alignment contact |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900019045A KR930007756B1 (en) | 1990-11-23 | 1990-11-23 | Manufacturing method of self-alignment contact |
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| Publication Number | Publication Date |
|---|---|
| KR920010838A KR920010838A (en) | 1992-06-27 |
| KR930007756B1 true KR930007756B1 (en) | 1993-08-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019900019045A KR930007756B1 (en) | 1990-11-23 | 1990-11-23 | Manufacturing method of self-alignment contact |
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| KR920010838A (en) | 1992-06-27 |
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