KR19980037651A - Pad of semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a semiconductor memory device, a pad, and a method of fabricating the same, which are suitable for solving etch damage and field butting problems that occur during the formation of bit line and node contacts of a semiconductor device. A substrate having a defined field region, a field insulating film formed on the field region, a gate electrode formed at regular intervals so as to be insulated on all sides of the active region, a source / drain region formed on the substrate on both sides of the exposed gate electrode, and a source / Storage of a capacitor formed on the selective tungsten formed to be in contact with the drain region, the first conductive layer formed on contact with the selective tungsten formed between the gate electrode, and the selective tungsten formed on the selective tungsten between the gate electrode and the field insulating layer in isolation from the first conductive layer; Nodes and dielectric films stacked on storage nodes And a plate node of the capacitor.

Description

Pad of semiconductor memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to pad formation, and more particularly, to a pad of a semiconductor memory device and a method for manufacturing the same, which are suitable for solving etch damage and field butting problems occurring during bit line and node contact formation of semiconductor devices. .

Hereinafter, a pad of a conventional semiconductor memory device and a method of manufacturing the same will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a pad of a conventional semiconductor memory device, and FIG. 2 is a cross-sectional view of a process of manufacturing a pad of a conventional semiconductor memory device.

First, as shown in FIG. 1, a pad of a conventional semiconductor memory device includes a field oxide film 2 in a field region on a substrate 1 on which a field region and an active region are defined, and a plurality of gates having a predetermined interval on the active region. An electrode 4, a gate oxide film 3 is formed on the substrate 1 below the gate electrode 4, a gate cap insulating film 5 is stacked on the gate electrode 4, and the gate electrode A gate sidewall insulating film 7 is formed on the side surface of (4).

A source / drain region 6 having a lightly doped drain (LDD) structure is formed in a predetermined region of the substrate 1 between the gate electrode 4 and the field oxide layer 2.

In addition, a polysilicon pad 10 is formed to contact the source / drain region 6 between the gate electrode 4 and the field oxide layer 2, and the polysilicon pad between the gate electrode 4 ( The first insulating layer 12 is formed to have a contact hole on 10, and the bit line 14 is formed to contact the polysilicon pad 10 between the gate electrodes 4 through the contact hole.

The first insulating layer 12 and the second insulating layer 16 having contact holes are stacked on the polysilicon pad 10 formed between the gate electrode 4 and the field oxide layer 2 to form the contact hole. The storage node 18 of the capacitor in contact with the polysilicon pad 10 is formed.

The dielectric layer 19 is formed on the storage node 18 of the capacitor, and the plate node 20 of the capacitor is formed on the dielectric layer 19.

Next, in the pad manufacturing method of the conventional semiconductor memory device, as shown in FIG. 2A, the field oxide film 2 is formed in the field region of the substrate 1 in which the field region and the active region are defined in a thermal process.

A first oxide film is deposited on the entire surface, and a polysilicon layer and a second oxide film are sequentially deposited on the first oxide film.

Subsequently, the photoresist film is applied to selectively pattern the photoresist film by an exposure and development process so that a predetermined portion remains.

Then, the second oxide film and the polysilicon layer are anisotropically etched sequentially using the patterned photoresist as a mask to form a plurality of gate electrodes 4 and gate cap insulating films 5 at predetermined portions.

After the third oxide film is deposited on the entire surface, gate sidewall insulating films 7 are formed on both sides of the gate electrode 4 at anisotropic perspective. A source / drain region 6 having a lightly doped drain (LDD) structure is formed on the substrates 1 on both sides of the gate electrode 4.

Subsequently, as illustrated in FIG. 2B, the first insulating film 8 is deposited on the entire surface, the photosensitive film 9 is applied, and the photosensitive film 9 is selectively patterned by an exposure and development process.

The first insulating layer 8 is etched using the patterned photoresist 9 as a mask to expose the source / drain regions 6.

After removing the photoresist film 9 as shown in FIG. 2C, polysilicon is deposited on the entire surface, and the photoresist film 9 is coated on the polysilicon.

After the photoresist 9 is selectively patterned by an exposure and development process, the polysilicon pad 10 is formed to contact the source / drain region 6 using the patterned photoresist 9 as a mask.

Next, as shown in FIG. 2D, a fourth oxide film is deposited on the entire surface to form a first interlayer insulating film 12, and a photosensitive film 13 is coated on the entire surface to selectively pattern a predetermined portion by an exposure and development process.

Subsequently, the first interlayer insulating layer 12 is etched using the patterned photoresist layer 13 as a mask to form a contact hole in a predetermined portion on the polysilicon pad 10 between the gate electrodes 4.

Next, as shown in FIG. 2E, after removing the photoresist layer 13, polysilicon is deposited on the entire surface, and the photoresist layer 15 is applied to selectively pattern the photoresist layer by an exposure and development process. Instead of polysilicon, aluminum or tungsten may be deposited.

The silicon film is etched using the patterned photosensitive film 15 as a mask to form a bit line 14 in the contact hole.

As shown in FIG. 2F, the photosensitive film 15 is removed and an oxide film is deposited on the entire surface to form a second interlayer insulating film 16.

Then, the photosensitive film 17 is coated on the entire surface to remove a predetermined portion by an exposure and development process. Thereafter, the second interlayer insulating film 16 is etched using the removed photoresist as a mask to form a contact hole on the polysilicon pad 10 between the gate electrode 4 and the field oxide film 2.

Next, as illustrated in FIG. 2G, a conductive polysilicon or metal layer is deposited on the front surface and then selectively patterned to form the storage node 18 of the capacitor in the contact hole.

An oxide film is deposited on the entire surface, and a conductive polysilicon or metal layer is deposited on the oxide film, and then patterned to form a dielectric layer 19 and a plate node 20 of the capacitor on the storage node 18 of the capacitor. .

Through this process, the conventional semiconductor memory device and the pad forming process are completed.

Conventional pads of semiconductor memory devices and manufacturing methods thereof have the following problems.

First, at least two photolithography processes are required to form bit line contacts and node contact pads of a semiconductor memory device.

In both cases, the higher the integration device, the less contact margin in the process of forming the pad, so that misalignment may be formed, and thus, the substrate and the etching damage may be easily caused, and the field booting problem of the contact may occur.

SUMMARY OF THE INVENTION The present invention provides a pad of a semiconductor memory device and a method of manufacturing the same, which are designed to solve the problems as described above, which can simplify the process, solve the etching damage, secure the contact margin, and solve the booting of the contact. There is a purpose.

1 is a cross-sectional view of a pad of a conventional semiconductor memory device

2A to 2G are cross-sectional views illustrating a method for manufacturing a pad of a conventional semiconductor memory device.

3 is a cross-sectional view of a pad of the semiconductor memory device of the present invention.

4A through 4F are cross-sectional views illustrating a method for manufacturing a pad of a semiconductor memory device according to the present invention.

Explanation of symbols on the main parts of the drawings

30: fin 31: field oxide film

32: gate oxide film 33: gate electrode

34: gate cap insulating film 35: low concentration source / drain region

36: gate sidewall insulating film 37: high concentration source / drain region

38: selective tungsten 39: first insulating film

40, 42, 44: Photosensitive film 41: Bit line

43: second insulating film 45: storage degree

46: dielectric film 47: plate node

The pad of the semiconductor memory device of the present invention for achieving the above object is formed with a substrate having an active region and a field region defined, a field insulating film on the field region, a predetermined interval so as to be insulated on all sides on the active region A gate electrode, a source / drain region formed on substrates on both sides of the exposed gate electrode, a selective tungsten formed in contact with the source / drain region, and a first conductive layer formed in contact with the selective tungsten formed between the gate electrode; And a storage node of a capacitor which is isolated from the first conductive layer and is in contact with the selective tungsten between the gate electrode and the field insulating film, and a dielectric layer and a plate node of the capacitor which are stacked on the storage node. It is characterized by.

In addition, the method for manufacturing a pad of the semiconductor memory device of the present invention configured as described above includes the steps of defining a field region and an active region on a substrate, forming a field oxide film between the field regions, and forming a predetermined interval on the active region. Forming a plurality of gate electrodes insulated in all directions, forming a source / drain region on both sides of the gate electrode, forming a selective tungsten in contact with the source / drain region, and forming the gate electrode Forming a first conductive layer in contact with the selective tungsten between; forming a storage node of a capacitor in contact with the selective tungsten between the field insulating film and the gate electrode so as to be isolated from the first conductive layer; On the storage node of the capacitor, the dielectric film of the capacitor and the capacitor It is characterized by forming a plate node laminated.

Hereinafter, a pad and a method of manufacturing the semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

3 is a cross-sectional view illustrating a pad of a semiconductor memory device of the present invention, and FIGS. 4A to 4F are cross-sectional views illustrating a method of manufacturing a pad of the semiconductor memory device of the present invention.

First, as shown in FIG. 3, the pad of the semiconductor memory device of the present invention includes a substrate 30 in which an active region and a field region are defined, and a field oxide layer 31 is formed on the field region.

In addition, a plurality of gate electrodes 33 are formed on the active region of the substrate 30 at predetermined intervals, and a gate oxide layer 32 is formed on the substrate 30 below the gate electrode 33. A gate cap insulating film 34 is stacked on the 33, and a gate sidewall insulating film 36 is formed on the side of the gate electrode 33.

In the predetermined region in the substrate 30 between the gate electrode 33 and the field oxide layer 31, the low concentration source / drain region 35 and the high concentration source / drain region 37 have LDD (Lightly Doped Drain) structures. Formed.

A selective tungsten 38 is formed on the substrate 30 between the gate electrode 33 and the field oxide layer 31 to have a height parallel to the gate cap insulating layer 34. A first interlayer insulating film 39 is formed to have a contact hole on the selective tungsten 38 between the 33 and the bit line 41 to contact the selective tungsten 38 between the gate electrode 33 through the contact hole. Is formed.

In addition, a first interlayer insulating layer 39 and a second interlayer insulating layer 43 are formed to have a contact hole on the selective tungsten 38 formed on the gate electrode 33 and the field oxide layer 31. The storage node 45 of the capacitor was formed in contact with the selective tungsten 38.

A capacitor dielectric layer 46 is formed on the storage node 45 of the capacitor, and a plate node 47 of the capacitor is formed on the dielectric layer 46.

Referring to the method of manufacturing the pad of the semiconductor memory device of the present invention configured as described above, as shown in FIG. 4A, the pad oxide film and the nitride film are deposited on the substrate 30 in sequence, and the photoresist film is coated on the nitride film. Alternatively, the photoresist was patterned to remove the nitride film and the oxide film in sequence using the patterned photoresist as a mask (not shown in the drawing).

The photoresist layer is removed after the field oxide layer 31 is formed through the thermal oxidation process.

The oxide film is deposited on the entire surface by thermal oxidation or chemical vapor deposition.

Subsequently, after depositing the doped polycrystalline silicon layer on the front surface, a silicon oxide film is deposited on the polycrystalline silicon layer by chemical vapor deposition. In place of the doped polycrystalline silicon layer, amorphous silicon may be deposited.

Subsequently, the photoresist film is coated to selectively pattern the photoresist film by an exposure and development process leaving only a predetermined portion.

Then, the silicon oxide film and the polycrystalline silicon layer are anisotropically etched sequentially using the patterned photoresist as a mask to form a plurality of gate electrodes 33 and gate cap insulating films 34 at predetermined portions. The gate cap insulating film 34 may be formed of a nitride film instead of the silicon oxide film.

When the substrate 30 is later revealed to be P-type, phosphorus ions are implanted to form a low concentration source / drain region 35.

In this case, when the substrate is N-type, boron is ion implanted.

The silicon oxide film is deposited on the entire surface by thermal oxidation or chemical vapor deposition, and then anisotropically etched to form gate sidewall insulating films 36 on both sides of the gate electrode 33 and the gate cap insulating film 34. The gate sidewall insulating film 36 may be formed of a nitride film instead of the silicon oxide film.

In addition, a high concentration source / drain region 37 is formed by implanting ions (As +) ions into the gate electrode 33 and the substrate 40 on both sides of the gate sidewall insulating layer 36.

Next, a selective tungsten 38 is formed on the exposed substrate 30 as shown in FIG. 4B to have a height parallel to the gate cap insulating film 34.

As shown in FIG. 4C, an oxide film is deposited on the entire surface by chemical vapor deposition to form a first interlayer insulating film 39.

Then, the photoresist film 40 is coated on the first interlayer insulating film to selectively pattern the photoresist film by an exposure and development process.

The first interlayer insulating layer 39 is etched using the patterned photoresist 40 as a mask to form contact holes on the selective tungsten 38 between the gate electrodes 33.

Next, as shown in FIG. 4D, the photosensitive film 40 is removed, and a conductive material such as silicon, aluminum, and tungsten is deposited on the front surface, and then the photosensitive film 42 is coated on the front surface.

Then, a predetermined portion of the photosensitive film 42 is selectively patterned by exposure and development processes.

The conductive material is etched using the patterned photoresist as a mask to form a bit line 41 between the gate electrodes 33.

Subsequently, as shown in FIG. 4E, the photosensitive film 42 is removed and an oxide film or a nitride film is deposited on the entire surface by chemical vapor deposition to form a second interlayer insulating film 43.

Then, a photosensitive film is coated on the second interlayer insulating film 43 to be selectively patterned by an exposure and development process.

Subsequently, the first interlayer insulating layer 39 and the second interlayer insulating layer 43 are anisotropically etched using the patterned photoresist as a mask to form a selective tungsten 38 between the gate electrode 33 and the field oxide layer 31. A node contact hole is formed to be exposed.

Next, as illustrated in FIG. 4F, a conductive polysilicon or metal layer is deposited on the front surface, and then selectively patterned to form the storage node 45 of the capacitor in the contact hole.

The dielectric layer 46 and the plate node 47 are formed on the storage node 45 by depositing an oxide layer on the entire surface and depositing a patterned conductive silicon or metal layer on the oxide layer. Through this process, the pad manufacturing process of the semiconductor memory device according to the present invention is completed.

The pad of the semiconductor memory device of the present invention as described above and a method of manufacturing the same have the following effects.

First, the selective tungsten formed on the substrate is connected to the node contact and the bit line contact wiring, thereby solving the problem of etching damage to the substrate and field booting of the contacts generated when the contact wiring is formed.

Second, since the pad of the memory device is formed of the selective tungsten, the process staff can be reduced to improve the yield.

Claims (9)

A substrate in which the active area and the field area are defined, A field insulating film on the field region, A gate electrode formed to have a predetermined interval so as to be insulated on the active region in all directions; Source / drain regions formed in the substrate on both sides of the exposed gate electrode; A selective tungsten formed in contact with the source / drain region, A first conductive layer in contact with the selective tungsten between the gate electrode; A storage node of a capacitor which is isolated from the first conductive layer and formed in contact with the selective tungsten between the gate electrode and the field insulating film; And a plate node of a capacitor and a dielectric layer stacked on the storage node. The pad of claim 1, wherein the gate electrode is insulated from the gate cap insulating layer on the upper side and the gate sidewall insulating layer on the lower side of the gate electrode. 3. The pad of claim 1, wherein the selective tungsten region is formed to have the same height as that of the gate cap insulating layer. The pad of claim 1, wherein the first conductive layer serves as a bit line. Defining a field region and an active region on the substrate; Forming a field oxide film on the field region; Forming a plurality of gate electrodes insulated from all directions to have a predetermined distance on the active region; Forming source / drain regions on both sides of the gate electrode; Forming selective tungsten to be in contact with the source / drain region; Forming a first conductive layer in contact with the selective tungsten between the gate electrodes; Forming a storage node of a capacitor to be in contact with the selective tungsten between the field insulating film and the gate electrode so as to be isolated from the first conductive layer; And forming a dielectric layer of the capacitor and a plate node of the capacitor on the storage node of the capacitor. The method of claim 5, wherein the insulating layer remaining on the active region is completely removed before the selective tungsten is formed to expose the source / drain regions. 6. The method of claim 5, wherein a gate cap insulating film is formed on the gate electrode, and gate sidewall insulating films are formed on both sides of the gate electrode to insulate the gate cap insulating film. The method of claim 5, wherein the gate cap insulating film and the gate sidewall insulating film are formed of an oxide film or a nitride film. The method of claim 5, wherein the first conductive layer is formed of a conductive polysilicon or metal layer and used as a bit line.