KR100249157B1 - Method for fabricating of semiconductor device - Google Patents

Abstract

The present invention has been made to solve the above problems, and relates to a method of manufacturing a semiconductor device for preventing the double pin phenomenon and pin break phenomenon and to increase the capacity of the capacitor.

A method of manufacturing a semiconductor device of the present invention includes the steps of forming a gate insulating film on a substrate, forming a gate electrode having a cap gate insulating film and an insulating film sidewall on the gate insulating film, and forming impurity regions in the substrate surfaces on both sides of the gate electrode. Forming a storage node contact hole by patterning the first, second, and third insulating films in order on the front surface including the gate electrode, and patterning the first, second, and third insulating films; Forming a layer and a fourth insulating film, patterning the fourth insulating film so as to be removed only above the storage contact hole, forming a second conductive layer and a fifth insulating film on the entire surface, and forming the first and second conductive layers and the fourth insulating film. Patterning the fifth insulating film and removing the third, fourth and fifth insulating films to form a storage node, forming a dielectric film on the surface of the storage node and dielectric The film is characterized by the yirueojim and forming a plate electrode.

Description

Method for fabricating a semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for increasing the capacity of a capacitor.

Hereinafter, a method of manufacturing a semiconductor device will be described with reference to the accompanying drawings.

1A to 1G are cross-sectional views illustrating a method of manufacturing a pin capacitor according to the prior art.

The fin capacitor according to the prior art forms an initial oxide film, a first nitride film, and a first photoresist film sequentially on a semiconductor substrate 11 having a p-type and defined active region and isolation region, as shown in FIG. 1A. After selectively exposing and developing the first photoresist film so as to be removed only above the isolation region, the first nitride film and the initial oxide film are selectively etched using the selectively exposed and developed first photoresist film as a mask, and the first photoresist film is selectively removed. The photoresist film is removed. Then, heat is applied to the entire surface using the first nitride film as a mask to form a field oxide film 12 in the isolation region, and then the first nitride film and the initial oxide film are removed.

As shown in FIG. 1B, a gate oxide layer 13 is formed by thermally oxidizing the semiconductor substrate 11, and then a first polycrystalline silicon, a first oxide layer, and a second photosensitive layer are sequentially formed on the entire surface, and the second photosensitive layer is formed. After selectively exposing and developing only the portion where the gate is to be formed, the first oxide film and the first polycrystalline silicon are etched using the selectively exposed and developed second photosensitive film as a mask, thereby capping the gate oxide film 14 and the gate. An electrode 15 is formed and the second photosensitive film is removed.

Subsequently, n-type impurity ions are implanted and drive-in diffused on the entire surface by using the gate electrode 15 as a mask to form the impurity region 16 in the semiconductor substrate 11 on both sides of the gate electrode 15.

A first nitride film is deposited on the entire surface including the cap gate oxide film 14 and etched back to form first nitride film sidewalls 17 on both sides of the cap gate oxide film 14 and the gate electrode 15.

As shown in FIG. 1C, a second oxide film 18, a second nitride film 19, a third oxide film 20, and a third photosensitive film 21 are sequentially formed on the entire surface including the cap gate oxide film 14.

And selectively exposing and developing the third photoresist layer 21 to remove only a portion where a storage node contact hole of a capacitor is to be formed, and then using the selectively exposed and developed third photoresist layer 21 as a mask. A contact hole is formed by selectively etching the oxide film 13, the third oxide film 20, the second nitride film 19, and the second oxide film 18.

As shown in FIG. 1D, after removing the third photoresist film 21, the first polycrystalline silicon 22, the fourth oxide film 23, and the fourth photoresist film 24 are disposed on the entire surface including the third oxide film 20. The fourth photoresist layer 24 is sequentially formed, and the fourth photoresist layer 24 is selectively exposed and developed to remove only a portion where a storage node via hole of a capacitor is to be formed above the contact hole. The via hole is formed by selectively etching the fourth oxide layer 23 using the mask as a mask.

As shown in FIG. 1E, after the fourth photoresist layer 24 is removed, the second polycrystalline silicon 25 and the fifth photoresist layer 26 are sequentially formed on the entire surface including the fourth oxide layer 23. 5 is selectively exposed and developed so that the photoresist layer 26 remains only at the site where the storage node is to be formed.

As shown in FIG. 1F, the second polycrystalline silicon 25, the fourth oxide film 23, and the first polycrystalline silicon 22 are selectively selected using the selectively exposed and developed fifth photosensitive film 26 as a mask. Etch it. Here, the second polycrystalline silicon 25 and the fourth oxide film 23 are etched by using the fifth photosensitive film 26 as a mask, and both ends of the fifth photosensitive film 26 are formed with the second polycrystalline silicon 25. Etching is performed at the etching selectivity of the fourth oxide film 23. For this reason, the second polycrystalline silicon 25 is etched more than the first polycrystalline silicon 22 so that the length of the first polycrystalline silicon 22 is longer than the length of the second polycrystalline silicon 25.

Subsequently, after the fifth photoresist layer 26 is removed, the etched fourth oxide layer 23 and the third oxide layer 20 are removed by wet etching to form a storage node electrode of the capacitor.

As shown in FIG. 1G, a dielectric film 27 is formed on the storage node electrode surface, and a plate electrode of the third polycrystalline silicon 28 is formed on the dielectric film 27.

In the conventional method of manufacturing a semiconductor device, when the upper polycrystalline silicon and the oxide film are etched in the storage node manufacturing process of the pin capacitor, both ends of the photoresist film are etched at a select ratio with the upper polycrystalline silicon or the oxide film. The polycrystalline silicon was etched again, resulting in a double fin phenomenon in which the upper portion was shorter than the lower portion, and a pin crack phenomenon in which the lower polycrystalline silicon was broken during the subsequent process, and the capacity of the capacitor was insufficient.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device which prevents double pin phenomenon and pin crack phenomenon and increases the capacity of a capacitor.

1A to 1G are cross-sectional views illustrating a method of manufacturing a pin capacitor according to the prior art.

2A to 2G are cross-sectional views illustrating a method of manufacturing a pin capacitor according to an exemplary embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 field oxide film

33: gate oxide film 34: cap gate oxide film

35: gate electrode 36: impurity region

37: first nitride film sidewall 38: second oxide film

39: second nitride film 40: third oxide film

42: first polycrystalline silicon 43: fourth oxide film

45: second polycrystalline silicon 46: fifth oxide film

48: dielectric film 49: third polycrystalline silicon

A method of manufacturing a semiconductor device of the present invention comprises the steps of forming a gate insulating film on a substrate, forming a gate electrode having a cap gate insulating film and an insulating film sidewall on the gate insulating film, impurity regions in the substrate surface on both sides of the gate electrode Forming a first, second and third insulating films on the front surface including the gate electrode, and forming a storage node contact hole by patterning the first, second and third insulating films Forming a first conductive layer and a fourth insulating layer on the substrate; patterning the fourth insulating layer to be removed only on the upper side of the storage contact hole; forming a second conductive layer and a fifth insulating layer on the front surface; Patterning the second conductive layer and the fourth and fifth insulating layers and removing the third, fourth and fifth insulating layers to form a storage node, the storage node surface And forming a plate electrode on the dielectric film.

When described in detail with reference to the accompanying drawings a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention as follows.

2A to 2G are cross-sectional views illustrating a method of manufacturing a pin capacitor according to an exemplary embodiment of the present invention.

In the pin capacitor according to the embodiment of the present invention, as shown in FIG. 2A, an initial oxide film, a first nitride film, and a first photoresist film are sequentially formed on the semiconductor substrate 31 having a p-type, active region and defined isolation region. After selectively exposing and developing the first photoresist film so as to be removed only above the isolation region, the first nitride film and the initial oxide film are selectively etched using the selectively exposed and developed first photoresist film as a mask, and the first photoresist film is selectively removed. The photoresist film is removed. Then, heat is applied to the entire surface using the first nitride film as a mask to form a field oxide film 32 in the isolation region, and then the first nitride film and the initial oxide film are removed.

As shown in FIG. 2B, the semiconductor substrate 31 is thermally oxidized to form a gate oxide film 33, and then a first polycrystalline silicon, a first oxide film, and a second photosensitive film are sequentially formed on the entire surface, and the second photosensitive film is formed. After selectively exposing and developing so that only the portion where the gate is to be formed remains, the first oxide film and the first polycrystalline silicon are etched using the selectively exposed and developed second photosensitive film as a mask, thereby capping the gate oxide film 34 and the gate. An electrode 35 is formed and the second photosensitive film is removed.

Subsequently, n-type impurity ions are implanted and drive-in diffused on the entire surface using the gate electrode 35 as a mask to form the impurity region 36 in the semiconductor substrate 31 on both sides of the gate electrode 35.

A first nitride film is deposited on the entire surface including the cap gate oxide film 34 and etched back to form first nitride film sidewalls 37 on both sides of the cap gate oxide film 34 and the gate electrode 35.

As shown in FIG. 2C, a second oxide film 38, a second nitride film 39, a third oxide film 40, and a third photosensitive film 41 are sequentially formed on the entire surface including the cap gate oxide film 34.

And selectively exposing and developing the third photoresist layer 41 to remove only a portion where a storage node contact hole of a capacitor is to be formed, and then using the selectively exposed and developed third photoresist layer 41 as a mask. A contact hole is formed by selectively etching the oxide film 33, the third oxide film 40, the second nitride film 39, and the second oxide film 38.

As shown in FIG. 2D, after the third photosensitive film 41 is removed, the first polycrystalline silicon 42, the fourth oxide film 43, and the fourth photosensitive film 44 are disposed on the entire surface including the third oxide film 40. The fourth photoresist layer 44 is sequentially formed, and the fourth photoresist layer 44 is selectively exposed and developed to remove only a portion where a storage node via hole of a capacitor is to be formed above the contact hole. The via hole is formed by selectively etching the fourth oxide layer 43 using the mask as a mask.

As shown in FIG. 2E, after the fourth photosensitive film 44 is removed, the second polycrystalline silicon 45, the fifth oxide film 46, and the fifth photosensitive film 47 are disposed on the entire surface including the fourth oxide film 43. After sequentially forming, the fifth photoresist layer 47 is selectively exposed and developed so that only the portion where the storage node is to be formed remains. The fifth oxide film 46 is three to five times thicker than the fourth oxide film 43.

As shown in FIG. 2F, the fifth oxide film 46, the second polycrystalline silicon 45, the fourth oxide film 43 and the first polycrystal are formed by using the selectively exposed and developed fifth photosensitive film 47 as a mask. The silicon 42 is selectively etched. Here, in the etching process of the fifth oxide film 46 and the second polycrystalline silicon 45 by using the fifth photosensitive film 47 as a mask, both ends of the fifth photosensitive film 47 may be formed of the fifth oxide film 46 and the fifth film. It is etched by the etching selectivity of 2 polycrystalline silicon 45. However, as the mask of the fifth oxide layer 46, the second polycrystalline silicon 45 and the first polycrystalline silicon 42 are etched by the same etching amount, so that the length of the first polycrystalline silicon 42 and the second polycrystalline silicon are etched. The length of 45 becomes equal.

Subsequently, the fifth photoresist layer 47 is removed, and then the etched fifth and fourth oxide layers 46 and 43 and the third oxide layer 40 are removed by wet etching to form storage node electrodes of the capacitor.

As shown in FIG. 2G, the dielectric film 48 is formed on the storage node electrode surface, and the plate electrode of the third polycrystalline silicon 49 is formed on the dielectric film 47.

In the method of manufacturing a semiconductor device of the present invention, a pin oxide and pin cracking phenomenon are formed by masking the upper polycrystalline silicon even when both ends of the photoresist layer are etched by forming a thick oxide film on the upper polycrystalline silicon in the storage node manufacturing process of the pin capacitor. It is effective in preventing and increasing the capacity of the capacitor.

Claims (1)

Forming cell transistors having impurity regions in the gate electrode and on both substrate surfaces thereof, on the semiconductor substrate; Forming an interlayer insulating layer including first, second, and third insulating films on the entire surface, and forming contact holes to expose one side impurity region of the cell transistor; Forming a first conductive layer and a fourth insulating layer on the entire surface; Patterning the fourth insulating layer to be removed only above the storage contact hole; Forming a second conductive layer on the entire surface and forming a fifth insulating layer on the second conductive layer to a thickness of 3 to 5 times thicker than the fourth insulating layer; Patterning the first, second conductive layers and the fourth and fifth insulating layers and removing the third, fourth and fifth insulating layers to form a storage node; And forming a dielectric film and a plate electrode on the surface of the storage node.

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