JPH1126756A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide reliable manufacturing steps for a MOS transistor having a small variation where a photolithography step is reduced and a shortage between a gate electrode and a source/drain is prevented. SOLUTION: A thermal oxide film 2 and a silicon nitride film 3 are formed on a silicon substrate 1, a part of a field region of the silicon substrate 1 is made etching and after that a filed oxide film 4 is formed. Next a silicon oxide film 5 is formed and after that an SOG film is applied. Next the silicon oxide film 3 and a pad oxide film 2 on an active region are eliminated and after that polycrystalline silicon 7 is piled to make etching-back. Next the polysilicon 7 in a gate electrode forming region is eliminated and after that the oxide film on the field region is eliminated. Next a sidewall 8 is formed and after that a gate oxide film 9 is formed. After that a polycrystalline silicon 10 is piled and the polycrystalline silicon 10 of the gate electrode and polycrystalline silicon 7 on a source/drain region are separated by making etching-back.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a MOS transistor having a fine structure.

[0002]

2. Description of the Related Art In recent years, with the increasing integration of LSIs, transistors used have been increasingly miniaturized.
A transistor having a gate length of 0.2 to 0.3 μm has been required. For this reason, the precision required for photolithography for performing fine processing is becoming increasingly severe. There is also a method of preparing an exposure apparatus using light having a short wavelength or an electron beam, but it is expensive, and a technique for forming a fine pattern exceeding the limit using a conventional exposure apparatus has been proposed. As an example, a manufacturing method disclosed in Japanese Patent Application Laid-Open No. 5-235024 will be described with reference to FIG.

First, as shown in FIG. 7A, a field oxide film 22 is formed on a P-type silicon substrate 21 by a LOCOS method, and then a silicon nitride film 3 is deposited by a CVD method. Next, a window (X) is opened in the silicon nitride film 23 by photolithography. Thereafter, a silicon oxide film 24 is deposited by a CVD method.

Next, the silicon oxide film 2 is formed by RIE.
4 is anisotropically etched to form side walls 25 on the side walls of the silicon nitride film 23 as shown in FIG.

Next, the gate oxide film 26 is formed by a thermal oxidation method.
To form Thereafter, polycrystalline silicon 27 containing a dopant such as phosphorus is deposited on the entire surface by CVD.

Thereafter, as shown in FIG. 7C, a gate electrode 28 is formed by photolithography, and thereafter, the silicon nitride film 23 and the sidewall 25 are removed by etching. Next, silicon oxide films 29 and 30 are formed on the entire surface by a thermal oxidation method. At this time, the silicon oxide film 29 on the surface of the gate electrode 28 becomes thicker than the oxide film 30 on the substrate surface due to the accelerated oxidation of polycrystalline silicon.

Next, the silicon oxide film 30 on the surface of the P-type silicon substrate 21 is removed by etching. Further FIG.
As shown in FIG. 1D, polycrystalline silicon 32 containing a dopant such as phosphorus is deposited on the entire surface. Thereafter, heat treatment is performed in nitrogen to form the activation layer 31 by solid phase diffusion. Thereafter, the polycrystalline silicon 32 is patterned by photolithography to form wiring electrodes,
Obtain an S-type transistor.

[0008]

However, according to the above-mentioned conventional manufacturing method, the LOC is required until the gate electrode is formed.
It is necessary to perform patterning a total of three times, once in the OS process and twice in the gate electrode formation process, and it is necessary to perform patterning also in processing of contact openings and wiring.

Further, etching of a silicon nitride film existing on a silicon substrate is quite difficult, and there is a risk that the silicon substrate is not limited to the silicon substrate but is etched to some extent.

Further, the isolation between the gate electrode and the source / drain regions is a film obtained by thermally oxidizing polycrystalline silicon, so that the insulation resistance is extremely low and the risk of short circuit is very high.

An object of the present invention is to reduce the number of photolithography steps, prevent a short circuit between a gate electrode and a source / drain, and provide a reliable manufacturing process of a MOS transistor with less variation. Things.

[0012]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
Forming a pad oxide film and a silicon nitride film, removing the pad oxide film and the silicon nitride film on a region to be an element isolation region, and etching the semiconductor substrate having the exposed surface to a predetermined depth to form a groove portion. After the formation, a step of forming an element isolation region having no step by forming a LOCOS oxide film in the groove by thermal oxidation using the silicon nitride film as an oxidation resistant film, and a predetermined thickness on the entire surface. After forming the silicon nitride film, a step of embedding a silicon oxide film on the element isolation region, and removing the silicon nitride film and the pad oxide film on the region to be the active region,
Depositing a first conductive material containing a conductive type impurity on the entire surface and then performing etch back to bury the first conductive material in a region to be the active region;
Removing the first conductive material in a region to be a gate electrode formation region, depositing an insulating film over the entire surface, and etching back to form sidewalls on the first conductive material sidewalls; After forming the gate oxide film, a second conductive material to be a gate electrode is deposited on the entire surface and etched back to form a gate electrode, the first conductive material burying step, and the gate electrode forming step. Forming a source / drain region by diffusing impurities contained in the first conductive material into the semiconductor substrate by performing a heat treatment between the semiconductor substrate and the gate electrode forming step. It is characterized by the following.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device, a pad oxide film and a silicon nitride film are formed on the first conductivity type semiconductor substrate, and the pad oxide film and the silicon oxide film are formed on a region to be an element isolation region. Removing the silicon nitride film;
The surface of the exposed semiconductor substrate is etched to a predetermined depth to form a groove, and then the silicon nitride film is used as an oxidation-resistant film, and a LOCOS oxide film is formed in the groove by thermal oxidation. Forming a silicon nitride film having a predetermined thickness on the entire surface, embedding a silicon oxide film on the device isolation region, and forming a silicon nitride film on the active region. And after removing the pad oxide film, by ion implantation,
Forming a second conductivity type impurity region serving as a source / drain region in a region serving as an active region, and etching back after depositing a first conductive material containing a second conductivity type impurity over the entire surface; A step of embedding the first conductive material in a region to be the active region, and removing the first conductive material in a region to be a gate electrode formation region,
Depositing an insulating film on the entire surface and etching back to form a sidewall on the side wall of the first conductive material, and using the first conductive material and the sidewall as a mask to connect the semiconductor substrate to the second conductive material; Forming a source / drain region by etching deeper than the impurity region of the mold, forming a gate oxide film, depositing a second conductive material to be a gate electrode over the entire surface, and etching back to form a gate. Forming an electrode.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

FIG. 1 shows a MOS transistor according to a first embodiment of the present invention.
Showing the first half of the manufacturing process of the type transistor (FIG.
FIG. 2A is a view showing the latter half of the manufacturing process of the MOS transistor according to the embodiment of the present invention (XX section in FIG. 3A), and FIG. ) Is a plan view in the step shown in FIG. 2A, FIG. 3B is a sectional view taken along the line YY in the step shown in FIG. 2A in FIG. 3A, and FIG. FIG. 5 is a diagram showing the first half of the manufacturing process of the MOS transistor according to the second embodiment, and FIG. 5 is a diagram showing the second half of the manufacturing process of the MOS transistor according to one embodiment of the present invention; FIG. 5A is a plan view in the step shown in FIG. 5A, and FIG. 6B is a cross-sectional view along the line XX in the step shown in FIG.

Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 1A, a thermal oxide film 2 (pad oxide film) is
A silicon nitride film 3 is formed at a thickness of 200 to 2000 .ANG., And then the active region is patterned by a known photolithography method using a resist mask. In the figure, A is an active region, B is
Indicates a field (locos) area.

Next, as shown in FIG. 1 (b), the silicon substrate in the field region is
1500 ° etched. Next, as shown in FIG. 1C, a field oxide film 4 is formed at 1000 to 3000 ° by a wet oxidation method at 1000 to 1100 ° C. Under these conditions, the silicon-etched portion of the field region is filled with the oxide film, and the surface of the active region and the surface of the field region become flat.

Next, as shown in FIG. 1 (d), a silicon nitride film 5 is formed at a thickness of 50 to 150.degree. By a CVD method, and then a SOG film is applied at a temperature of 2000 to 4000.degree. After the heat treatment, the silicon nitride film 3 was etched back to the same height. The formation of the silicon nitride film serves as a stopper at the time of etching the SOG film shown in FIG. 3A and prevents the field oxide film from being etched.

Next, as shown in FIG.
The silicon nitride film 3 on the active region is removed by the IE method, the pad oxide film 2 is removed by hydrofluoric acid, and then the phosphorus-doped polycrystalline silicon 7 is removed by the CVD method.
Deposition was performed at a depth of 00 to 20000 °, and etch back was performed until the height became the same as that of the oxide film 6 in the field region.
In this case, the polycrystalline silicon is buried with A in FIG.
This is possible when the thickness is 5 to 1.0 μm, but it is necessary to change the thickness of the polycrystalline silicon 7 depending on the desired dimensions.

Next, as shown in FIGS. 3A and 3B, a resist pattern having an opening slightly extending over the field region is used to form a gate electrode forming region as shown in FIG. 2A. The polycrystalline silicon 7 of D was removed using a known etching technique, and thereafter, the oxide film on the field region was removed by RIE. In FIG. 3A, reference numeral 13 denotes an opening of the resist pattern, and reference numeral 14 denotes an active region.

Next, as shown in FIG. 2B, an oxide film was deposited at a thickness of 500 to 1500 ° by a CVD method and etched back to obtain a side wall 8. At this time,
A sidewall width of 0.05 to 0.1 μm was obtained.

Next, as shown in FIG.
By oxidizing at 900 ° C., the gate oxide film 9 becomes 5
Then, a polycrystalline silicon 10 doped with phosphorus was deposited at 5000-15000 ° and then etched back to separate the polycrystalline silicon 10 of the gate electrode from the polycrystalline silicon 7 on the source / drain regions. The polycrystalline silicon 7 on the source / drain regions is also oxidized when the gate is oxidized, but is removed by over-etching when the polycrystalline silicon 10 is etched.

Next, a heat treatment in a nitrogen atmosphere at 900 to 1000 ° C. is performed for 50 to 80 minutes, so that the source /
Phosphorus is diffused from the polycrystalline silicon on the region to be the drain region into the silicon substrate 1 to form the source / drain region 11, thereby completing the MOS transistor. still,
In the present invention, the polycrystalline silicon may be diffused after the polycrystalline silicon 7 is deposited.

Thereafter, a metal wiring material is deposited on the entire surface,
It is patterned and completed by forming a protective film. That is, since the surface is almost flat in FIG. 2C and there is no protective film on the gate electrode and the source / drain regions,
The formation of the interlayer insulating film and the opening of the contact hole are not particularly required.

Next, a second embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 4A, a thermal oxide film 2 (pad oxide film) is
A silicon nitride film 3 is formed at a thickness of 200 to 2000 .ANG., And then the active region is patterned by a known photolithography method using a resist mask. In the figure, A is an active region, B is
Indicates a field (locos) area.

Next, as shown in FIG. 4 (b), the silicon substrate in the field region is
1500 ° etched. Next, as shown in FIG. 4C, a field oxide film 4 is formed at 1000 to 3000 ° by a wet oxidation method at 1000 to 1100 ° C. Under these conditions, the silicon-etched portion of the field region is filled with the oxide film, and the surface of the active region and the surface of the field region become flat.

Next, as shown in FIG. 4D, a silicon nitride film 5 is formed by CVD at a thickness of 50 to 150.degree., And then an SOG film is applied at 2000 to 4000.degree. After the heat treatment, the silicon nitride film 3 was etched back to the same height. The formation of the silicon nitride film serves as a stopper at the time of etching the SOG film shown in FIG. 3A and prevents the field oxide film from being etched.

Next, as shown in FIG.
The silicon nitride film 3 on the active region is removed by the IE method, the pad oxide film 2 is removed by hydrofluoric acid, and arsenic is implanted at an energy of 30 to 50 k to form source / drain regions.
Ion implantation and an arsenic implantation region 12 were formed under conditions of eV and a dose of 3 × 10 ^{15 to} 5 × 10 ¹⁵ cm ⁻² . Thereafter, the phosphorus-doped polycrystalline silicon 7 was deposited by 10,000 to 20,000 ° by the CVD method, and was etched back to the same height as the oxide film 6 in the field region. The burying of the polycrystalline silicon 7 is performed in the first
A in the figure is 0.5 to 1.0 μm
However, depending on the desired dimensions, it is necessary to change the thickness of the polycrystalline silicon 7 and the like.

Next, as shown in FIGS. 6 (a) and 6 (b), the polysilicon in the gate electrode formation region is formed by a resist pattern having openings slightly extended in the field region as shown in FIG. 5 (a). Was removed using a known etching technique, and then the oxide film on the field region was removed by RIE. In FIG. 6A, reference numeral 13 denotes an opening of the resist pattern, and reference numeral 14 denotes an active region.

Next, as shown in FIG. 5B, an oxide film was deposited at a thickness of 500 to 1500 ° by a CVD method and etched back to obtain a side wall 8. At this time,
A sidewall width of 0.05 to 0.1 μm was obtained.
Thereafter, the silicon substrate 1 is removed by a known RIE method.
Etching was performed at 00 to 1000 °. At this time, the etching is performed deeper than the arsenic implantation region 12 described above.

Next, as shown in FIG.
By oxidizing at 900 ° C., the gate oxide film 9 becomes 5
Then, a polycrystalline silicon 10 doped with phosphorus was deposited at a thickness of 5,000 to 15,000, and then etched back to separate the polycrystalline silicon 10 of the gate electrode from the polycrystalline silicon 7 on the source / drain regions. At the time of gate oxidation, the polycrystalline silicon 7 on the region serving as the source / drain region is also oxidized.
0 is removed by over-etching at the time of etching.

Next, by performing a heat treatment in a nitrogen atmosphere at 800 to 900 ° C. for 30 to 60 minutes, the arsenic implanted region 12 is activated to form the source / drain region 12a, thereby obtaining a MOS transistor. Thereafter, similarly to the first embodiment, a metal wiring material is deposited, patterned, and completed by forming a protective film. That is, FIG.
In (c), since the surface is flat and there is no protective film on the gate electrode and on the source / drain regions, there is no particular need to form an interlayer insulating film and open contact holes.

In the first and second embodiments, the NMOS type transistor has been described.
It goes without saying that a MOS transistor can be formed only by changing the polarity.

[0036]

As described in detail above, by using the present invention, the gate electrode can be formed by one photolithography process, which required two photolithography processes in the prior art. Since the gate electrode and the source / drain electrodes are insulated when forming the gate electrode, there is no need to separately form an interlayer insulating film.

When the gate electrode is formed, the surface of the gate electrode and the surface of the source / drain electrode are exposed and flat, so that this is a photolithography step for forming a contact for connecting the gate electrode and the source / drain region. .

Further, since a gate oxide and a source / drain region are separated by using a CVD oxide film, the insulation resistance is superior to that of the prior art.

As described above, according to the present invention, an existing exposure apparatus can be used to reduce the number of masks and to form the MOS type transistors having a fine gate electrode having a capability exceeding the capability of the apparatus. .

[Brief description of the drawings]

FIG. 1 is a diagram showing a first half of a manufacturing process of a MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a latter half of a manufacturing process of the MOS transistor according to the first embodiment of the present invention;

3A is a plan view in a step shown in FIG. 2A, and FIG. 3B is a sectional view taken along the line YY in the step shown in FIG.

FIG. 4 is a diagram showing a first half of a manufacturing process of a MOS transistor according to a second embodiment of the present invention;

FIG. 5 is a diagram showing a latter half of the manufacturing process of the MOS transistor according to the second embodiment of the present invention;

6 (a) is a plan view in the step shown in FIG. 5 (a), and FIG. 6 (b) is a YY sectional view in the step shown in FIG. 5 (a).

FIG. 7 is a manufacturing process diagram of a MOS transistor using a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Pad oxide film 3, 5 Silicon nitride film 4 Field oxide film 6 SOG film 7, 10 Polycrystalline silicon 8 Side wall 9 Gate oxide film 11, 12a Source / drain region 12 Arsenic implantation region 13 Resist opening 14 Activation area

Claims (2)

[Claims] A step of forming a pad oxide film and a silicon nitride film on a first conductivity type semiconductor substrate, removing the pad oxide film and the silicon nitride film on a region to be an element isolation region; After the exposed semiconductor substrate is etched to a predetermined depth to form a groove, the silicon nitride film is used as an oxidation-resistant film, and a LOCOS oxide film is formed in the groove by thermal oxidation. Forming a region, forming a silicon nitride film of a predetermined thickness on the entire surface, and then embedding a silicon oxide film on the device isolation region; and forming a silicon nitride film and a pad oxide on the region to be the active region. After removing the film and depositing a first conductive material containing impurities of the second conductivity type over the entire surface, the first conductive material is etched back to form the first conductive material on the region to be the active region. A step of embedding a conductive material, removing the first conductive material in a region to be a gate electrode formation region, depositing an insulating film on the entire surface, and etching back to form a side surface on the first conductive material sidewall. A step of forming a wall, a step of forming a gate oxide film, depositing a second conductive material to be a gate electrode over the entire surface, and etching back to form a gate electrode; By performing heat treatment between the embedding step and the gate electrode forming step or after the gate electrode forming step, the impurities contained in the first conductive material are diffused into the semiconductor substrate, so that the source / drain regions are formed. And a step of forming
A method for manufacturing a semiconductor device. 2. A step of forming a pad oxide film and a silicon nitride film on a first conductivity type semiconductor substrate, and removing the pad oxide film and the silicon nitride film on a region to be an element isolation region; After the exposed semiconductor substrate is etched to a predetermined depth to form a groove, the silicon nitride film is used as an oxidation-resistant film, and a LOCOS oxide film is formed in the groove by thermal oxidation. Forming a region, forming a silicon nitride film of a predetermined thickness on the entire surface, and then embedding a silicon oxide film on the device isolation region; and forming a silicon nitride film and a pad oxide on the region to be the active region. Forming a second conductivity type impurity region serving as a source / drain region in a region serving as an active region by ion implantation after removing the film; A step of embedding the first conductive material on the region to be the active region by depositing the first conductive material on the entire surface and then performing etch-back, and a step of embedding the first conductive material in the region to be the gate electrode formation region. Forming a sidewall on the side wall of the first conductive material by removing the first conductive material, depositing an insulating film on the entire surface, and etching back; Forming a source / drain region by etching the semiconductor substrate deeper than the second conductivity type impurity region on the mask, forming a gate oxide film and then depositing a second conductive material to be a gate electrode over the entire surface; Forming a gate electrode by etching back.
A method for manufacturing a semiconductor device.