JPH098135A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To prevent the resistance of a diffusion layer from increasing due to outer diffusion of an impurity and to drastically reduce the number of processes in the method for manufacturing p-channel MOSFET. CONSTITUTION: For example, after forming a gate electrode 16 on silicon substrate 11 where an element separation region 12 and n-type well region 13 are formed, approximately 20nm silicon nitride film 17 is formed. Then, p-type impurity is doped on the surface of the silicon substrate 11 via the silicon nitride film 17 and is activated by thermal annealing, thus forming a shallow p-type diffusion layer 18. Also, after laminating an interlayer insulation film 19 with silicon oxide film as a main constituent, the interlayer insulation film 19 and the silicon nitride film 17 are etched by changing conditions, thus forming a contact hole 21. Finally, metal wiring 22 is formed on the interlayer insulation film 19 containing the inside of the contact hole 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, for example, a MOSFET (Metal).
Oxide Semiconductor Field Effect Transistor) is used to form a diffusion layer and contact wiring connected to it.

[0002]

2. Description of the Related Art Conventionally, miniaturization has been advanced in semiconductor devices such as MOSFETs. Particularly, in the quarter micron generation and beyond, the source / drain diffusion layers have a depth of about 0.08 μm in order to suppress the short channel effect. It must be formed extremely shallow. As a method for achieving this, a method of ion-implanting impurities at a low acceleration voltage is generally used. However, in the case of this method, it is necessary to perform a thermal annealing process for activating the introduced impurities.

On the other hand, in order to reduce the area of the transistor, it is effective to set the alignment margin of the contact holes on the source / drain diffusion layers to zero. However, in this case, the field oxide film is etched due to the misalignment of the mask when opening the contact hole,
In order to prevent a short circuit between the diffusion layer and the silicon substrate, it was necessary to form the diffusion layer again after opening the contact hole.

9 to 14 show a MOSFET manufacturing process by taking a p-channel MOSFET as an example.
First, as shown in FIG. 9, after forming an element isolation region 102 and an n-type well region 103 on a silicon substrate 101, a silicon oxide film 1 of about 10 nm is formed by a thermal oxidation method.
04, and a p-type polysilicon film 105 having a thickness of about 200 nm is deposited thereon.

Then, as shown in FIG. 10, the p-type polysilicon film 105 is etched by using a photolithography process and an RIE (Reactive Ion Etching) method to form a gate electrode 106.

Thereafter, as shown in FIG. 11, the surface of the silicon substrate 101 is doped with p-type impurities such as boron by ion implantation at a low accelerating voltage of about 7 KeV to about 1 × 10 ¹⁵ cm ^-2. Then, it is activated by thermal annealing at about 850 ° C. to form the shallow p-type diffusion layer 107 to be the source / drain.

Then, as shown in FIG. 12, for example, B
An insulating film 108 having a silicon oxide film as a main component such as a PSG (Boron-doped Phospho-Silicate Glass) film is deposited to flatten the surface of the silicon substrate 101.

Then, the insulating film 108 and the silicon oxide film 104 are etched by a photolithography process and an RIE method to form a contact hole 109 connected to the p-type diffusion layer 107.

After that, as shown in FIG. 13, again, by ion implantation, p-type impurities such as boron are removed by 15 Ke.
Doping is performed at about 1 × 10 ¹⁵ cm ⁻² with an acceleration voltage of about V, and thermal annealing is performed at about 850 ° C. to form the diffusion layer 110.

As a result, the contact hole 109 is formed.
In the formation, the diffusion layer 110 is also formed in the portion overetched due to the mask misalignment with respect to the p-type diffusion layer 107, and the metal wiring to be formed later and the n-type well region 103 are insulated from each other. .

Thereafter, as shown in FIG. 14, a desired MOSFET is formed through a step of forming the metal wiring 111. However, in the MOSFET formed by the method described above, the impurities that have been doped by the thermal annealing when forming the p-type diffusion layer 107 are diffused outward, and the impurity concentration of the p-type diffusion layer 107 is reduced. Therefore, the resistance of the p-type diffusion layer 107 increases, and the MOSF
There are problems that the drain current of ET is lowered and the contact resistance is increased.

Further, the diffusion layer 110 must be re-formed in order to prevent the p-type diffusion layer 107 and the n-type well region 103 from being short-circuited due to the misalignment of the mask. Was needed.

[0013]

As described above, in the prior art, the impurity concentration of the diffusion layer is lowered by the outward diffusion of the impurities during activation annealing, and the drain current is lowered by the increase of the resistance of the diffusion layer. There is a problem that it causes an increase in contact resistance.

Further, there is a problem in that a re-diffusion step for re-forming the diffusion layer is required, and the number of steps is increased accordingly. Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device, which can prevent an increase in resistance of a diffusion layer due to outward diffusion of impurities and can significantly reduce the number of steps.

[0015]

In order to achieve the above object, in a method of manufacturing a semiconductor device according to the present invention, a step of forming a nitride film on a semiconductor substrate, and a step of forming the nitride film through the nitride film Implanting impurities into the substrate and activating it by thermal annealing to form a diffusion layer; forming an insulating film on the nitride film; selectively removing the insulating film; A step of forming an opening reaching the nitride film on the diffusion layer; a step of removing the nitride film exposed on the bottom surface of the opening to form a contact hole reaching the diffusion layer; Is filled with a conductive material to form a wiring connected to the diffusion layer.

[0016]

According to the present invention, the nitride film is formed by the above-mentioned means.
Since it can be used as an outward diffusion stopper for impurities when forming a diffusion layer and an etching stopper when forming a contact hole, it is possible to suppress outward diffusion and overetching of impurities. .

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 to 8 are MOSFETs (Metal
1 schematically shows a manufacturing process of Oxide Semiconductor Field Effect Transistor). Note that a p-channel MOSFET will be described here as an example.

First, as shown in FIG. 1, a silicon substrate 1
After forming the element isolation region 12 and the n-type well region 13 on the silicon oxide film 1, a silicon oxide film 14 of about 10 nm is formed by a thermal oxidation method, and a p-type polysilicon film 15 of about 200 nm is deposited thereon.

Subsequently, as shown in FIG. 2, the p-type polysilicon film 15 is etched by using a photolithography process and an RIE (Reactive Ion Etching) method to form a gate electrode 16.

Then, as shown in FIG.
₄ F was wet etching the silicon oxide film 14 by using, to expose the surface of the silicon substrate 11.
The step of removing the silicon oxide film 14 is not always necessary.

Thereafter, as shown in FIG. 4, for example, CV
20 nm by D (Chemical Vapor Deposition) method
The silicon nitride film 17 is formed to a certain degree. Then, as shown in FIG. 5, p-type impurities, for example, boron, which is a p-type impurity, is ion-implanted into the surface of the silicon substrate 11 through the silicon nitride film 17 at a low acceleration voltage of about 7 KeV at 1 × 10. ^The shallow p-type diffusion layer 18 serving as a source / drain is formed by doping it by about ¹⁵ cm ⁻² and activating it by thermal annealing at about 850 ° C.

At this time, the silicon nitride film 17 has a smaller segregation coefficient than the silicon oxide film, and has a larger force to shrink than the silicon substrate 11. Therefore, by covering the surface of the silicon substrate 11 with the silicon nitride film 17, it is possible to suppress outward diffusion of impurities. Therefore, it is possible to prevent the impurity concentration from decreasing and the resistance of the p-type diffusion layer 18 to increase, and to prevent the drain current of the MOSFET from decreasing and the contact resistance from increasing.

Then, as shown in FIG. 6, for example, BP
An interlayer insulating film 19 having a silicon oxide film as a main component such as an SG (Boron-doped Phospho-Silicate Glass) film is deposited to flatten the surface of the silicon substrate 11.

Thereafter, as shown in FIG. 7, the interlayer insulating film 19 and the silicon nitride film 17 are etched according to a photoresist (mask) 20 by a photolithography process and an RIE method, and the p-type diffusion is performed. Layer 1
A contact hole 21 connected to No. 8 is formed.

At this time, first, the silicon nitride film 17 is formed.
On the other hand, the etching of the interlayer insulating film 19 is performed under the condition of RIE that can obtain an etching selection ratio. As a result, the etching is temporarily stopped on the silicon nitride film 17 to form the opening 21a which becomes the source of the hole 21 (see FIG. 6).

Next, the opening 21a is formed by the RIE method.
The silicon nitride film 17 exposed at the
The contact hole 21 with extremely suppressed over-etching is completed. In this case, the silicon nitride film 1
By forming the film thickness of 7 as thin as about 20 nm, the amount of etching can be easily controlled.

That is, by etching the thin silicon nitride film 17 having a thickness of about 20 nm, the amount of overetching of the element isolation region 12 can be reduced even if the mask is misaligned with the p-type diffusion layer 18. . Therefore, the p-type diffusion layer 18 and the silicon substrate 1 are
1 (n-type well region 13) can be prevented from being short-circuited, so that it is possible to eliminate the need to re-diffuse the diffusion layer.

After removing the photoresist 20, as shown in FIG. 8, a desired p-channel MOSFET is formed through a step of forming a metal wiring 22. As described above, the silicon nitride film can be used as an impurity outward diffusion stopper when forming the p-type diffusion layer and an etching stopper when forming the contact hole.

That is, the surface of the silicon substrate is covered with a silicon nitride film having a smaller segregation coefficient than the silicon oxide film. This makes it possible to suppress outward diffusion of impurities during thermal annealing for activating the impurities doped by ion implantation. Therefore, it is possible to prevent the impurity concentration from decreasing and the resistance of the p-type diffusion layer to increase, and it is possible to prevent the drain current of the MOSFET and the contact resistance from increasing.

Further, the silicon nitride film can be used as a stopper for self-aligned contact when the contact hole is opened. Therefore, even if there is a mask misalignment, the amount of over-etching of the element isolation region can be extremely suppressed, and the re-diffusion step for re-forming the diffusion layer can be eliminated.

In the above embodiment, the case where boron is used as the p-type impurity has been described by taking the p-channel MOSFET as an example. However, the present invention is not limited to this, and boron fluoride or indium may be used, for example.

The interlayer insulating film is not limited to the BPSG film, but may be, for example, a PSG (Phospho-Silicate Glass) film or a silicon oxide film. In this case as well, the contact hole may be formed under the etching conditions that can provide a selective ratio with respect to the silicon nitride film.

Further, the silicon nitride film may be formed by, for example, a thermal nitriding method or PVD (Physical) in addition to the CVD method.
It can also be formed by the vapor deposition method. Further, not only the p-channel MOSFET but also the n-channel MOSFET can be similarly applied. In this case, the well region may be p-type, the polysilicon film may be n-type, and n-type phosphorus, arsenic, antimony, or the like may be used as the impurity of the diffusion layer.

Further, since it can be applied not only to the p-channel MOSFET but also to the n-channel MOSFET, C
It can also be applied to a semiconductor device having a MOS structure.
Of course, various modifications can be made without departing from the scope of the present invention.

[0035]

As described above in detail, according to the present invention, it is possible to prevent the increase in the resistance of the diffusion layer due to the outward diffusion of impurities and to reduce the number of steps significantly. A manufacturing method can be provided.

[Brief description of drawings]

FIG. 1 is a p-channel MO according to an embodiment of the present invention.
FIG. 6 is a schematic cross-sectional view shown for explaining the manufacturing process of the SFET.

FIG. 2 is also a schematic cross-sectional view shown for explaining the manufacturing process of the p-channel MOSFET.

FIG. 3 is a schematic sectional view similarly shown for explaining the manufacturing process of the p-channel MOSFET.

FIG. 4 is a schematic sectional view similarly shown for explaining the manufacturing process of the p-channel MOSFET.

FIG. 5 is a schematic sectional view similarly shown for explaining the manufacturing process of the p-channel MOSFET.

FIG. 6 is also a schematic cross-sectional view shown for explaining the manufacturing process of the p-channel MOSFET.

FIG. 7 is also a schematic cross-sectional view shown for explaining the manufacturing process of the p-channel MOSFET.

FIG. 8 is likewise a schematic cross-sectional view showing a p-channel MOSFET.

FIG. 9 is a schematic cross-sectional view showing a manufacturing process of a p-channel MOSFET for explaining the conventional technique and its problems.

FIG. 10 is a schematic cross-sectional view of a conventional p-channel MOSFET manufacturing process.

FIG. 11 is a schematic cross-sectional view of a conventional p-channel MOSFET manufacturing process.

FIG. 12 is also a schematic cross-sectional view of a conventional p-channel MOSFET manufacturing process.

FIG. 13 is a schematic cross-sectional view of a conventional p-channel MOSFET manufacturing process.

FIG. 14 is likewise a schematic cross-sectional view of a conventional p-channel MOSFET.

[Explanation of symbols]

11 ... Silicon substrate, 12 ... Element isolation region, 13 ... N-type well region, 14 ... Silicon oxide film, 15 ... P-type polysilicon film, 16 ... Gate electrode, 17 ... Silicon nitride film,
18 ... P-type diffusion layer, 19 ... Interlayer insulating film, 20 ... Photoresist (mask), 21 ... Contact hole, 21a ...
Opening, 22 ... Metal wiring.

Claims (2)

[Claims] 1. A step of forming a nitride film on a semiconductor substrate, a step of ion-implanting an impurity into the substrate through the nitride film, and activating the impurity by thermal annealing to form a diffusion layer, Forming an insulating film on the nitride film; selectively removing the insulating film to form an opening reaching the nitride film on the diffusion layer; and exposing the bottom surface of the opening. The method comprises: a step of removing a nitride film to form a contact hole reaching the diffusion layer; and a step of burying a conductive material in the contact hole to form a wiring connected to the diffusion layer. Manufacturing method of semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the opening, etching is performed under a condition of RIE that allows a selective ratio with respect to the nitride film.