JPH06232394A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve junction breakdown voltage, by forming a first channel stopper layer of low impurity concentration, in a region adjacent to an element forming region, and forming a second channel stopper layer of high impurity concentration, in a comparatively inner part of the element isolation region. CONSTITUTION:A pad oxide film 22 and an oxidation resistant film 23 are formed on the surface of a P-type silicon substrate 21. A side wall is formed on the side part of the oxidation resistant film 23, and high concentration impurity ions are implanted by applying the side wall to a mask. A field oxide film 26 is formed by a selective oxidation process applying the oxidation resistant film 23 to a mask. In this case, a first channel stopper layer 31 corresponding with the first ion implantation and a second channel stopper layer 32 corresponding with the second ion implantation are formed just under the field oxide film 26. Thereby a channel stopper layer wherein the impurity concentration is high in the vicinity of the element isolation region 41, and the impurity concentration is high in the central part of the element isolation region 42 can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device which is suitable for manufacturing a MOS type semiconductor integrated circuit.

[0002]

2. Description of the Related Art MOS (Metal Oxide Semiconductor)
Type semiconductor integrated circuits, so-called LOCOS (LOcal Oxidation Of Silicon
n) The technology is widely applied. The LOCOS technique is shown in FIG. That is, first, as shown in FIG. 3A, for example, a pad oxide film 2 is formed on the surface of a P-type silicon substrate 1, and an oxidation resistant film 3 such as a Si ₃ N ₄ film is deposited thereon. .

Next, as shown in FIG. 3B, the oxidation resistant film 3 is patterned by the photolithography technique using the resist 4. Then, as shown in FIG. 3 (c),
The resist 4 is removed, and the oxidation resistant film 3 is used as a mask.
B ⁺ ions for channel stopper are implanted. This B
^{The +} ion is a P-type impurity having the same conductivity type as the silicon substrate 1.

As shown in FIG. 3D, the thermal oxidation process is performed after the ion implantation, so that the silicon substrate 1 in the region where the oxidation resistant film 3 is not formed is oxidized and the field oxide film 5 grows. To do. At this time, at the same time, the implanted B ⁺ ions are activated and the channel stopper layer 6 is formed in the region below the field oxide film 5. The channel stopper layer 6 contributes to the improvement of the breakdown voltage between the element formation regions.

Finally, the oxidation resistant film 3 is peeled off to complete the element isolation process. After that, as shown in FIG. 3E, the gate oxide film 11 is formed after removing the pad oxide film 2. The gate electrode 8 is formed on the surface of the gate oxide film 11, and the N-type impurity ions are implanted and the implanted ions are activated by using the gate electrode 8 as a mask, whereby the source region 9 and the drain region are formed. 10 is formed. A plan view of the state of FIG. 3 (e) is shown in FIG.

[0006]

In order to increase the degree of integration of the MOS type semiconductor integrated circuit, it is essential to reduce the element isolation region 15 (see FIG. 3 (e)) in which the field oxide film 5 and the like are formed. It becomes an issue. Sufficient breakdown voltage is secured between the element formation regions regardless of the reduction of the element isolation region 15.
In order to prevent punch through, it is necessary to increase the impurity concentration of the channel stopper layer 6.

However, if the impurity concentration of the channel stopper layer 6 is increased, as shown by reference numeral 16 in FIG.
7 bleeds, and the effective area of the element forming region 17 decreases. Therefore, there arises a problem that the narrow channel effect remarkably appears. Further, when the impurity concentration of the channel stopper layer 6 is increased, the source region 9 and the drain region 10
Between the channel stopper layer 6 and the channel stopper layer 6 (see FIG.
See (e). ), The electric field concentrates on this boundary portion 18,
The junction breakdown voltage at 19 decreases. Further, since the junction capacitance at the boundary portions 18 and 19 increases, there is a problem that the operating speed of the element decreases.

Therefore, an object of the present invention is to solve the above-mentioned technical problems, to satisfactorily separate the element forming region, and to satisfactorily operate the element formed in the element forming region. A method of manufacturing a device is provided.

[0009]

According to a method of manufacturing a semiconductor device of the present invention for achieving the above object, an oxidation resistant film is patterned on a surface of an element forming region of a semiconductor substrate having a predetermined conductivity type. And a step of adding the impurity of a predetermined conductivity type to the semiconductor substrate at a predetermined first concentration using the oxidation resistant film as a mask, and forming a first channel stopper layer in a region not covered with the oxidation resistant film. A step of forming, a step of forming a predetermined thin film on the surface of the oxidation resistant film and the surface of the semiconductor substrate not covered with the oxidation resistant film, and etching back the predetermined thin film to form the acid resistant film. A step of forming a sidewall on a side portion of the oxidizable film and removing the predetermined thin film in the remaining portion, and using the oxidation resistant film and the sidewall as a mask, the impurity of the predetermined conductivity type on the semiconductor substrate. In a second concentration higher than the first concentration to form a second channel stopper layer in a region not covered with the oxidation resistant film or the side wall, and a step of removing the side wall. ,
A step of selectively oxidizing the surface of the semiconductor substrate using the oxidation resistant film as a mask to form an element isolation oxide film.

[0010]

According to the above method, the element isolation oxide film is formed in the region where the oxidation resistant film is not formed by the selective oxidation treatment using the oxidation resistant film as a mask. Therefore, the region separated by this element isolation oxide film becomes the element formation region, and the region where the element isolation oxide film is formed becomes the element isolation region for separating the element formation regions.

In this element isolation region, first, impurities are added at a low concentration using the oxidation resistant film formed in the element formation region as a mask to form a first channel stopper layer.
After that, a sidewall is formed on a side portion of the oxidation resistant film, and impurities are added at a high concentration using the sidewall as a mask. As a result, the second channel stopper layer is formed.

After that, the sidewalls are removed and selective oxidation treatment is performed using the oxidation resistant film as a mask, whereby an element isolation oxide film is formed in a region where the oxidation resistant film is not formed. As a result, the above first and second
The channel stopper layer will be located in a region below the element isolation oxide film. The first channel stopper layer is formed up to the boundary between the element formation region and the element isolation region.
On the other hand, the second channel stopper layer is formed in a region inside the element isolation region by a distance corresponding to the sidewall from the above-mentioned boundary portion due to the function of the sidewall.

In this structure, the first channel stopper layer adjacent to the element forming region contains only a low concentration of impurities, so that the impurities do not seep into the element forming region.
The effective area of the element formation region does not decrease. Further, since the impurity concentration of the first channel stopper layer is low,
Even if an impurity region having a conductivity type opposite to that of the first channel stopper layer is formed in a region adjacent to the first channel stopper layer in the element forming region, the boundary between the impurity region and the first channel stopper layer is formed. The electric field does not concentrate on the part. Therefore, the junction breakdown voltage at this boundary portion does not decrease, and a large parasitic capacitance does not occur.

On the other hand, since the second channel stopper layer having a high impurity concentration is formed immediately below the element isolation oxide film, the element formation region is well separated from other regions of the semiconductor substrate.

[0015]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. 1 and 2 are cross-sectional views showing, in the order of steps, manufacturing steps when a method for manufacturing a semiconductor device according to an embodiment of the present invention is applied to manufacturing a MOS semiconductor integrated circuit. In this embodiment, an N-channel MOS integrated circuit is created.

First, as shown in FIG. 1A, a pad oxide film 22 is formed on the entire surface of a P-type silicon substrate 21 by a thermal oxidation method. Furthermore, on the pad oxide film 22,
For example, Si _{3 is formed} by the CVD method (chemical vapor deposition method).
An oxidation resistant film 23 made of N ₄ is formed, and the oxidation resistant film 23 is patterned by the photolithography technique. As a result, the oxidation resistant film 23 is formed in the element formation region 41.
Patterned. The pad oxide film 22 has a film thickness of, for example, about 400 Å, and the oxidation resistant film 23 has a film thickness of, for example, about 1500 Å.

Next, as shown in FIG. 1B, the first ion implantation is performed using the oxidation resistant film 23 as a mask.
That is, B ⁺ ions, which are P-type impurities, are implanted. The implantation amount at this time is, for example, 1 × 10 ¹³ cm ^-2 . The acceleration energy of B ⁺ ions is, for example, 30 keV. In FIG. 1, B ⁺ ions implanted in the silicon substrate 21 by the first ion implantation are represented by the symbol “x”.

Then, as shown in FIG. 1 (c),
The silicon oxide film 24 as a predetermined thin film is, for example, C
It is deposited on the entire surface by the VD method. The film thickness of the silicon oxide film 24 is, eg, about 2000 Å.
The silicon oxide film 24 is formed by RIE (Reactive Ion Etc).
It is etched back by anisotropic etching such as hing). As a result, as shown in FIG. 1D, the sidewall 24A made of the silicon oxide film 24 is formed on the side portion of the oxidation resistant film 23. The remaining silicon oxide film 24 is removed.

From this state, the second ion implantation is performed. That is, B ⁺ ions, which are P-type impurities, are implanted. The injection amount at this time is, for example, 5 × 10 ¹³ cm ^-2
It is said that That is, the implantation amount is set to be larger than that in the first ion implantation. The acceleration energy of B ⁺ ions is, for example, 30 keV. In FIG. 1, B ⁺ ions implanted into the silicon substrate 21 by the second ion implantation are represented by the symbol “◯”.

Next, as shown in FIG. 2 (e), the sidewalls 24A are removed and a selective oxidation process is performed using the oxidation resistant film 23 as a mask. As a result, the surface of the silicon substrate 21 other than the region where the oxidation resistant film 23 is formed is oxidized, and the field oxide film 26 for separating the device forming region 41 from other device forming regions is formed. The region where the field oxide film 26 is formed is the element isolation region 4
It becomes 2.

For the selective oxidation treatment, for example, a temperature of 10 is used.
Steam oxidation at about 00 ° C. is applied. Due to the heat applied to the silicon substrate 21 during this selective oxidation process,
The B ⁺ ions implanted in the silicon substrate 21 are activated. As a result, the low concentration first channel stopper layer 31 corresponding to the first ion implantation and the high concentration second channel stopper layer 32 corresponding to the second ion implantation are formed in the region immediately below the field oxide film 26. Will be done.

However, the first channel stopper layer 31 is formed in a wide area up to the element forming area 41,
The second channel stopper layer 32 is formed in a relatively narrow region near the center of the element isolation region 42. This is because the sidewall 24A was not formed during the first ion implantation, whereas the sidewall 24A was formed during the second ion implantation. Also,
The second channel stopper layer 32 is diffused to a deeper portion of the silicon substrate 21 than the first channel stopper layer 31 is because the impurity ion implantation amount at the time of forming the second channel stopper layer 32 is the first channel stopper. This is because the implantation amount is set to be larger than that at the time of forming the layer 31.

From the state of FIG. 2E, as shown in FIG. 2F, the oxidation resistant film 23 is removed, and further the pad oxide film 22 is removed. Then, a gate oxide film 27 is formed by, for example, a thermal oxidation method, and a gate electrode 28 made of, for example, polysilicon is formed thereon. Next, as shown in FIG. 2G, using the gate electrode 28 as a mask,
N ⁺ type impurities such as As ⁺ ions are implanted at a high concentration to form source region 29 and drain region 30.

Further, as shown in FIG. 2H, after the interlayer film 35 is formed on the entire surface, the interlayer film 35 and the gate oxide film 27 are contacted at the positions above the source region 29 and the drain region 20, respectively. Holes 36 and 37 are formed. Electrodes 38 and 39 made of aluminum or the like are embedded in the contact holes 36 and 37 to complete the device.

As described above, according to the manufacturing method of this embodiment, the element isolation region 4 in which the field oxide film 26 is formed is formed.
2 near the boundary between the element 2 and the element formation region 41
A channel stopper layer 31 is formed, and a high concentration second channel stopper layer 32 is formed near the center of the element isolation region 42. Therefore, the impurities in the first channel stopper layer 31 do not seep out into the element forming region 31, so that the effective area of the element forming region 31 does not decrease. Thereby, the narrow channel effect can be effectively suppressed. Further, since the impurity concentration of the first channel stopper element 31 is low, this first channel stopper layer 3
Also, the electric field is not concentrated at the boundary between 1 and the source region 29 and the drain region 30 to which impurities are added at a high concentration. Therefore, the junction breakdown voltage at this boundary does not decrease. Further, since no large junction capacitance is generated at this boundary portion, the element formed in the element formation region 41 can be operated at high speed.

On the other hand, the breakdown voltage required between the element forming region 41 and other element forming regions is ensured by the presence of the second channel stopper layer 32. Therefore, the element formation region 41 can be favorably separated from the elements formed in the other element formation regions. In this way, in the semiconductor integrated circuit manufactured by the manufacturing method of the present embodiment, even if the element isolation region 42 is narrowed to improve the degree of integration, the element formation regions are well isolated. In addition, the elements formed in each element formation region can be operated well.

The embodiments of the present invention have been described above, but the present invention is not limited to the above embodiments. For example, in the above embodiment, the case where the N-channel MOS type integrated circuit is manufactured has been described, but the present invention can be easily applied to the manufacture of the P-channel MOS type integrated circuit and the CMOS integrated circuit. That is, for example, in order to form a P-channel MOS type integrated circuit, for example, when an N type well is formed on the surface of a silicon substrate and each region of this N type well is separated by a field oxide film, the lower part thereof is formed. The above-mentioned first channel stopper layer and second channel stopper layer may be formed on the substrate. However, in this case, in forming these channel stopper layers, it is necessary to implant As ⁺ ions and P ⁺ ions which are N-type impurities. The CMOS integrated circuit can be manufactured by combining the manufacturing method of the N-channel MOS type integrated circuit and the manufacturing method of the P-channel MOS type integrated circuit.

Further, in the above embodiment, the ion implantation is performed twice, but the ion implantation before forming the sidewall 24A may be omitted. That is,
The implantation amount in the first ion implantation may be zero. Further, in the above-described embodiment, the steam oxidation method is adopted in the oxidation treatment step for forming the field oxide film 26, but other methods such as a thermal oxidation method may be adopted.

Further, in the above-mentioned embodiment, the resist used for patterning the oxidation resistant film 23 is peeled off before the first ion implantation, but this resist is ion-implanted together with the oxidation resistant film 23. It may be used as a mask for implantation, and the resist may be removed after the first ion implantation. In addition, various modifications can be made without changing the gist of the present invention.

[0030]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the first channel stopper layer having a low impurity concentration is formed in the region adjacent to the element formation region, and the relatively low inside of the element isolation region is formed. A second channel stopper layer having a high impurity concentration is formed in this region.

Thus, it is possible to prevent the impurities from seeping out to the element forming region and prevent the effective area of the element forming region from decreasing. Further, even if an impurity region having a conductivity type opposite to that of the first channel stopper layer is formed in a region adjacent to the element isolation region in the element formation region, a boundary portion between the impurity region and the first channel stopper layer is formed. The junction withstand voltage at 1 does not decrease and a large parasitic capacitance does not occur.

Moreover, since the second channel stopper layer containing a high impurity concentration is formed immediately below the element isolation oxide film, the element formation region is well separated from other regions of the semiconductor substrate. As a result of these, the element formation region can be well separated from other regions, and
The element formed in the element formation region can be operated well.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a manufacturing process that follows the manufacturing process in FIG.

FIG. 3 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device in the order of steps.

4 is a simplified plan view of the configuration shown in FIG. 3 (e).

[Explanation of symbols]

 21 P-type silicon substrate 23 Oxidation resistant film 24 Silicon oxide film 24A Side wall 26 Field oxide film 31 First channel stopper layer 32 Second channel stopper layer 41 Element formation region 42 Element isolation region

Claims (1)

[Claims] 1. A step of patterning an oxidation resistant film on a surface of an element formation region of a semiconductor substrate having a predetermined conductivity type, and impurities of the predetermined conductivity type in the semiconductor substrate using the oxidation resistant film as a mask. Is added at a predetermined first concentration to form a first channel stopper layer in a region not covered with the oxidation resistant film, and a surface of the oxidation resistant film and the oxidation resistant film are covered. Not forming a predetermined thin film on the surface of the semiconductor substrate, and etching back the predetermined thin film to form a side wall on the side of the oxidation resistant film, and removing the predetermined thin film on the remaining portion. A step of removing, and using the oxidation resistant film and the sidewall as a mask, adding the impurity of the predetermined conductivity type to the semiconductor substrate at a second concentration higher than the first concentration to form the oxidation resistant film or the above. Rhino Second in areas not covered by dwall
The method includes a step of forming a channel stopper layer, a step of removing the sidewall, and a step of selectively oxidizing the surface of the semiconductor substrate with the oxidation resistant film as a mask to form an element isolation oxide film. A method of manufacturing a semiconductor device, comprising: