JP2798953B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to a structure and a manufacturing method of a MOS transistor.

(Prior Art) Semiconductor devices are being integrated more and more, and accordingly, miniaturization of MOS transistors is required. With this requirement, the distance between the gate electrode and the source / drain contact has been reduced. One of them is a MOS transistor described in Japanese Patent Application No. 63-246411 already filed by the present inventors. FIG. 4 is a sectional view showing the semiconductor device in the order of steps. An element isolation region 21 is formed by a normal LOCOS method, a silicon oxide film 23 serving as a gate insulating film is formed in the element region 22, and then polycrystalline silicon containing impurities is deposited on the entire surface, and a CVD insulating film is formed thereon. 24 is deposited and the gate electrode 25 is patterned. Then, after further depositing the CVD insulating film 26, the film is etched by anisotropic etching to leave only on the side wall of the gate electrode 25. Next, a diffusion layer 27 serving as a source / drain is formed by ion implantation, and after oxidizing the entire surface, polycrystalline silicon is deposited on the entire surface to form an interlayer insulating film 29. (FIG. 4A) Next, a resist pattern is formed by a photolithography technique, and the interlayer insulating film 29 is etched using the resist pattern as a mask to form a contact hole. At this time, even if misalignment of the mask occurs, the polysilicon 28 serves as a stopper,
Since the gate insulating film and the gate electrode are not exposed, they are not damaged. Thereafter, the polysilicon 28 at the bottom of the contact hole is removed by etching, and a CVD insulating film 30 is deposited on the entire surface. (FIG. 4 (b)) Next, an Al wiring 31 is formed by anisotropic etching, leaving only the side wall of the contact hole. At this time, the polycrystalline silicon remaining on the periphery becomes a silicon oxide film 32 through an oxidation step of heating in an oxygen atmosphere after depositing the CVD insulating film 30 on at least the entire surface, so that the remaining polycrystalline silicon may cause some problems. There is nothing. (4th
(FIG. (C)) In the semiconductor device as described above, as the area of the element region becomes smaller and smaller, the thickness of the insulating film left on the gate side wall must be made sufficiently thin so as to lower the contact resistance even a little.

At this time, in the conventional structure, the gate electrode is patterned almost vertically, and the insulating film left on the side wall becomes thinner toward the upper side. There is a concern that the distance between the two will be the shortest and both will be short-circuited at this point. The fact that the shape of the gate electrode is square in this portion also causes concentration of an electric field and leads to deterioration of withstand voltage.

As described above, in the related art, the withstand voltage of the insulating film between the gate electrode and the Al wiring is deteriorated in the upper corner portion of the gate electrode, so that the film cannot be sufficiently thinned, which hinders miniaturization of the element. Was.

(Problems to be Solved by the Invention) As described above, in the conventional method for manufacturing a MOS transistor, it was difficult to make the distance between the gate electrode and the Al wiring sufficiently small. The present invention is an MO that solves such a problem.
An object of the present invention is to provide a structure and a manufacturing method of an S transistor.

[Configuration of the invention]

Means for Solving the Problems The present invention has been made in view of the above circumstances, and has a gate electrode having a trapezoidal cross section formed on a semiconductor substrate via a gate insulating film, and a gate on the gate electrode. A semiconductor device comprising: an insulating film formed wider than an upper surface of an electrode; and a side wall insulating film formed from the insulating film to a side surface of the gate electrode.

A step of forming a gate insulating film on the semiconductor substrate; a step of forming a conductive film and then an insulating film pattern on the gate insulating film; and anisotropically etching the conductive film after isotropic etching. A method of forming a gate electrode having a trapezoidal cross section by using the method, and a step of forming a sidewall insulating film from the insulating film pattern to a side surface of the gate electrode. .

(Operation) As described above, in the semiconductor device of the present invention, the gate electrode below the insulating film has a trapezoidal cross section having an upper portion tapered, and the sidewall insulating film is formed on the side surface of the gate electrode. Therefore, it is possible to secure a sufficient thickness of the side wall insulating film at the upper corner of the gate electrode, to prevent electric field concentration even when miniaturizing the MOS transistor, and to prevent a short circuit with the Al wiring. Become.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

An element isolation region 2 is formed on a P-type semiconductor substrate 1 by a normal LOCOS method or the like. Further, a gate oxide film 3 is formed at a predetermined position of an element formation region on the P-type semiconductor substrate 1. Further, on the gate oxide film 3, a conductor film having a trapezoidal cross section, for example, a gate electrode 4 made of polycrystalline silicon in which phosphorus is diffused at a high concentration is formed. On this gate electrode 4, an insulating film 5 having a thickness of 5000 ° which is wider than the upper surface of the gate electrode 4 is formed. A sidewall insulating film 6 made of, for example, an LP-CVD oxide film is formed from the insulating film 5 to the side surface of the gate electrode 4. Polycrystalline silicon into which impurities are ion-implanted to contact the P-type semiconductor substrate 1 from a predetermined position on the insulating film 5 to the side wall insulating film 6, the source / drain region 7, and a part of the element isolation region 2. Is formed. Further, an interlayer insulating film 9 is formed so as to cover the insulating film 5 and the element isolation region 2.
A wiring 10 of Al or the like is formed from the pad layer 8 on the source / drain region 7 to the interlayer insulating film 9 on the element isolation region 2.

In the semiconductor device having the above-described structure, the upper portion of the gate electrode 4 has a tapered shape and the upper corner is shifted, so that the film of the sidewall insulating film 6 left on the side surface of the gate electrode 4 is formed. It is possible to prevent the thickness from becoming thin at this corner, and the concentration of the electric field at this corner is reduced, and the withstand voltage can be ensured. You can do it.

FIG. 2 is a sectional view showing the steps of manufacturing the semiconductor device according to the embodiment of the present invention in the order of steps.

First, an element isolation region 2 is formed on a P-type semiconductor substrate 1 having a specific resistance of about 5 Ω · cm by, for example, a normal LOCOS method. Next, ion implantation for controlling a threshold value is performed in the element formation region as needed. Next, a gate oxide film 3 is formed to a thickness of about 10 nm in an element formation region on the P-type semiconductor substrate 1 and then has a thickness of about 10 nm.
350nm polycrystalline silicon film and 300nm thick CVD
An insulating film 5 made of an oxide film is deposited. (FIG. 2A) Next, the insulating film 5 is left only on the gate electrode 4 formation region by photolithography and anisotropic etching. Next, when the polycrystalline silicon film is exposed, the polycrystalline silicon film is etched using an insulating film 5 as a mask by an isotropic etching technique such as a chemical dry etching method so that at least the entire polycrystalline silicon film is not removed by etching.
(FIG. 2B) Next, using the insulating film 5 as a mask, the remaining polycrystalline silicon is etched by an anisotropic etching technique. As described above, the gate electrode 4 is formed in a shape with a sharp upper corner of the gate electrode 4 (FIG. 2 (c)). Next, an LP-CVD oxide film is deposited on the entire surface to a thickness of about 100 nm and anisotropically. By performing the reactive etching, the side wall insulating film 6 is left only on the side surface of the gate. At this time, the P-type semiconductor substrate 1 in the source / drain region is exposed by the over-etching of the anisotropic etching. Next, after polycrystalline silicon is deposited on the entire surface and impurities are ion-implanted, the insulating film 5 is formed by photolithography and anisotropic etching.
A pad layer 8 is formed from a predetermined position on the sidewall insulating film 6, the source / drain region 7, and a part of the element isolation region 2. Since the pad layer 8 is formed so as to cover the side wall of the gate electrode 4, even if the subsequent contact hole is misaligned due to misalignment, short circuit to the gate electrode 4 is prevented. In addition, since the pad layer 8 protrudes into the element isolation region 2 and is patterned, a so-called punch-through phenomenon caused by opening a contact in contact with the element isolation region 2 is prevented. Therefore,
Contact patterning can be performed relatively easily even with a fine MOS transistor. Next, after depositing a silicon oxide film from the insulating film 5 on the entire surface of the pad layer and the element isolation region by a CVD method or the like, an interlayer insulating film covering the insulating film 5 and the element isolation region 2 by a photolithography technique and an anisotropic etching technique. 9 is formed. Further, wiring such as Al is formed from the end of the interlayer insulating film 9 on the insulating film 5 to the pad layer 8 on the source / drain region 7 and the end of the interlayer insulating film 9 on the element isolation region 2. (FIG. 2 (d)) In the method of manufacturing a semiconductor device as described above, it is possible to prevent the thickness of the side wall insulating film 6 left on the side surface of the gate electrode 4 from becoming thin at this corner, The electric field concentration in which the upper corners of the gate electrode 4 are staggered is alleviated, the thickness of the sidewall insulating film can be reduced to the utmost, and a fine transistor can be formed.

FIG. 3 is a sectional view of a semiconductor device showing a modification of the embodiment of the present invention.

After the step shown in FIG. 2 (c) is completed, the polycrystalline silicon film is further etched by using an isotropic etching technique, so that a slight corner shown in FIG. A gate electrode 4 having an appropriate forward tapered shape is formed.
Next, the side wall insulating film 6 is formed by the process shown in FIG.

In the method of manufacturing a semiconductor device as described above, the thickness of the side wall insulating film 6 can be made almost the same everywhere, the electric field concentration can be reduced, and the thickness of the side wall insulating film 6 can be made as thin as possible. A fine transistor can be formed, and reliability can be increased.

Further, the insulating film 5 of the present embodiment is not necessarily limited to the silicon oxide film, and a composite film made of a polycrystalline silicon film, a silicon nitride film, a silicon oxide film or the like is taken into consideration in consideration of a selectivity at the time of etching. May be used.

As the pad layer 8, a silicon epitaxial film may be used in addition to the polycrystalline silicon.
May not be required.

Further, when the gate electrode 25 is processed using the CVD insulating film 24 as a mask in the step of FIG. 4A, isotropic etching and then anisotropic etching are performed as described above. It is also effective to carry out the steps b) and (c).

〔The invention's effect〕

As described above, according to the semiconductor device of the present invention, it is possible to reduce the electric field concentration of the gate electrode by forming the corner of the gate electrode or making the gate taper forward, so that the withstand voltage can be sufficiently secured. Further, even if the thickness of the sidewall insulating film is reduced, a short circuit between the gate electrode and the wiring can be prevented, and a fine and highly reliable MOS transistor can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG.
FIG. 3 is a cross-sectional view showing a process of an embodiment of the present invention, FIG. 3 is a cross-sectional view showing a modification of the embodiment of the present invention, and FIG. In the drawing, 1 ... P-type semiconductor substrate, 2 ... Element isolation region, 3 ... Gate oxide film, 4 ... Gate electrode, 5 ... Insulating film, 6 ...
Side wall insulating film, 7: source / drain region, 8: pad layer, 9: interlayer insulating film, 10: Al wiring, 21: element isolation region, 22: element region, 23: silicon oxide film ,twenty four…
... CVD insulating film, 25 ... gate electrode, 26 ... CVD insulating film, 27
... diffusion layer, 28 ... polycrystalline silicon, 29 ... interlayer insulating film, 30 ... CVD insulating film, 31 ... Al wiring, 32 ... silicon oxide film.

Claims (2)

(57) [Claims] A semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first width formed on the gate insulating film, having a first width on a bottom surface, and an upper surface facing the bottom surface. A gate electrode having a second width smaller than the first width, and having a smooth and outwardly projecting side surface between the bottom surface and the top surface; and a side wall insulation formed in contact with the side surface. A semiconductor device comprising: a film; A step of forming a gate insulating film on the semiconductor device; a step of forming a conductive film on the gate insulating film; a step of forming a mask pattern on the conductive film; Forming a gate electrode having outwardly convex and smooth side surfaces by sequentially performing isotropic etching, anisotropic etching, and isotropic etching on the conductive film; Forming a side wall insulating film on the semiconductor device.