JPH04101433A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simplify the manufacturing process by making the device in such a structure that a side-wall silicon oxide film is protruded from the gate electrode. CONSTITUTION:After formation of an oxide film 2 on a P-type silicon substrate 1, the substrate is subjected to thermal oxidation to form an oxide film on a part of the surface of the substrate on which an element is formed. Next, a non-doped polycrystal silicon layer 4, silicon oxide film 5 and silicon nitride film 6 are deposited in this order and are etched to form a gate electrode. Using the silicon nitride film 6 and oxide film 2 as a mask, phosphorus is injected by ion implantation to form a diffusion layer 7. After that, a side-wall silicon oxide film 8 is formed and then a silicon oxide film 9 is formed. After removal of the silicon nitride film 6, arsenic is injected by ion implantation to form a diffusion layer 10. Next, a silicon oxide film 11 is deposited and photo resist is applied. And, an opening is made on the photo resist film 12. After that, the silicon oxide film 11 is etched to form a contact hole and a polycrystal silicon film 13 is deposited and etched to form an interconnection layer. Then, an aluminum interconnection layer is formed. Consequently, a MOS integrated circuit in which self-alignment contact is employed can be manufactured by an easy and simple process.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.

[Conventional technology]

As shown in FIG. 3(a), the conventional method for manufacturing a semiconductor device is to form a field oxide film 2 on the surface of a P-type silicon substrate 1 using a selective oxidation method to define an element formation region.
The silicon substrate 1 is thermally oxidized at about 900° C. to form a gate oxide M3 with a thickness of about 20 nm on the surface of the element formation region. Next, a polycrystalline silicon layer 4 with a thickness of about 300 nm is deposited on the surface including the gate oxide film 3, and phosphorus is added so that the layer resistance becomes 15 to 20 Ω/hole. Next, a silicon oxide film 15 with a thickness of about 300 nm is deposited on the entire surface, and the silicon oxide film 15 and the polycrystalline silicon layer 4 are selectively etched in sequence to form a gate electrode. Next, using the gate electrode and field oxide film 2 as a mask, phosphorus ions of about 1.013 cm-'' are implanted into the surface of the element formation region to form an N- type diffusion layer 7.

Next, as shown in FIG. 3(b), a sidewall silicon oxide film 8 with a width of about 200 nm is formed using a known method, and a width of about 5×1015 cm- is formed using the sidewall silicon oxide film 8 as a mask.
Arsenic ions of No. 2 are ion-implanted to form an N+ type scattering layer 10. Next, a silicon oxide film 16 is formed over the entire surface by low pressure CVD.
is deposited to a thickness of approximately 300 nm.

Next, as shown in FIG. 3(C), a photoresist film 12 is coated on the entire surface and selectively exposed and developed.
A pattern for forming a contact hole is formed on the + type scattering layer 10, and the silicon oxide film 16 is etched using the photoresist film 12 as a mask to form a contact hole. At this time, since the polycrystalline silicon layer 4 of the gate electrode is covered with the thick silicon oxide 15.1.6, there is no need to provide a margin between the contact hole and the gate electrode.

[Invention or problem to be solved]

In recent years, with the miniaturization of devices, the channel length of transistors is being reduced from submicrons to half microns. Accordingly, it is being considered to shorten the channel by changing the P-channel MOS transistor, which has conventionally operated as a buried channel type, to a surface channel type operation. As a method for manufacturing a complementary MO3 semiconductor device including a surface channel type P-channel MO3) transistor,
After patterning non-doped polycrystalline silicon as a gate electrode, when high concentration impurities are implanted into the source and drain regions, impurities are also implanted into the gate electrode at the same time to change the gate electrode of the N-channel MO3) transistor from an N+ type to a P-channel transistor. A method is used to dope the gate electrode of a MOS transistor to P+ type, but the conventional manufacturing method described above has the problem that impurity ions cannot be introduced into the gate electrode due to the presence of a thick oxide film on the gate electrode. There is.

In addition, if the thickness of the silicon oxide film on the gate is made thin so that impurity ions are implanted into the gate electrode by ion implantation into the source/drain region, if there is no margin between the contact hole and the gate electrode, the wiring layer Therefore, in the conventional technology, self-line contact is used to make the P-channel MO3) transistor perform surface channel type operation.
There is a problem in that a complicated process is required, such as pre-diffusing boron only into the gate electrode of the transistor to dope it to P+ type.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of forming a gate oxide film on the surface of an element formation region provided on the main surface of a semiconductor substrate of a -conductivity type, and forming a polycrystalline silicon layer on the gate oxide layer. a step of sequentially depositing different kinds of insulating films; a step of selectively and sequentially etching the insulating film and the polycrystalline silicon layer to form a gate electrode with a laminated structure; a step of forming a low concentration diffusion layer by ion-implanting a type of impurity; a step of forming a sidewall insulating film made of a different material from the insulating film of the uppermost layer of the gate electrode on the side surface of the gate electrode of the stacked structure; The step of removing the upper layer insulating film, and the step of ion-implanting impurities of opposite conductivity type into the element formation region using the gate electrode and sidewall insulating film as a mask to form a high concentration diffusion region, and at the same time, injecting impurities into the polycrystalline silicon layer. The method includes a step of doping conductive impurities, and a step of depositing an insulating film over the entire surface and selectively etching it to form a contact hole on the high concentration diffusion region.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type silicon substrate 1
A field oxide film 2 is formed on one main surface using a selective oxidation method to define an element formation region.

Next, the silicon substrate 1 is thermally oxidized at about 900° C. to form a gate oxide film 3 with a thickness of about 20 nm on the surface of the element formation region. Next, about 300nm is applied to the surface including the gate oxide film 3.
undoped polycrystalline silicon layer 4 with a thickness of m and about 30n
A silicon oxide film 5 with a thickness of m and a silicon nitride film 6 with a thickness of about 500 nm are sequentially deposited to form a silicon nitride film 6. The silicon oxide film 5 and the polycrystalline silicon layer 4 are selectively and sequentially etched to form a gate electrode. Next, using the silicon nitride film 6 and field oxide film 2 as a mask, 1013c
An N- type diffusion layer 7 is formed by ion-implanting phosphorus in an amount of about m-''.

Next, as shown in FIG. 1(b), a polycrystalline silicon layer 4
．． Silicon oxide film 5. A sidewall silicon oxide film 8 having a width of about 200 nm is formed on the side surface of the silicon nitride film 6 by a sidewall forming method. Next, a silicon oxide film 9 of about 20 nm thick is formed on the silicon substrate by performing oxidation in dry oxygen at about 900°C. Next, the silicon nitride film 6 is removed using hot phosphoric acid, and about 5×10 15 cm −2 of arsenic is ion-implanted to form an N+ type scattering layer 10 connected to the N− type diffusion layer 7.
Form. At this time, since the silicon oxide film 5 on the polycrystalline silicon layer 4, which is the gate electrode, is as thin as about 30 nm, a sufficient amount of arsenic is implanted into the polycrystalline silicon layer 4. is doped to N+ type. Further, the structure is such that the sidewall silicon oxide film 8 protrudes beyond the polycrystalline silicon layer 4 of the gate.

Next, as shown in FIG. 1(C), about 300 nm is applied to the entire surface.
After silicon oxide M11- is deposited to a thickness of 1.0 by low pressure CVD, a photoresist film 1.2 is applied, and a hole is opened in the photoresist film 12 in a contact hole formation region using photolithography. Here, as in the case of normal self-line contacts, the corners of the gate electrode are covered with a thicker oxide film than the top of the diffusion layer, so it is necessary to provide a sufficient margin between the contact hole and the gate electrode. There isn't. Next, the silicon oxide film 11 is etched using the photoresist M12 as a mask to form a contact hole, and then a polycrystalline silicon layer 13 with a thickness of about 300 nm is deposited on the entire surface and selectively etched to form an N+ type film. A wiring layer connecting the distributed layer 10 is formed.

Thereafter, a semiconductor device can be constructed by depositing an interlayer insulating film by known means, forming contact holes, and forming an aluminum wiring layer.

FIG. 2(a) is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

As shown in FIG. 2(a), after forming up to the gate oxide film 3 through the same steps as in the first embodiment, a polycrystalline silicon layer 4 and a silicon nitride film 6 are formed on the surface including the gate oxide film 3. A gate electrode is formed by sequentially depositing and selectively etching. Next, phosphorus ions are implanted using the silicon nitride film 6 and the field oxide film 2 as masks to form an N- type diffusion layer 7.

Next, as shown in FIG. 2(b), a polycrystalline silicon layer 4
Then, a sidewall silicon oxide film 8 is formed on the side surface of the silicon nitride film 6, the silicon nitride film 6 is removed, and arsenic is ion-implanted using the polycrystalline silicon layer and the sidewall silicon oxide WX8 as a mask to form an N+ type scattering layer 10. Form. Next, a titanium layer is deposited on the entire surface and heat treated to form a titanium silicide layer 14 on the surfaces of the polycrystalline silicon layer 6 and the N+ type scattering layer 10 in contact with the silicon layer, and the unreacted titanium layer is removed.

Next, as shown in FIG. 2(c), a silicon oxide film 11 is coated on the entire surface with H! After stacking, a photoresist film 12 is applied and patterned, and the silicon oxide film 11 is etched using the photoresist film 12 as a mask to form a contact hole. Thereafter, a semiconductor device is constructed through the same steps as in the first embodiment.

Here, providing the titanium silicide layer 14 has the advantage of lowering the resistance.

〔Effect of the invention〕

As explained above, the present invention deposits a silicon nitride film on a polycrystalline silicon layer that will become a gate electrode, forms a sidewall silicon oxide film on the sidewalls of the gate electrode after patterning the gate electrode, and then deposits a silicon nitride film on the gate electrode. By removing the film, the sidewall silicon oxide film is made to protrude beyond the gate electrode, thereby ensuring insulation between the oxide layer and the gate electrode when forming a self-line contact, and preventing impurity ions from forming on the gate electrode. Surface channel type CMO3 for both N-channel and P-channel using Selfaline Contactor 1~ with easy injection process.
This has the effect that integrated circuits can be manufactured.

]...P-type silicon substrate, 2...field oxide film,
3... Gate oxide film, 4... Polycrystalline silicon layer, 5...
・Silicon oxide film, 6... Silicon nitride film, 7...
N-type diffusion layer, 8... sidewall silicon oxide film, 9...
silicon oxide film, ]0.N+ type scattering layer 11... silicon oxide film, ]2... photoresist film, 13... polycrystalline silicon layer, 14... titanium silicide layer, 1516...
・Silicon oxide film.

Claims (1)

[Claims] A step of forming a gate oxide film on the surface of an element formation region provided on the main surface of a semiconductor substrate of one conductivity type, and a step of sequentially depositing a polycrystalline silicon layer and at least one type of insulating film on the gate oxide film. a step of selectively and sequentially etching the insulating film and the polycrystalline silicon layer to form a gate electrode with a stacked structure; and a step of ion-implanting impurities of opposite conductivity type into the element formation region using the gate electrode as a mask. a step of forming a concentration diffusion layer; a step of forming a sidewall insulating film of a different material from the uppermost layer insulating film of the gate electrode on the side surface of the gate electrode of the stacked structure; and a step of removing the uppermost layer insulating film. , ion-implanting impurities of opposite conductivity type into the element formation region using the gate electrode and sidewall insulating film as a mask to form a high concentration diffusion region, and simultaneously doping the polycrystalline silicon layer with impurities of opposite conductivity type; 1. A method of manufacturing a semiconductor device, comprising the steps of: depositing an insulating film over the entire surface and selectively etching it to form a contact hole on a high concentration diffusion region.