JP3521921B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP3521921B2
JP3521921B2 JP18354992A JP18354992A JP3521921B2 JP 3521921 B2 JP3521921 B2 JP 3521921B2 JP 18354992 A JP18354992 A JP 18354992A JP 18354992 A JP18354992 A JP 18354992A JP 3521921 B2 JP3521921 B2 JP 3521921B2
Authority
JP
Japan
Prior art keywords
film
contact layer
forming
buried contact
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP18354992A
Other languages
Japanese (ja)
Other versions
JPH0629381A (en
Inventor
明生 名取
俊彦 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP18354992A priority Critical patent/JP3521921B2/en
Publication of JPH0629381A publication Critical patent/JPH0629381A/en
Application granted granted Critical
Publication of JP3521921B2 publication Critical patent/JP3521921B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】 【0001】 【産業上の利用分野】本発明は、埋め込みコンタクト層
を具備する半導体装置の構造に関し、特に素子分離領域
の構造に関する。 【0002】 【従来の技術】図3に、従来の、埋め込みコンタクト層
を有するMOSFETの構造を示す。P型半導体基板1
表面に、N型不純物拡散層2からなるソース,ドレイン
領域と、ゲート酸化膜3と、多結晶シリコン膜からなる
ゲート電極4により構成されるNチャンネル型MOSF
ETが形成されている。多結晶シリコン膜5により形成
される埋め込みコンタクト層6に隣接する素子分離膜9
の分離幅(図中L1)は、埋め込みコンタクト層6に隣
接しない素子分離膜7の分離幅(図中L2)と同一であ
った。 【0003】 【発明が解決しようとする課題】しかし、前記のような
従来構造の半導体装置は、下記のような問題点を有して
いた。 【0004】シリコン基板と多結晶シリコン膜の接触及
び、多結晶シリコン膜から拡散された不純物層よりなる
埋め込みコンタクト層を形成するためには、多結晶シリ
コン膜を形成する前に、シリコン基板上のシリコン酸化
膜を除去する必要がある。このとき、フォトリソグラフ
ィ工程における合わせズレを考慮して除去のためのパタ
ーニングを行なうため、埋め込みコンタクト層に隣接す
る素子分離膜の一部も除去されてしまう。 【0005】この、素子分離膜の除去により、素子分離
膜の膜厚は薄くなり、更に素子分離幅も縮小してしまう
ため、素子分離特性が悪くなり寄生MOSトランジスタ
が形成され易くなってしまう。 【0006】そこで、本発明はこのような課題を解決し
ようとするもので、その目的とするところは、埋め込み
コンタクト層を具備する半導体装置において、素子分離
特性を向上せしめた半導体装置を提供するところにあ
る。 【0007】 【課題を解決するための手段】本発明の半導体装置の製
造方法は、埋め込みコンタクト層を含むMOSトランジ
スタを有する半導体装置の製造方法であって、半導体基
板に第1のLOCOS膜と前記第1のLOCOS膜より
も幅の広い第2のLOCOS膜とを形成する工程と、前
記第1のLOCOS膜と前記第2のLOCOS膜とに挟
まれた前記半導体基板の上にゲート絶縁膜を形成する工
程と、前記ゲート絶縁膜のうち前記第2のLOCOS膜
に近接する部分と、前記第2のLOCOS膜の上部とを
除去することにより、前記ゲート絶縁膜に開孔部を形成
する工程と、前記開孔部の内に導体層を形成する工程
と、前記開孔部の下方の前記半導体基板に前記埋め込み
コンタクト層を前記導体層から前記開孔部の下方の前記
基板に不純物を導入することにより形成する工程と、前
記埋め込みコンタクト層に近接する領域に前記MOSト
ランジスタのソース領域又はドレイン領域のいずれか一
方となる第1の不純物領域を形成し、前記第1のLOC
OS膜に近接する領域に前記ソース領域又はドレイン領
域の他方となる第2の不純物領域を形成する工程とを有
し、前記埋め込みコンタクト層に隣接する前記第2のL
OCOS膜の幅が前記第1のLOCOS膜の幅より広い
半導体装置を得ることを特徴とする。 【0008】 【実施例】以下、本発明の実施例を図面により詳細に説
明する。 【0009】図1は、本発明による半導体装置の構造断
面図である。 【0010】P型半導体基板1表面に、N型不純物拡散
層2からなるソース,ドレイン領域と、ゲート酸化膜3
と、多結晶シリコン膜からなるゲート電極4により構成
されるNチャンネル型MOSFETが形成されている。
多結晶シリコン膜5により形成される埋め込みコンタク
ト層6に隣接する素子分離膜9の分離幅(図中L1)
は、埋め込みコンタクト層6に隣接しない素子分離膜7
の分離幅(図中L2)よりも広くなっている。 【0011】次に、本発明の半導体装置の製造方法の一
実施例を図2(a)〜図2(d)に基づき説明する。 【0012】まず、P型半導体基板1表面に、素子分離
膜10および約200オングストロームのゲート酸化膜
3を形成する。この状態を図2(a)に示す。 【0013】次に、パターニングされたフォトレジスト
膜8を用いて、埋め込みコンタクト層を形成する領域の
ゲート酸化膜3を除去する。このとき、埋め込みコンタ
クト層に隣接する領域の素子分離膜9の上部も同時に除
去される。この状態を図2(b)に示す。 【0014】次に、フォトレジスト膜を除去後、約40
00オングストロームの多結晶シリコン膜を化学的気相
成長法により形成し、N型不純物、例えば、燐イオンを
イオン注入した後、パターニングしてMOSFETのゲ
ート電極4および、埋め込みコンタクト層を形成する多
結晶シリコン膜5を形成する。次に、800〜900℃
程度の熱アニールにより、前記多結晶シリコン膜5中の
燐をゲート酸化膜3の開孔部より、P型半導体基板1中
に導入し埋め込みコンタクト層6を形成する。この状態
を図2(c)に示す。 【0015】次に、ゲート電極4、多結晶シリコン膜5
および素子分離膜7,9をマスクとして、N型不純物、
例えば、燐イオンをイオン注入し、N型不純物拡散層2
を形成する。この状態を図2(d)に示す。 【0016】その後は、通常のプロセスにより、埋め込
みコンタクト層を具備する半導体装置を得ることができ
る。 【0017】以上実施例に基づき具体的に説明したが、
本発明は上記実施例に限定されるものではなく、例え
ば、MOSFETはPチャンネル型であっても本発明を
適用できる。 【0018】 【発明の効果】以上述べたように本発明によれば、埋め
込みコンタクト層を具備する半導体装置において、埋め
込みコンタクト層に隣接する素子分離膜の分離幅を、埋
め込みコンタクト層に隣接しない素子分離膜の分離幅よ
りも広くすることにより、埋め込みコンタクト層形成に
伴う素子分離膜の除去による素子分離特性の劣化を防
ぎ、素子分特性を向上せしめた半導体装置の提供が可能
となる。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device having a buried contact layer, and more particularly to a structure of an element isolation region. 2. Description of the Related Art FIG. 3 shows a structure of a conventional MOSFET having a buried contact layer. P-type semiconductor substrate 1
On the surface, an N-channel MOSF composed of source and drain regions composed of an N-type impurity diffusion layer 2, a gate oxide film 3, and a gate electrode 4 composed of a polycrystalline silicon film.
ET is formed. Element isolation film 9 adjacent to buried contact layer 6 formed by polycrystalline silicon film 5
Is the same as the isolation width of the element isolation film 7 not adjacent to the buried contact layer 6 (L2 in the figure). [0003] However, the semiconductor device having the conventional structure as described above has the following problems. In order to contact a silicon substrate with a polycrystalline silicon film and to form a buried contact layer made of an impurity layer diffused from the polycrystalline silicon film, a silicon substrate must be formed before the polycrystalline silicon film is formed. It is necessary to remove the silicon oxide film. At this time, since patterning for removal is performed in consideration of misalignment in the photolithography process, a part of the element isolation film adjacent to the buried contact layer is also removed. The removal of the device isolation film reduces the film thickness of the device isolation film and further reduces the device isolation width, thereby deteriorating the device isolation characteristics and easily forming a parasitic MOS transistor. Accordingly, the present invention is to solve such a problem, and an object of the present invention is to provide a semiconductor device having a buried contact layer and having improved element isolation characteristics. It is in. A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a MOS transistor including a buried contact layer, wherein a first LOCOS film is formed on a semiconductor substrate. Forming a second LOCOS film wider than the first LOCOS film; and forming a gate insulating film on the semiconductor substrate sandwiched between the first LOCOS film and the second LOCOS film. Forming and forming an opening in the gate insulating film by removing a portion of the gate insulating film close to the second LOCOS film and an upper portion of the second LOCOS film. Forming a conductor layer in the opening, and burying the embedded contact layer in the semiconductor substrate below the opening from the conductor layer to the substrate below the opening. Forming an impurity by introducing an impurity, and forming a first impurity region to be one of a source region and a drain region of the MOS transistor in a region adjacent to the buried contact layer;
Forming a second impurity region serving as the other of the source region and the drain region in a region adjacent to the OS film, wherein the second L region adjacent to the buried contact layer is formed.
A semiconductor device in which the width of the OCOS film is wider than the width of the first LOCOS film is obtained. An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a structural sectional view of a semiconductor device according to the present invention. On the surface of a P-type semiconductor substrate 1, a source / drain region comprising an N-type impurity diffusion layer 2 and a gate oxide film 3
And an N-channel MOSFET formed by a gate electrode 4 made of a polycrystalline silicon film.
Isolation width of element isolation film 9 adjacent to buried contact layer 6 formed by polycrystalline silicon film 5 (L1 in the figure)
Is a device isolation film 7 not adjacent to the buried contact layer 6
(L2 in the figure). Next, one embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 2 (a) to 2 (d). First, an element isolation film 10 and a gate oxide film 3 of about 200 Å are formed on the surface of a P-type semiconductor substrate 1. This state is shown in FIG. Next, using the patterned photoresist film 8, the gate oxide film 3 in the region where the buried contact layer is to be formed is removed. At this time, the upper portion of the element isolation film 9 in the region adjacent to the buried contact layer is also removed at the same time. This state is shown in FIG. Next, after removing the photoresist film, about 40
A polycrystalline silicon film of 00 Å is formed by a chemical vapor deposition method, and an N-type impurity, for example, phosphorus ions is ion-implanted and then patterned to form a MOSFET gate electrode 4 and a buried contact layer. A silicon film 5 is formed. Next, 800-900 ° C
By thermal annealing to a certain extent, phosphorus in the polycrystalline silicon film 5 is introduced into the P-type semiconductor substrate 1 from the opening of the gate oxide film 3 to form a buried contact layer 6. This state is shown in FIG. Next, the gate electrode 4, the polycrystalline silicon film 5
And an N-type impurity using the element isolation films 7 and 9 as a mask.
For example, phosphorus ions are implanted, and the N-type impurity diffusion layer 2 is formed.
To form This state is shown in FIG. Thereafter, a semiconductor device having a buried contact layer can be obtained by an ordinary process. The above has been specifically described based on the embodiments.
The present invention is not limited to the above embodiment. For example, the present invention can be applied even if the MOSFET is a P-channel type. As described above, according to the present invention, in a semiconductor device having a buried contact layer, the isolation width of an element isolation film adjacent to the buried contact layer is reduced by an element not adjacent to the buried contact layer. By making the separation width larger than the separation width of the separation film, it is possible to prevent the deterioration of the element separation characteristics due to the removal of the element separation film due to the formation of the buried contact layer, and to provide a semiconductor device with improved element separation characteristics.

【図面の簡単な説明】 【図1】本発明の半導体装置の構造断面図を示す図であ
る。 【図2】本発明の半導体装置の製造方法の一実施例を示
す図である。 【図3】従来の半導体装置の構造断面図を示す図であ
る。 【符号の説明】 1 P型半導体基板 2 N型不純物拡散層 3 ゲート酸化膜 4 ゲート電極 5 多結晶シリコン膜 6 埋め込みコンタクト層 7 埋め込みコンタクト層に接しない素子分離膜 8 フォトレジスト膜 9 埋め込みコンタクト層に接する素子分離膜 10 素子分離膜
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a structural sectional view of a semiconductor device of the present invention. FIG. 2 is a view showing one embodiment of a method of manufacturing a semiconductor device according to the present invention. FIG. 3 is a diagram showing a structural cross-sectional view of a conventional semiconductor device. [Description of Signs] 1 P-type semiconductor substrate 2 N-type impurity diffusion layer 3 gate oxide film 4 gate electrode 5 polycrystalline silicon film 6 buried contact layer 7 element isolation film 8 not in contact with buried contact layer 8 photoresist film 9 buried contact layer Isolation film 10 in contact with device Isolation film

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平3−114254(JP,A) 特開 昭62−57228(JP,A) 特開 昭59−75653(JP,A) 特開 昭63−200562(JP,A) 特開 平3−187224(JP,A)   ────────────────────────────────────────────────── ─── Continuation of front page       (56) References JP-A-3-114254 (JP, A)                 JP-A-62-57228 (JP, A)                 JP-A-59-75653 (JP, A)                 JP-A-63-200562 (JP, A)                 JP-A-3-187224 (JP, A)

Claims (1)

(57)【特許請求の範囲】 【請求項1】 埋め込みコンタクト層を含むMOSトラ
ンジスタを有する半導体装置の製造方法であって、 半導体基板に第1のLOCOS膜と前記第1のLOCO
S膜よりも幅の広い第2のLOCOS膜とを形成する工
程と、 前記第1のLOCOS膜と前記第2のLOCOS膜とに
挟まれた前記半導体基板の上にゲート絶縁膜を形成する
工程と、 前記ゲート絶縁膜のうち前記第2のLOCOS膜に近接
する部分と、前記第2のLOCOS膜の上部とを除去す
ることにより、前記ゲート絶縁膜に開孔部を形成する工
程と、 前記開孔部の内に導体層を形成する工程と、 前記開孔部の下方の前記半導体基板に前記埋め込みコン
タクト層を前記導体層から前記開孔部の下方の前記基板
に不純物を導入することにより形成する工程と、 前記埋め込みコンタクト層に近接する領域に前記MOS
トランジスタのソース領域又はドレイン領域のいずれか
一方となる第1の不純物領域を形成し、前記第1のLO
COS膜に近接する領域に前記ソース領域又はドレイン
領域の他方となる第2の不純物領域を形成する工程とを
有し、 前記埋め込みコンタクト層に隣接する前記第2のLOC
OS膜の幅が前記第1のLOCOS膜の幅より広い半導
体装置を得ることを特徴とする半導体装置の製造方法。
(57) A method of manufacturing a semiconductor device having a MOS transistor including a buried contact layer, wherein a first LOCOS film and a first LOCOS film are formed on a semiconductor substrate.
Forming a second LOCOS film wider than the S film; and forming a gate insulating film on the semiconductor substrate sandwiched between the first LOCOS film and the second LOCOS film Forming a hole in the gate insulating film by removing a portion of the gate insulating film close to the second LOCOS film and an upper part of the second LOCOS film; Forming a conductor layer in the opening; and introducing the buried contact layer into the semiconductor substrate below the opening from the conductor layer into the substrate below the opening. Forming the MOS transistor in a region adjacent to the buried contact layer.
Forming a first impurity region to be either a source region or a drain region of the transistor;
Forming a second impurity region serving as the other of the source region and the drain region in a region adjacent to a COS film, wherein the second LOC adjacent to the buried contact layer is provided.
A method for manufacturing a semiconductor device, comprising: obtaining a semiconductor device having an OS film having a width larger than that of the first LOCOS film.
JP18354992A 1992-07-10 1992-07-10 Method for manufacturing semiconductor device Expired - Fee Related JP3521921B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18354992A JP3521921B2 (en) 1992-07-10 1992-07-10 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18354992A JP3521921B2 (en) 1992-07-10 1992-07-10 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0629381A JPH0629381A (en) 1994-02-04
JP3521921B2 true JP3521921B2 (en) 2004-04-26

Family

ID=16137754

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18354992A Expired - Fee Related JP3521921B2 (en) 1992-07-10 1992-07-10 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3521921B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3652677B2 (en) 2002-09-20 2005-05-25 ファナック株式会社 Electric motor and interphase insulation method of electric motor

Also Published As

Publication number Publication date
JPH0629381A (en) 1994-02-04

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