JPH0113230B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and in particular, a method of manufacturing a semiconductor device suitable for use in manufacturing an integrated circuit in which complementary MOS transistors and double-gate MOS transistors are configured on the same chip. Regarding.

Currently, P-channel MOS transistors and
Complementary transistor (CMOS) ICs, which consist of N-channel MOS transistors, have the advantages of low power consumption and large noise margins.
It is very important to use it as a peripheral circuit for MOS transistors (SAMOS structure).

However, the manufacturing process for CMOS/EPROM requires an EPROM process in addition to the fact that the CMOS/IC is composed of a P-channel MOS transistor and an N-channel transistor.
It is the most complex of all MOS ICs.
In particular, CMOS/IC P-channel transistors and CMOS/IC N-channel transistors,
EPROM N-channel transistor source
The drain region must be etched or doped using a photolithographic PEP process, increasing the probability of unexpected mask resist pinholes or mask alignment errors.
This degrades the characteristics of CMOS/EPROM composite structures during manufacture, and is a factor that reduces product yields.

Hereinafter, a conventional manufacturing method will be explained with reference to FIGS. 1A to 1E. On the other hand, a conductive type semiconductor substrate, for example, P
Three field effect transistors, for example a CMOS transistor 2 and
A manufacturing method for forming SAMOS transistors 3 on the same chip will be explained. An n-type well region 5 is formed in the P-channel MOS type transistor region 4 of the CMOS transistor 2 formation region of the substrate 1. Thereafter, a field oxide film 6 is grown on the surface of the substrate 1, and a thin gate oxide film 7 having a thickness of, for example, 700 Å to 1000 Å is formed on the surface of the substrate 1 between the oxide films 6. Next, an impurity-containing layer, for example a polycrystalline silicon film 8 having a thickness of 3500 to 4500 Å, is formed on the oxide films 6 and 7. Note that this film 8 is doped with, for example, "phosphorus" as an n-type impurity by a normal diffusion method. Further, molybdenum silicide or tungsten silicide may be used instead of polycrystalline silicon.

After that, on the polycrystalline silicon layer 8, a layer with a thickness of about 700 ~
An oxide film 9 with a thickness of 1500 Å is grown, and an impurity-containing layer, for example, a polycrystalline silicon film 10 with a thickness of 3500 to 4500 Å, is formed on this oxide film 9. In this case as well, molybdenum silicide is used instead of polycrystalline silicon.
Tungsten silicide may also be used in the same manner as above. Next, an oxide film 11 having a thickness of about 500 to 1000 Å is also formed on this polycrystalline silicon film 10. next,
As shown in FIG. 1A, a resist mask 12 is formed in the area where the double gate is to be formed in the SAMOS transistor region 3 by photolithography. Then, by selectively etching up to the oxide film 9 using this mask 12, a control gate structure of a SAMOS transistor consisting of three layers of the oxide film 9, the polycrystalline silicon film 10, and the oxide film 11 is formed under the mask 12. Form a pattern as shown in Figure B. Furthermore, CMOS transistor formation region 2
Resist masks 13 and 14 are formed on each gate portion of the P channel and the N channel as shown in FIG. 1B. Using these masks 13 and 14 and the patterned oxide film 11 as masks, the polycrystalline silicon film 8 is selectively etched.
3 and 14, a resist mask 15 is placed on the surface of the P-channel MOS transistor formation region.
, and then an n-channel on the inner surface of the substrate 1.
MOS transistor source/drain region 16,
For example, _As is implanted into 17, 18, and 19 by ion implantation to form each source and drain as shown in FIG. 1C. After selectively etching away the resist mask 15, the n-channel
A resist mask 20 is formed on the surface of the MOS transistor formation region, and impurities, such as boron ions, are implanted into the source and drain regions of the P-channel MOS transistor formation region to form source and drain 21 and 22 as shown in FIG. 1E. After that, the resist mask 20 is removed and the CMOS-
They were manufacturing ICs with SAMOS composite structure.

However, this conventional manufacturing method requires a manufacturing method with as few steps as possible to obtain the desired yield and properties.

The present invention has been made in view of the above points, and by reducing the number of mask steps by one compared to the conventional manufacturing method described above, it not only simplifies the process, but also reduces misalignment during mask alignment and improves yield. The present invention provides an improved method of manufacturing a semiconductor device.

That is, in a method for manufacturing a semiconductor device in which an insulated gate field effect transistor and a double gate field effect transistor having a floating gate and a control gate in channels of opposite conductivity type are formed on the same semiconductor substrate,
A step of selectively forming a well region and a field insulating layer of one conductivity type on a semiconductor substrate of the other conductivity type, and forming a first insulating layer as a gate insulating film on the substrate surface of the element region separated by the field insulating layer. A step of forming a first conductive layer to serve as a gate electrode or a floating gate of each of the transistors on the entire surface of the substrate, a second insulating layer on the first conductive layer, and a step of forming a first conductive layer on the entire surface of the substrate. a step of sequentially forming a second conductive layer and a third insulating layer to serve as a control gate of the double-gate field-effect transistor; and a step of forming the third insulating layer corresponding to a position where the gate structure of the double-gate field-effect transistor is planned to be formed. forming a first mask for photolithography on the layer, and selectively removing the third insulating layer, the second conductive layer, and the second insulating layer using the first mask; forming a control gate of the double gate field effect transistor, and forming a second mask for photolithography on the first conductive layer corresponding to a position where the insulated gate field effect transistor is to be formed. and this second mask and the remaining third mask.
forming a floating gate of the double gate field effect transistor by selectively removing the first conductive layer using the insulating layer as a mask; forming source and drain regions of the double gate field effect transistor by implanting impurity ions using the first conductive layer and the gate structure of the double gate field effect transistor as masks; forming a third mask for photolithography on the first conductive layer corresponding to the planned formation position of the gate structure of the field effect transistor and on the formation position of the double gate field effect transistor;
selectively removing the first conductive layer using a mask to form a gate electrode of the insulated gate field effect transistor; and implanting impurity ions using the third mask to form the gate electrode of the insulated gate field effect transistor. The present invention provides a method for manufacturing a semiconductor device, which includes a step of forming source and drain regions of a field effect transistor.

and using a first conductive layer remaining on a planned formation position of the insulated gate field effect transistor as a mask when forming the source and drain regions of the double gate field effect transistor, and a third mask. It is characterized in that it is used for etching the remaining first conductive layer and for forming the source and drain regions of the insulated gate field effect transistor.

Hereinafter, one embodiment of the present invention will be described in FIGS. 2A to 2E.
Explain with reference to. Note that the steps in FIG. 2 A and E are the same as those in the conventional FIG. 1 A and E described above, so their explanation will be omitted, and only the steps in FIG. 2 B, C, and D, which are different from the conventional one, will be explained in detail. do.
Further, the same parts as those in FIG. 1 will be described with the same reference numerals.

First, as shown in FIG. 2A, the same process as in FIG. 1A is performed, and then, as shown in FIG. The process up to the etching removal process is the same as the conventional method. After that, the source and drain regions of the MOS transistor of one channel are formed first. If this is made into an n-channel MOS transistor as shown in FIG. 1, when forming the resist mask 14 for forming the gate structure of this transistor, at the same time a resist mask 14 for covering the region of the other channel, the p-channel MOS transistor, is used. (Second mask) 30 is formed. After that, the exposed polycrystalline silicon film 8
is removed by etching to form a structure as shown in FIG. 2C. Thereafter, the masks 14 and 30 are removed, and impurities, such as
Each source and drain is formed by ion implantation of _As . In this state, one n-channel MOS transistor of CMOS transistor 2 and
This means that SAMOS transistor 3 has been formed.

Next, the other channel, i.e. the P channel
This is the formation of a MOS structure. Similarly, in this step, as shown in FIG. 2D, a resist mask 20 for covering the region of the N-channel MOS transistor is formed at the time of forming the resist mask 31 for forming the gate of the P-channel MOS transistor. Then, by selectively etching the polycrystalline silicon film 8 using these masks (third masks) 31 and 20, a gate electrode is formed. Then mask 3
Well area 5 with 1 and 20 left as they are.
Impurities are added to the source/drain regions 21 and 22 within the
For example, each source/drain is formed by ion implantation of boric acid. In this way, a P-channel MOS transistor and an N-channel MOS transistor are placed on the substrate 1.
Form a transistor. After this, the mask 31,
By removing 20, a structure similar to that shown in FIG. 1E can be formed as shown in FIG. 2E.

As explained above, according to the method of the present invention, the number of mask steps can be reduced by one, which not only simplifies the manufacturing process but also reduces misalignment defects during mask alignment, resulting in semiconductor devices with high yield. A manufacturing method can be obtained.

In the above embodiment, the present invention is applied to an integrated circuit with a composite structure of a CMOS structure and a SAMOS structure. However, special consideration should be given to the formation of a MOS transistor of the same conductivity type as a SAMOS transistor. There is no need to pay for this, and it can be done in a part of the SAMOS transistor manufacturing process. Therefore, whether or not there is a MOS transistor of the same conductivity type as the SAMOS transistor described above has no direct bearing on the essence (features) of the present invention. is irrelevant. Therefore, it goes without saying that the present invention can also be applied to the case where a MOS transistor and a SAMOS transistor with a channel of the opposite conductivity type are formed in the same semiconductor device.

[Brief explanation of drawings]

FIGS. 1A to 1E are cross-sectional views of elements by process to explain the conventional manufacturing method, and FIGS.
FIG. 3 is a cross-sectional view of an element by process for explaining an example applied to a CMOS-SAMOS composite structure IC manufacturing method. 1...Substrate, 2...CMOS transistor, 3
...SAMOS transistor, 6, 7, 9, 11...
...Oxide film, 8,10...Polycrystalline silicon film, 3
0, 14, 31, 20...Resist mask, 2
1, 22, 16, 17, 18, 19... Source
drain area.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor device in which an insulated gate field effect transistor and a double gate field effect transistor having a floating gate and a control gate in opposite conductivity type channels are formed on the same semiconductor substrate, A step of selectively forming a well region and a field insulating layer of one conductivity type on a semiconductor substrate of the other conductivity type, and forming a first insulating layer as a gate insulating film on the substrate surface of the element region separated by the field insulating layer. A step of forming a first conductive layer to serve as a gate electrode or a floating gate of each of the transistors on the entire surface of the substrate, a second insulating layer on the first conductive layer, and a step of forming a first conductive layer on the entire surface of the substrate. The second gate serves as the control gate of the heavy gate field effect transistor.
a conductive layer and a third insulating layer, and forming a first mask for photolithography on the third insulating layer corresponding to the position where the gate structure of the double gate field effect transistor is to be formed. The step of forming the third insulating layer and the first mask,
forming a control gate of the double gate field effect transistor by selectively removing the second conductive layer and the second insulating layer, and corresponding to a planned formation position of the insulated gate field effect transistor; forming a second mask for photolithography on the first conductive layer, and selectively removing the first conductive layer using the second mask and the remaining third insulating layer as masks; forming a floating gate of the double gate field effect transistor by removing the first conductive layer remaining at the intended formation position of the insulated gate field effect transistor and the second conductive layer of the double gate field effect transistor; forming the source and drain regions of the double gate field effect transistor by implanting impurity ions using the gate structure as a mask; A third layer for photolithography is formed on the conductive layer and on the formation location of the double gate field effect transistor.
forming a mask, selectively removing the first conductive layer using the third mask to form a gate electrode of the insulated gate field effect transistor, and using the third mask. 1. A method of manufacturing a semiconductor device, comprising the step of implanting impurity ions to form source and drain regions of the insulated gate field effect transistor. 2. The method of manufacturing a semiconductor device according to claim 1, wherein each of the first and second conductive layers is made of impurity-doped polycrystalline silicon, molybdenum silicide, or tungsten silicide.