JPH08181223A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To scale down the cell size of a transistor largely by etching a conductive layer and leaving the conductive layer so as to be superposed to a silicon oxide film, in which the film thickness of the lower sections of both ends is increased for a specified area. CONSTITUTION: Each gate electrode of high breakdown-strength transistor sections in polysilicon films 10 is patterned so that both ends are overlapped approximately 1μm to third silicon oxide films 9, and patterned so that the polysilicon films 10 are formed so as to be overlapped approximately 1μm on active regions even in the boundary regions of the active regions from field oxide film edges 14. The gate electrodes are used as the masks of ion implantation for forming high-concentration impurity regions 11. Accordingly, the yield of the high breakdown-strength transistor is improved largely without increasing junction breakdown strength.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a high breakdown voltage transistor.

[0002]

2. Description of the Related Art At present, with the increase in demand for liquid crystal drivers and vehicle-mounted LSIs, development of semiconductor devices such as CMOS in which high breakdown voltage transistors are on-chip is in progress. Since a high voltage of 20 to 60 V is applied to the drain and the gate of the high breakdown voltage transistor, various devises have been made in the structure, and from now on, the cost increase from the normal CMOS process can be suppressed and the high breakdown voltage transistor can be suppressed. The miniaturization of is required.

The first conventional technique will be described with reference to the flow chart of FIG.

First, a silicon oxide film 22 and a silicon nitride film 23 are formed in a predetermined region of the P-type silicon substrate 21 so that a region where the field oxide film 25 is formed is exposed.
To form an oxidation resistant film (FIG. 5A).

Next, a low-concentration N-type impurity such as phosphorus is selectively dosed at a dose of 1 × 10 7 only in a region to be an electric field relaxation region (n ⁻ region) 24 in a high breakdown voltage transistor.
Ion implantation is performed at about ¹² ions / cm ² . After that, the field oxide film 25 is formed by the locos oxidation method using a known technique (FIG. 5B).

Next, after removing the silicon nitride film 23 and the silicon oxide film 22, the film thicknesses of the gate oxide film 27b in the 5V system transistor (low breakdown voltage transistor) portion and the gate oxide film 27a in the high breakdown voltage transistor portion are changed. Then, a polysilicon gate 26 is formed in each of them (FIG. 5).
(C)).

Next, using the polysilicon gate 26 and the field oxide film 25 as a mask, a high-concentration N-type impurity (for example, arsenic) is dosed at 1 × 10 ¹⁶ ions / cm 2.
^Then , ion implantation is performed to form a high concentration impurity region 28 which will be a source region and a drain region (FIG. 5).
(D)).

As a second conventional technique, as shown in FIG. 6, a gate insulating film (a silicon oxide film 25, a silicon nitride film 29, a silicon film) under a predetermined region on both ends of a polysilicon film 26 to be a gate electrode. A technique for forming a high breakdown voltage transistor by increasing the film thickness of the oxide film 30) is disclosed in JP-A-64-90562.

[0009]

In the above-mentioned first prior art, since the high breakdown voltage transistor forms the low concentration impurity layer under the field oxide film as the electric field relaxation layer, the high heat treatment step at the time of forming the field oxide film is performed. As a result, the electric field relaxation layer has a large lateral spread, and it is necessary to increase the gate length of the transistor. In addition, the size of the electric field relaxation layer requires an alignment margin when forming the gate electrode.

Due to these problems, in the prior art, the area of the high breakdown voltage transistor is remarkably increased. In addition, since the high-concentration impurity regions in the source region and the drain region are in a shape of being in direct contact with the edge portion of the field oxide film, the influence of the disorder (defect) of the silicon crystal due to the stress generated when the field oxide film is formed There is a problem in that it is easily received and the frequency of breakdown voltage is high.

Further, Japanese Unexamined Patent Application Publication No. Sho 6 (1994) which describes the second prior art
4-90562 does not describe whether the ends of the high-concentration regions in the source region and the drain region are apart from the ends of the field oxide film by a predetermined distance, and the above problems are solved. Not not.

An object of the present invention is to provide a method of manufacturing a semiconductor device in which the cell size of a transistor is significantly reduced as compared with the conventional one, the junction breakdown voltage is improved, and the yield of high breakdown voltage transistors is improved.

[0013]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising a step of forming an element isolation region on a semiconductor substrate by a field oxide film, and a predetermined film thickness in an activation region. Forming a silicon oxide film, and then forming a silicon nitride film on a part of a region to be a gate electrode, and performing ion implantation with the silicon nitride film as a mask to reduce the concentration in the source region and the drain region. A step of forming an impurity region, a step of increasing the thickness of the silicon oxide film other than under the silicon nitride film to a predetermined thickness by oxidation, a step of removing the silicon nitride film and depositing a conductive layer on the entire surface And a step of etching the conductive layer, leaving the conductive layer such that the lower ends of both ends overlap with the silicon oxide film whose thickness has been increased in the above step by a predetermined area, and A step of leaving the conductive layer only in a predetermined area from the edge of the field oxide film in the activated area, and ion implantation using the patterned gate electrode material as a mask to form a high concentration impurity area in the source area and the drain area. And a step of forming.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including a step of forming an element isolation region on a semiconductor substrate with a field oxide film, and a silicon oxide film having a predetermined thickness in the activation region. After forming, a step of forming a silicon nitride film on a part of a region to be a gate electrode, and ion implantation using the silicon nitride film as a mask,
Forming a low concentration impurity region in the source region and the drain region, increasing the film thickness of the silicon oxide film other than under the silicon nitride film to a predetermined film thickness by oxidation, and removing the silicon nitride film. A step of depositing a conductive layer on the entire surface, and then depositing a first insulating film having a predetermined thickness on the entire surface, and etching the first insulating film and the conductive layer so that lower end portions of the step The first insulating film and the conductive layer are left so as to overlap with the silicon oxide film whose thickness has been increased by a predetermined area, and only a predetermined area from the edge of the field oxide film to the activation area. A step of leaving the first insulating film and the conductive layer, and ion implantation using the patterned gate electrode material as a mask to perform high-concentration impurity regions in the source region and the drain region. And a step of forming a second insulating film on the entire surface, and then a sidewall is formed on the side wall of the gate electrode by etching back to contact the metal electrode with the source region and the drain region in a self-aligned manner. The method for manufacturing a semiconductor device according to claim 1, further comprising a step.

[0015]

With the above structure, the high-concentration impurity region in the source / drain region is separated from the edge of the field oxide film by a predetermined distance to form a high breakdown voltage transistor having a reduced size.

[0016]

EXAMPLES The present invention will be described in detail below based on examples.

FIG. 1 shows a high breakdown voltage CMO according to an embodiment of the present invention.
FIG. 3 is a diagram showing a process of forming S and a low breakdown voltage CMOS on the same substrate, FIG. 2 is a final process sectional view of the same process of another embodiment of the present invention, and FIG. FIG. 4 is a plan view of a breakdown voltage transistor, and FIG. 4 is a diagram for explaining the effect of the present invention.

1 to 3, 1 is a P-type silicon substrate,
2 is an N-type well region, 3 is a field oxide film, 4 is a first
Silicon oxide film, 5 is a second silicon oxide film, 6 is a silicon nitride film, 7 is a resist, 8a and 8b are low concentration impurity regions in the source and drain regions, and 9 is a third
Silicon oxide film, 10 is a polysilicon film, 11a, 1
1b is a high concentration impurity region in the source region and the drain region, 12 is an interlayer insulating film, 13 is a metal wiring, 14 is a field oxide film edge, 15 is a sidewall, 16
Indicates a fourth silicon oxide film.

Next, a process of forming the high breakdown voltage CMOS and the low breakdown voltage CMOS of the embodiment of the present invention on the same substrate will be described with reference to FIG. The present invention is not limited to the process of forming the high breakdown voltage CMOS and the low breakdown voltage CMOS on the same substrate, but can be applied to the process of forming the high breakdown voltage transistor.

First, the impurity concentration is 1 × 10 ¹⁵ ions /
An N-type well region 2 is formed in a P-type silicon substrate 1 of about cm ³ and then a field oxide film 3 is formed to form a high breakdown voltage N channel transistor portion, a high breakdown voltage P channel transistor portion, and a low breakdown voltage N channel transistor portion. And the active region of the low breakdown voltage P-channel transistor portion is separated.

Next, after forming an oxide film on the entire surface in a region (active region) other than the field oxide film 3 by a thermal oxidation method, the oxide film in the low breakdown voltage CMOS portion is removed, and the first breakdown voltage is formed in the high breakdown voltage CMOS portion. Of the gate oxide film 4 of FIG.
A second gate oxide film 5 having a thickness of about 10 to 20 nm is formed on the S portion. At this time, it is necessary to set the initial film thickness of the first gate oxide film 4 so that the final film thickness of the first gate oxide film 4 becomes 50 to 100 nm. Then, a silicon nitride film 6 is formed on the entire surface so as to have a film thickness of about 50 to 100 nm.

Next, in a photoresist process using the resist 7, the silicon nitride film on the regions which will be the source region and the drain region of the N-channel high breakdown voltage transistor portion of the P-type silicon substrate 1 is removed to adjust the dose amount. 5 x 10 ¹² io
Phosphorus is ion-implanted at ns / cm ² and acceleration energy of 120 keV to form an N-type low-concentration impurity region 8a (FIG. 1A). Then, in the same process, the silicon nitride film on the regions to be the source region and the drain region of the P-channel high breakdown voltage transistor in the N-type well region is removed, and the dose amount is 1 × 10 ¹³ ions / cm ² . Boron is ion-implanted at an acceleration energy of 80 keV to form a P-type low-concentration impurity region 8b.

Next, the high breakdown voltage transistor portion forming region is oxidized to form the first silicon oxide film 4 in the region other than the gate electrode region as the third silicon oxide film 9 having a film thickness of about 200 to 300 nm (FIG. 1 (b)).

Next, after removing all of the silicon nitride film 6, an N ⁺ -doped polysilicon film 10 to be a gate electrode is formed on the entire surface to a thickness of about 200 to 400 nm. Then, patterning into a predetermined shape to form a gate electrode, and
The second silicon oxide film 5 and the third silicon oxide film 9 in the region where the polysilicon film 10 is not formed are removed (FIG. 1C). As shown in FIG. 3, a plan view of the high breakdown voltage transistor at this time is such that the high concentration impurity regions 11 in the source region and the drain region are surrounded by the polysilicon film 10, and the field oxide film edge 14 is below the polysilicon film 10. It is located in.

Further, each gate electrode of the high breakdown voltage transistor portion is patterned so that both ends thereof overlap with the third silicon oxide film 9 by about 1 μm, and the field oxide film edge 14 and the active region boundary region are also formed. Patterning is performed so that the polysilicon film 10 is formed so as to overlap the active region by about 1 μm. When the breakdown voltage is 60 V, both the overlap amount A at the gate electrode portion and the overlap amount B at the boundary region need to be about 1 μm. For example, when the breakdown voltage is 40 V, 0.8 μm. If the breakdown voltage is 20 V, the overlap amounts A and B of about 0.5 μm (see FIG.
A, B) in the above are required. Further, the overlap amount A and the overlap amount B do not necessarily have to be the same, and can be appropriately changed according to the required breakdown voltage.

As described above, the field oxide film edge 14 is formed.
Since the polysilicon film 10 is also formed in the boundary region between the active region and the active region, it serves as an ion implantation mask for forming the high concentration impurity region 11 in the source region and the drain region in the next step, and serves as the source region and the drain region. A low-concentration impurity region 8 is formed between the end of the high-concentration impurity region 11 and the edge 14 of the field oxide film.

Offset length in FIG. 4 (A in FIG. 2)
It is a figure which shows the relationship between a withstand voltage. As shown in FIG. 4, as compared with the case where the field oxide film edge 14 shown by the dotted line and the high-concentration impurity region 11 in the source region and the drain region are in contact (B = 0 μm), the field oxide film edge 14 shown by the solid line is shown. The breakdown voltage is improved when there is a distance (B> 0 μm) between the high-concentration impurity region 11 serving as the source region and the drain region. When B> 0 (solid line portion), the value of A and the value of B are made equal.

Next, high concentration impurity regions 11a and 11b in the source region and the drain region are formed by ion implantation. After that, an interlayer insulating film 12 is formed, a contact hole is opened, and a metal electrode 13 is formed (FIG. 1).
(D)).

As another embodiment of the present invention, after the step shown in FIG. 1B, the silicon nitride film is removed,
N ⁺ doped polysilicon film 10 to be a gate electrode on the entire surface
For about 200 to 400 nm, and then an insulating film such as a fourth silicon oxide film 16 is formed on the entire surface for 200 nm to 300 n.
Then, the gate electrode is formed in a predetermined pattern.

Next, after forming the high-concentration impurity regions 11 in the source region and the drain region, an insulating film such as a silicon oxide film is grown on the entire surface by 250 to 400 nm and etched back by anisotropic dry etching to form a gate electrode. The sidewall 15 having a width of 250 to 300 nm is formed on the sidewall. After that, a contact hole is opened only on the gate electrode by the photolithography technique to form the metal electrode 13. At this time, self-contact is made with the metal electrodes in the source region and the drain region of each transistor (FIG. 2).

[0031]

As described above in detail, by using the present invention, by arranging the polysilicon of the gate electrode material also in the boundary region between the active region of the transistor and the field oxide film, a high concentration can be obtained. Since the high-concentration impurity regions in the source region and the drain region do not come into contact with the ends of the field oxide film, the yield of the high breakdown voltage transistor can be significantly improved without improving the junction breakdown voltage.

Further, the field oxide film is not used in the electric field relaxation region of the high breakdown voltage transistor, and a thick oxide film for relaxing the electric field concentration at the end portion of the gate electrode when patterning the polysilicon film as the gate electrode material is used. By etching simultaneously with polysilicon, as shown in FIG. 7, it is possible to significantly reduce the cell size of the high breakdown voltage transistor as compared with the conventional technique without adding a special process. For example, in FIG. 7, the size (the length between the end portions of the field oxide film on both sides) C of the high breakdown voltage transistor in the prior art is 15 μm (FIG. 7A).
On the other hand, the size D of the high breakdown voltage transistor according to the present invention is 11 μm, and by using the present invention, the transistor size can be reduced to about 2/3 as compared with the conventional technique.

Further, by using the present invention described in claim 2, it is not necessary to perform mask alignment in forming a contact hole for connecting the source region and the drain region to the metal electrode, and self-alignment is possible. Since it can be formed, the number of steps can be reduced and the yield can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a process of forming a high breakdown voltage CMOS and a low breakdown voltage CMOS on the same substrate according to an embodiment of the present invention.

FIG. 2 is a final process sectional view of the same process of another embodiment of the present invention.

FIG. 3 is a plan view of a high breakdown voltage transistor portion according to the present invention.

FIG. 4 is a diagram for explaining an effect of the present invention.

FIG. 5 is a diagram showing a process of forming a conventional high breakdown voltage transistor and a low breakdown voltage transistor on the same substrate.

FIG. 6 is a structural cross-sectional view of another conventional high breakdown voltage transistor.

FIG. 7 is a diagram provided for a comparative explanation of a conventional technique and the present invention.

[Explanation of symbols]

 1 P-type silicon substrate 2 N-type well region 3 Field oxide film 4 First silicon oxide film 5 Second silicon oxide film 6 Silicon nitride film 7 Resist 8 Low concentration impurity region 9 Third silicon oxide film 10 Polysilicon film 11 high-concentration impurity region 12 interlayer insulating film 13 metal electrode 14 field oxide film edge 15 sidewall 16 fourth silicon oxide film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication location H01L 21/316 29/78 H01L 21/94 A 27/08 321 D 29/78 301 G

Claims (2)

[Claims] 1. A step of forming an element isolation region by a field oxide film on a semiconductor substrate, and a part of a region which becomes a gate electrode after a silicon oxide film having a predetermined thickness is formed in an activation region. A step of forming a silicon nitride film thereon, a step of forming a low concentration impurity region in a source region and a drain region by performing ion implantation using the silicon nitride film as a mask, and a step of oxidizing the silicon other than under the silicon nitride film. A step of increasing the film thickness of the oxide film to a predetermined film thickness, a step of removing the silicon nitride film and depositing a conductive layer on the entire surface, and a step of depositing a conductive layer on both sides so that the lower end portions of the film are formed by the above step. The conductive layer is left so as to overlap with the thickened silicon oxide film by a predetermined area, and a predetermined area is formed in the activation region from the edge of the field oxide film. Semiconductor device characterized by including a step of leaving the conductive layer only in a region and a step of performing ion implantation using the patterned gate electrode material as a mask to form a high concentration impurity region in a source region and a drain region. Manufacturing method. 2. A step of forming an element isolation region by a field oxide film on a semiconductor substrate, and a part of a region which becomes a gate electrode after a silicon oxide film having a predetermined thickness is formed in an activation region. A step of forming a silicon nitride film thereon, a step of forming a low concentration impurity region in a source region and a drain region by performing ion implantation using the silicon nitride film as a mask, and a step of oxidizing the silicon other than under the silicon nitride film. A step of increasing the thickness of the oxide film to a predetermined thickness; a step of removing the silicon nitride film, depositing a conductive layer on the entire surface, and then depositing a first insulating film of a predetermined thickness on the entire surface. By etching the first insulating film and the conductive layer, the first insulating film and the conductive layer are overlapped with the silicon oxide film whose thickness is increased in the above step by a predetermined area. Leaving the film and the conductive layer, and said field oxide film edge from a predetermined region in the activation region of the first
Of the insulating film and the conductive layer, and a step of performing ion implantation using the patterned gate electrode material as a mask to form high-concentration impurity regions in the source region and the drain region, and the second insulating film over the entire surface. And depositing a side wall on the side wall of the gate electrode by etching back, and contacting the metal electrode with the source region and the drain region in a self-aligned manner. A method for manufacturing a semiconductor device as described above.