JPH04250668A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To highly integrate a semiconductor device by substantially increasing a gate width without increasing a planar size of a field effect transistor. CONSTITUTION:A recess 6 is formed on the surface of a semiconductor substrate 1 at least directly under a gate electrode 4 along a gate width direction, a recess region 7 is formed of the recess 6 thereby to increase the opposing size of the substrate 1, a gate silicon oxide film 3 in the gate width direction of the electrode 4, thereby substantially increasing the gate width. The manufacture of this semiconductor device includes a step of selectively etching the surface of a region to be formed with a field effect transistor of the substrate to form a recess region arranged with a plurality of recesses in the gate width direction, and a step of forming the gate electrode on the recess region.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a field effect transistor, and more particularly to a semiconductor device having an enlarged gate width of a field effect transistor and a method for manufacturing the same.

0002

[Prior Art] Conventional field effect transistors, especially MO
An example of an S-type field effect transistor (hereinafter referred to as MOSFET) is shown in FIG. The same figure (a) is a plan view, the same figure (
b) is an enlarged sectional view taken along the line B-B of (a). As shown in the figure, a semiconductor substrate 1 is separated into transistors by an element isolation silicon oxide film 2, a gate silicon oxide film 3 is formed on the entire surface, and a gate electrode 4 is formed on this. Further, source/drain regions 5 are provided on both sides of the gate electrode 4.
form. In such a MOSFET, the gate width W
is a portion along the lower surface of the gate electrode 4 sandwiched between the element isolation silicon oxide films 2.

0003

[Problem to be solved by the invention] This conventional MOSFE
At T, the length of the gate width W is directly tied to the vertical dimension of the transistor. Generally, the drain current of a MOSFET is proportional to W/L, which is the ratio of gate width W to gate length L. Therefore, in order to obtain a large drain current, it is necessary to increase the gate width W, which results in an increase in the transistor size and further a decrease in the degree of integration. An object of the present invention is to provide a semiconductor device in which the gate width can be increased without reducing the degree of integration, and a method for manufacturing the same.

0004

[Means for Solving the Problems] A semiconductor device of the present invention includes:
At least directly under the gate electrode of the field effect transistor,
The semiconductor substrate has a structure in which a concave region is formed in an uneven manner on the surface. The method for manufacturing a semiconductor device of the present invention also includes a step of selectively etching the surface of a region of a semiconductor substrate in which a field effect transistor is to be formed to form a recessed region in which a plurality of recesses are arranged; The method includes a step of forming a gate electrode.

[0005]

According to the semiconductor device of the present invention, the recessed region formed directly under the gate electrode increases the opposing dimension in the gate width direction between the semiconductor substrate and the gate electrode, thereby substantially increasing the gate width.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 shows an embodiment of the present invention, in which (a) is a plan view;
(b) is an enlarged sectional view taken along line A-A in (a). As shown in the figure, a semiconductor substrate 1 is separated into transistors by an element isolation silicon oxide film 2, a gate silicon oxide film 3 is formed on the entire surface, and a gate electrode 4 is formed on this. Further, source/drain regions 5 are formed on both sides of the gate electrode 4. Directly below the gate electrode 4 and in a region protruding to both sides along the gate electrode 4, a recessed region 7 having a plurality of semicircular recesses 6 arranged in the gate width direction is formed on the surface of the semiconductor substrate 1. ing. Then, the gate silicon oxide film 3 is formed on this concave region 7, and the gate electrode 4 is formed thereon.

According to this configuration, the contact area of the semiconductor substrate 1, the gate silicon oxide film 3, and the gate electrode 4 in the gate width direction is increased by the recessed portion 6 in the recessed region 7, and as a result, the planar dimensions of the MOSFET are increased. The effective gate width W can be increased without any problems. This point will be explained in detail later. Note that the concave region 7 protrudes from the gate electrode 4 in the gate length direction, but the dimension of this protrusion is determined by the overlapping accuracy of the gate electrode 4 and the concave region 7 during manufacturing. If this overlay accuracy is high, the protrusion dimension may be zero.

Next, a method for manufacturing the MOSFET shown in FIG. 1 will be explained using FIG. 2. Note that this embodiment is an example applied to an N-channel MOSFET. First, the same figure (a)
An element isolation silicon oxide film 2 is formed by selective oxidation on a semiconductor substrate 1 doped with P-type impurities, as shown in FIG. Next, as shown in FIG. 3B, a photoresist mask 8 having a plurality of openings arranged along the gate width direction is formed by photolithography. After that, HF+HN
The surface of the semiconductor substrate 1 is isotropically etched by wet etching using O3 or the like to form a plurality of recesses 6 arranged in the gate width direction, thereby forming a recessed region 7. Since this etching is not anisotropic etching using plasma, the semiconductor substrate 1 is etched using reactive ions, etc.
No damage to.

Next, as shown in FIG. 2C, the photoresist 8 is removed and a gate silicon oxide film 3 is formed on the entire surface of the semiconductor substrate 1. Next, the threshold voltage (V
t) Boron ions are implanted vertically into the semiconductor substrate 1 as channel doping for control. Note that damage caused during ion implantation can also be removed by peeling off the gate silicon oxide film 3 once after ion implantation, and oxidizing it again to form it again. Thereafter, as shown in FIG. 4(d), a gate electrode 4 is formed on the recessed region 7 with the gate silicon oxide film 3 interposed therebetween. Thereafter, an N-type impurity (for example, arsenic) is introduced into the semiconductor substrate 1 by a self-alignment method using the gate electrode 4.
Type source/drain regions 5 are formed, and the structure shown in FIG. 1 is formed. Although not shown, an interlayer insulating film is then further deposited, and the transistors are connected with metal wiring such as aluminum, to complete the desired integrated circuit.

[0010] In the MOSFET configured in this way,
In each concave portion 6 of the concave region 7, the length of the surface in the gate width direction, that is, the linear dimension indicated by L in FIG. Arc dimension 1.57
It turns out that the length becomes longer by 0.57L. Therefore, as shown in FIG. 4, the concave portion 6 of the concave region 7 is made into an arc-shaped concave portion with a width of 1 μm and a pitch of 2.5 μm.
If the pieces are lined up and the depth is 0.5 μm, then 0.5
The length becomes longer by 7×0.2×8=0.91 μm. As a result, for example, a conventional MOSFE with a gate width of 10 μm
When forming T, the planar dimension of the gate width can be designed to be smaller by this amount, and the planar dimension of the gate width can be reduced to 9.09 μm, and the degree of integration of the MOSFET can be increased.

[0011] The above embodiment is an N-channel MOSFET.
Although this is an example applied to a P-channel MOSFET, it can be similarly applied to a P-channel MOSFET. Also, III such as GaAs
A junction gate field effect transistor using a -V group semiconductor can also be easily applied by omitting the step of forming an oxide film under the gate electrode. Furthermore, although the wet etching method is used to form the concave region in the above embodiment, if the semiconductor substrate is activated by heat treatment to recover damage to the semiconductor substrate after the etching process, the processing dimensions can be controlled. Anisotropic etching using dry etching with good properties is also applicable. In this case, the recess can be formed into a rectangular shape, making it possible to further increase the gate width.

0012

[Effects of the Invention] As explained above, the present invention forms a concave region directly under the gate electrode to enlarge the facing dimension between the semiconductor substrate and the gate electrode in the gate width direction, so that the same gate width can be obtained. The plane dimension of the gate width can be reduced accordingly, and the degree of integration of the field effect transistor can be increased. Furthermore, when forming the recessed region, it is only necessary to selectively etch the surface of the region of the semiconductor substrate where the field effect transistor is to be formed, so it is only necessary to add one etching step to the conventional manufacturing process of the field effect transistor. , it becomes possible to easily manufacture highly integrated field effect transistors.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, (a) is a plan view, (a) is a plan view;
b) is an enlarged sectional view taken along line A-A.

2A to 2D are cross-sectional views showing the method for manufacturing the semiconductor device of FIG. 1 in order of steps;

FIG. 3 is a diagram for explaining the effects of the present invention, in which (a) is a cross-sectional view of a flat portion, and (b) is a cross-sectional view of a recessed portion.

FIG. 4 is a schematic cross-sectional view for explaining the effects of the present invention.

FIG. 5 shows a conventional semiconductor device, in which (a) is a plan view and (a) is a plan view;
b) is an enlarged sectional view taken along the line BB.

[Explanation of symbols]

1 Semiconductor substrate 3 Gate silicon oxide film 4 Gate electrode 5 Source/drain region 6 Recess 7 Concave area 8 Photoresist

Claims (2)

[Claims] 1. In a semiconductor device having a field effect transistor in which a gate electrode is formed on a semiconductor substrate, at least a surface of the semiconductor substrate immediately below the gate electrode is provided with a concave region having an uneven shape along the gate width direction. A semiconductor device characterized by: 2. A step of selectively etching the surface of a region of a semiconductor substrate where a field effect transistor is to be formed to form a recessed region in which a plurality of recesses are arranged in the gate width direction, and forming a gate electrode on the recessed region. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device.