JP2707977B2 - MOS type semiconductor device and method of manufacturing the same - Google Patents

MOS type semiconductor device and method of manufacturing the same

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Publication number
JP2707977B2
JP2707977B2 JP6232283A JP23228394A JP2707977B2 JP 2707977 B2 JP2707977 B2 JP 2707977B2 JP 6232283 A JP6232283 A JP 6232283A JP 23228394 A JP23228394 A JP 23228394A JP 2707977 B2 JP2707977 B2 JP 2707977B2
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JP
Japan
Prior art keywords
gate electrode
film
region
electrode material
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP6232283A
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Japanese (ja)
Other versions
JPH0878672A (en
Inventor
和之 水嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6232283A priority Critical patent/JP2707977B2/en
Publication of JPH0878672A publication Critical patent/JPH0878672A/en
Priority to US08/962,807 priority patent/US5828104A/en
Application granted granted Critical
Publication of JP2707977B2 publication Critical patent/JP2707977B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28105—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、ＭＯＳ型半導体装置お
よびその製造方法に関し、特に非対称ＬＤＤ（Lightly
Doped Drain ）構造を持つトランジスタを含むＭＯＳ型
半導体装置およびその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device and a method of manufacturing the same, and more particularly, to an asymmetric LDD (Lightly LDD).
The present invention relates to a MOS semiconductor device including a transistor having a Doped Drain structure and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】ＭＯＳ型半導体装置の構成要素であるＭ
ＯＳ型トランジスタの動作速度の高速化は主にゲート酸
化膜の薄膜化とゲート長の縮小によって達成されてき
た。すなわち、ＭＯＳ型半導体装置の寸法を比例縮小し
てきたわけであるが、ゲート長が１μｍ以下になるとス
レッショルド電圧がドレイン電圧に影響され変動するシ
ョートチャネル効果が顕著になる。2. Description of the Related Art M is a constituent element of a MOS type semiconductor device.
The increase in operating speed of the OS type transistor has been achieved mainly by reducing the thickness of the gate oxide film and reducing the gate length. That is, although the dimensions of the MOS type semiconductor device have been proportionally reduced, when the gate length becomes 1 μm or less, the short channel effect in which the threshold voltage is influenced by the drain voltage and fluctuates becomes remarkable.

【０００３】このショートチャネル効果を回避するため
には、チャネル部の不純物濃度を上げ、ドレイン拡散層
からの空乏層の広がりを抑える必要がある。一方、電源
電圧については半導体装置の使用されるセットの電源電
圧を自由に設定できないことから、ある程度の制約を受
け比例的には低減できないため、チャネル部の不純物濃
度の上昇とともに、ドレイン領域近傍の電界集中が顕著
になりホットキャリアが生じて、デバイスの特性を劣化
させるという問題がでてくる。In order to avoid this short channel effect, it is necessary to increase the impurity concentration in the channel portion and suppress the spread of the depletion layer from the drain diffusion layer. On the other hand, since the power supply voltage of the set used in the semiconductor device cannot be freely set, the power supply voltage cannot be reduced proportionally due to some restrictions. There is a problem that electric field concentration becomes remarkable and hot carriers are generated, thereby deteriorating device characteristics.

【０００４】この課題に対処するため、従来のＭＯＳ型
半導体装置では対称ＬＤＤ構造を採用していた。図３
は、従来の対称型ＬＤＤ構造を有するＭＯＳ型トランジ
スタの断面図である。ここで、１ａはシリコン基板、２
はゲート酸化膜、３はゲート電極、４は低濃度不純物領
域、５は高濃度不純物領域、６はゲート側壁絶縁膜であ
る。In order to address this problem, a conventional MOS semiconductor device employs a symmetric LDD structure. FIG.
1 is a sectional view of a conventional MOS transistor having a symmetrical LDD structure. Here, 1a is a silicon substrate, 2
Is a gate oxide film, 3 is a gate electrode, 4 is a low concentration impurity region, 5 is a high concentration impurity region, and 6 is a gate side wall insulating film.

【０００５】このＭＯＳ型半導体装置は次のように形成
される。シリコン基板１ａ上に例えば熱酸化法によりゲ
ート酸化膜２を形成し、不純物を高濃度にドープした多
結晶シリコン膜あるいは多結晶シリコン膜と金属シリサ
イド膜との積層体からなるゲート電極３を形成する。こ
のゲート電極をマスクに不純物イオンを注入して低濃度
不純物領域４を形成し、次に、全面に化学気相成長（Ｃ
ＶＤ）法などにより酸化膜を堆積し続いて異方性エッチ
ングを行うことによりゲート側壁絶縁膜６を形成する。
次に、ゲート電極３およびゲート側壁絶縁膜６をマスク
として不純物をイオン注入して高濃度不純物領域５を形
成する。This MOS type semiconductor device is formed as follows. A gate oxide film 2 is formed on a silicon substrate 1a by, for example, a thermal oxidation method, and a gate electrode 3 made of a polycrystalline silicon film doped with impurities at a high concentration or a laminate of a polycrystalline silicon film and a metal silicide film is formed. . Impurity ions are implanted using this gate electrode as a mask to form a low-concentration impurity region 4, and then a chemical vapor deposition (C
A gate sidewall insulating film 6 is formed by depositing an oxide film by the VD) method or the like and subsequently performing anisotropic etching.
Next, impurities are ion-implanted using the gate electrode 3 and the gate sidewall insulating film 6 as a mask to form the high-concentration impurity regions 5.

【０００６】この例では、ＬＤＤとなる低濃度不純物領
域はソース、ドレインの両方に形成される。しかし、本
来不要なソース側の低濃度不純物領域はソース抵抗を増
大させ電流駆動能力を低下させるという問題を起こす。
この対称型ＬＤＤ構造を持つＭＯＳ型半導体装置のこの
欠点を改善するため、ソース側の低濃度不純物領域を形
成せず、あるいは低濃度不純物領域を極めて狭くし、ソ
ース側のみ寄生抵抗を低減するという非対称ＬＤＤ型Ｍ
ＯＳ型半導体装置が提案されている。In this example, the low-concentration impurity regions serving as the LDD are formed on both the source and the drain. However, a low-concentration impurity region on the source side that is not required originally causes a problem that the source resistance is increased and the current driving capability is reduced.
In order to remedy this drawback of the MOS type semiconductor device having the symmetrical LDD structure, the source side low-concentration impurity region is not formed or the low-concentration impurity region is made extremely narrow to reduce the parasitic resistance only on the source side. Asymmetric LDD type M
OS type semiconductor devices have been proposed.

【０００７】図４（ａ）〜（ｃ）は、非対称ＬＤＤ構造
を有するＭＯＳ型トランジスタの一般的な製造方法を示
す工程順断面図である。ｐ型シリコン基板１上に熱酸化
法でゲート酸化膜２を形成し、次いでゲート電極３をパ
ターニングする。ゲート電極３をマスクにイオン注入
し、ドレイン低濃度不純物領域４ａおよびソース低濃度
不純物領域４ｂを形成する〔図４（ａ）〕。FIGS. 4A to 4C are cross-sectional views in the order of steps showing a general method for manufacturing a MOS transistor having an asymmetric LDD structure. A gate oxide film 2 is formed on a p-type silicon substrate 1 by a thermal oxidation method, and then a gate electrode 3 is patterned. Using the gate electrode 3 as a mask, ions are implanted to form a low-concentration drain region 4a and a low-concentration source region 4b (FIG. 4A).

【０００８】フォトリソグラフィ技術により、ゲート電
極上にその端部が位置し、少なくともドレイン領域のＬ
ＤＤ形成部分を覆い、かつソース領域を露出するように
フォトレジスト７ｂを加工する。次いでフォトレジスト
７ｂに覆われていないソース領域に高濃度に不純物をイ
オン注入し、ソース高濃度不純物領域５ｂを形成する
〔図４（ｂ）〕。According to the photolithography technique, the end portion is located on the gate electrode, and at least L
The photoresist 7b is processed so as to cover the DD formation portion and expose the source region. Next, high-concentration impurities are ion-implanted into the source region not covered with the photoresist 7b to form a high-concentration source region 5b (FIG. 4B).

【０００９】フォトレジスト７ｂを除去し、続いて、全
面に酸化膜を堆積し、異方性エッチングを行うことによ
りゲート電極３の側部にゲート側壁絶縁膜６を形成す
る。次いで、ゲート電極３、ゲート側壁絶縁膜６をマス
クに不純物イオンを高濃度に注入してドレイン高濃度不
純物領域５ａを形成する〔図４（ｃ）〕。The photoresist 7b is removed, an oxide film is deposited on the entire surface, and anisotropic etching is performed to form a gate sidewall insulating film 6 on the side of the gate electrode 3. Next, impurity ions are implanted at a high concentration using the gate electrode 3 and the gate side wall insulating film 6 as a mask to form a drain high-concentration impurity region 5a (FIG. 4C).

【００１０】このような構造をとることにより、ドレイ
ン領域からの空乏層の広がりを抑えるようにチャネル領
域を高濃度化してパンチスルーやスレッショルド電圧変
動を抑制することが可能になるとともに、ドレイン端に
設けたＬＤＤ領域で電界集中を緩和しホットキャリアに
よる劣化を軽減するという本来のＬＤＤ構造の目的を達
成しつつ、ソース側における寄生抵抗を低減化し、電流
駆動能力の低下を抑えることができるようになる。By adopting such a structure, it becomes possible to increase the concentration of the channel region so as to suppress the spread of the depletion layer from the drain region and thereby suppress punch-through and threshold voltage fluctuation. In order to reduce the parasitic resistance on the source side and suppress the decrease in the current driving capability, while achieving the original purpose of the LDD structure of reducing the electric field concentration and reducing the deterioration due to hot carriers in the provided LDD region. Become.

【００１１】非対称ＬＤＤ構造をもつＭＯＳ型半導体装
置の製造方法はこの例以外にも多数提案されている。例
えば特開昭６３−１４２６７６号公報では低濃度不純物
領域のイオン注入を９０度より小さい角度で行い、高濃
度不純物領域形成のイオン注入を９０度より大きい角度
で行うことにより非対称構造を形成する方法が提案され
ている。同様に斜めイオン注入を利用した手法として
は、特開平４−２４５６４２号公報に記載されたものが
ある。Many other methods of manufacturing MOS type semiconductor devices having an asymmetric LDD structure have been proposed in addition to this example. For example, Japanese Patent Application Laid-Open No. 63-142676 discloses a method of forming an asymmetric structure by performing ion implantation of a low concentration impurity region at an angle smaller than 90 degrees and performing ion implantation of a high concentration impurity region at an angle larger than 90 degrees. Has been proposed. Similarly, a technique utilizing oblique ion implantation is described in Japanese Patent Application Laid-Open No. Hei 4-245652.

【００１２】また、特開昭６２−５８６８２号公報に記
載されたものでは、ゲート側壁絶縁膜を形成する際の異
方性エッチングを基本主面に対してある角度をもって行
うことにより、ゲート側壁絶縁膜の厚さをソース側で薄
く、ドレイン側で厚くし非対称構造を形成している。さ
らに、特開平２−１５８１４３号公報では、ゲート電極
のエッチングを行う際にマイクロローディング効果を利
用して、ゲート電極を、隣接したゲート電極のない部分
では垂直に、隣接したゲート電極のある部分ではテーパ
ー状に加工することにより非対称構造を得る手法が提案
されている。Further, in Japanese Patent Application Laid-Open No. Sho 62-58682, anisotropic etching at the time of forming a gate sidewall insulating film is performed at a certain angle with respect to the basic principal surface, so that the gate sidewall insulating film is formed. The film is thinner on the source side and thicker on the drain side to form an asymmetric structure. Further, in Japanese Patent Application Laid-Open No. 2-158143, a gate electrode is etched vertically by using a microloading effect when etching the gate electrode, in a portion without an adjacent gate electrode, and in a portion with an adjacent gate electrode. A method of obtaining an asymmetric structure by processing into a tapered shape has been proposed.

【００１３】[0013]

【発明が解決しようとする課題】図４に示した従来の非
対称ＬＤＤ構造をもつＭＯＳ型半導体装置の製造方法で
は、フォトレジスト７ｂの一端をゲート電極３上に位置
させることが要求される。しかしながら、２００〜４０
０ｎｍの厚さでかつハーフミクロン以下の幅に微細化さ
れたゲート電極上に精度よくフォトレジスト端を形成す
ることは非常に困難である。すなわち、ゲート電極段部
におけるフォトリソグラフィでの位置合わせ、現像での
フォトレジストの膜減り、フォトレジストのテーパー角
など極めて高度に制御しなければならない。In the conventional method of manufacturing a MOS type semiconductor device having an asymmetric LDD structure shown in FIG. 4, it is required that one end of a photoresist 7b be located on the gate electrode 3. However, 200-40
It is very difficult to accurately form a photoresist edge on a gate electrode that has a thickness of 0 nm and has a width of half a micron or less. That is, it is necessary to control the alignment by photolithography in the step portion of the gate electrode, reduce the thickness of the photoresist film during development, and control the taper angle of the photoresist to a very high degree.

【００１４】さらに、イオン注入角度を変更することに
より非対称ＬＤＤを実現しようとしている特開昭６３−
１４２６７６号公報、特開平４−２４５６４２号公報お
よびエッチングの際に基本主面に対してある角度を持っ
た異方性エッチングを行っている特開昭６２−５８６８
２号公報に記載された方法では、ＭＯＳ型半導体装置の
ソース、ドレインの方向を一意に決定する必要があり、
レイアウト設計の自由度が制限を受けるという欠点があ
った。Furthermore, Japanese Patent Application Laid-Open No. 63-63980 attempts to realize an asymmetric LDD by changing the ion implantation angle.
No. 142676, Japanese Unexamined Patent Publication No. Hei 4-245624 and Japanese Unexamined Patent Publication No. Sho 62-5868 in which anisotropic etching is performed at a certain angle with respect to the basic principal surface during etching.
According to the method described in Japanese Patent Application Publication No. 2 (1993), it is necessary to uniquely determine the directions of the source and the drain of the MOS type semiconductor device.
There is a disadvantage that the degree of freedom in layout design is limited.

【００１５】また、ゲート電極のパターニング時にマイ
クロローディング効果によりゲート電極形状を左右非対
称にする特開平２−１５８１４３号公報の手法では、エ
ッチングに過大な精度が要求され、高集積な半導体装置
を再現性よく製造することは困難である。本発明は上述
の状況に鑑みてなされたものであって、その目的は、レ
イアウト上の制約を受けることなく製造することがで
き、かつ量産安定性に優れた非対称ＬＤＤ構造を持つＭ
ＯＳ型半導体装置を提供することである。In the method disclosed in Japanese Patent Application Laid-Open No. 2-158143, in which the shape of the gate electrode is left-right asymmetric due to the microloading effect at the time of patterning the gate electrode, excessive precision is required for etching, and a highly integrated semiconductor device can be reproduced. It is difficult to manufacture well. The present invention has been made in view of the above-described circumstances, and has as its object to provide an MLD having an asymmetric LDD structure that can be manufactured without being restricted by layout and has excellent mass production stability.
An object of the present invention is to provide an OS type semiconductor device.

【００１６】[0016]

【課題を解決するための手段】上記目的を達成するため
に、本発明によれば、ゲート電極が２層以上の導体また
は半導体で形成され、少なくとも２層はドレイン拡散領
域端に整合し、その２層の内の上層膜はソース拡散領域
端に整合しており、その２層の内の下層膜はソース拡散
領域端には達しておらず、かつ、ソースはゲート端部ま
で高濃度不純物領域が形成され、ドレインはゲート近傍
は低濃度不純物領域となりこれに接して高濃度不純物領
域が形成されているＭＯＳ型半導体装置、が提供され
る。According to the present invention, in order to achieve the above object, according to the present invention, a gate electrode is formed of two or more layers of a conductor or a semiconductor, and at least two layers are formed of a drain diffusion region.
The upper layer of the two layers is the source diffusion region
The lower layer of the two layers is the source diffusion
A MOS type in which a high-concentration impurity region is not formed at the end of the region, a source has a high-concentration impurity region formed up to the gate end , and a drain has a low-concentration impurity region near the gate and a high-concentration impurity region is formed in contact with the low-concentration impurity region. A semiconductor device is provided.

【００１７】また、本発明によれば、（１）シリコン基
板上にゲート酸化膜を形成する工程と、（２）ゲート酸
化膜上の、ドレイン形成予定部およびゲート電極形成予
定部の一部を含みソース形成予定部には達しない領域上
に第１のゲート電極材膜を形成する工程と、（３）全面
に第２のゲート電極材膜を形成する工程〔図１（ａ）〕
と、（４）形成すべきゲート電極形状のフォトレジスト
膜を形成し〔図１（ｂ）〕これをマスクとして第２のゲ
ート電極材膜をエッチングして該膜をゲート電極の形状
に加工する工程と、（５）前記フォトレジスト膜または
前記第２のゲート電極材膜をマスクとして不純物のイオ
ン注入を行い、ドレイン形成領域に低濃度不純物領域
を、ソース形成領域に高濃度不純物領域を形成する工程
〔図１（ｃ）〕と、（６）前記フォトレジスト膜または
前記第２のゲート電極材膜をマスクとして前記第１のゲ
ート電極材膜をパターニングして、第１および第２のゲ
ート電極材膜からなるゲート電極を形成する工程と、
（７）絶縁膜の堆積とそのエッチバックにより前記ゲー
ト電極の側面に側壁絶縁膜を形成する工程〔図１
（ｄ）〕と、（８）前記ゲート電極および前記側壁絶縁
膜をマスクとして不純物のイオン注入を行い、ドレイン
形成領域内およびソース形成領域内に高濃度不純物領域
を形成する工程〔図１（ｅ）〕と、を含むＭＯＳ型半導
体装置の製造方法、が提供される。Further, according to the present invention, (1) a step of forming a gate oxide film on a silicon substrate; and (2) a part of a portion where a drain is to be formed and a portion where a gate electrode is to be formed on the gate oxide film. A step of forming a first gate electrode material film on a region that does not reach a portion where a source is to be formed, and (3) a step of forming a second gate electrode material film on the entire surface [FIG. 1 (a)]
And (4) forming a photoresist film having a gate electrode shape to be formed [FIG. 1 (b)], using this as a mask, etching the second gate electrode material film to process the film into the shape of a gate electrode. And (5) ion implantation of impurities using the photoresist film or the second gate electrode material film as a mask to form a low concentration impurity region in a drain formation region and a high concentration impurity region in a source formation region. Steps (FIG. 1C) and (6) patterning the first gate electrode material film using the photoresist film or the second gate electrode material film as a mask to form first and second gate electrodes; Forming a gate electrode made of a material film;
(7) A step of forming a sidewall insulating film on the side surface of the gate electrode by depositing an insulating film and etching back the insulating film [FIG.
(D)] and (8) a step of forming high-concentration impurity regions in the drain formation region and the source formation region by performing ion implantation of impurities using the gate electrode and the side wall insulating film as a mask [FIG. )], And a method of manufacturing a MOS type semiconductor device.

【００１８】[0018]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。図１（ａ）〜（ｅ）は、本発明の一実施例
のＭＯＳ型半導体装置の製造途中段階での断面図を工程
順に示したものである。ここではｎ型チャネルを持つＭ
ＯＳ型半導体装置を例にあげて説明する。イオン注入法
などでチャネル不純物濃度を所望の値に設定したｐ型シ
リコン基板１上に、例えば熱酸化法によりゲート酸化膜
２を形成する。Next, embodiments of the present invention will be described with reference to the drawings. 1A to 1E are cross-sectional views of a MOS type semiconductor device according to an embodiment of the present invention in the course of manufacturing in the order of steps. Here, M with n-type channel
An OS type semiconductor device will be described as an example. A gate oxide film 2 is formed on a p-type silicon substrate 1 in which a channel impurity concentration is set to a desired value by an ion implantation method or the like, for example, by a thermal oxidation method.

【００１９】次に、高濃度にリンなどのｎ型不純物がド
ープされた多結晶シリコン膜３ａを例えば低圧ＣＶＤ法
により成膜し、フォトリソグラフィ技術により所望の形
状にパターニングする。ここで多結晶シリコン膜の膜厚
は５０〜８０ｎｍに設定されている。この膜厚は、一般
的ポリシリコンゲートの１／２．５〜１／８程度であ
る。また多結晶シリコン膜３ａはその端部が少なくとも
ゲート形成部に達しており、そこからドレイン拡散層形
成領域に延在するようにする。また、多結晶シリコン膜
３ａへの不純物ドープ方法としてはノンドープの多結晶
シリコン膜を形成した後、リンなどを気相拡散してもよ
い。Next, a polycrystalline silicon film 3a heavily doped with an n-type impurity such as phosphorus is formed by, for example, a low pressure CVD method, and is patterned into a desired shape by photolithography. Here, the thickness of the polycrystalline silicon film is set to 50 to 80 nm. This film thickness is about 1 / 2.5 to 1/8 of a general polysilicon gate. The end of the polycrystalline silicon film 3a reaches at least the gate formation portion, and extends therefrom to the drain diffusion layer formation region. As a method of doping impurities into the polycrystalline silicon film 3a, a non-doped polycrystalline silicon film may be formed, and then phosphorus or the like may be vapor-phase diffused.

【００２０】次に、ゲート電極材３ｂを全面に形成す
る。ここでゲート電極材としては高濃度に不純物がドー
プされた多結晶シリコン膜、高融点シリサイド膜あるい
は多結晶シリコン膜と高融点金属シリサイド膜の積層構
造が適用される。このゲート電極材３ｂの膜厚は２００
〜４００ｎｍ程度に設定される〔図１（ａ）〕。Next, a gate electrode material 3b is formed on the entire surface. Here, as a gate electrode material, a polycrystalline silicon film doped with impurities at a high concentration, a high melting point silicide film, or a laminated structure of a polycrystalline silicon film and a high melting point metal silicide film is applied. The thickness of the gate electrode material 3b is 200
It is set to about 400 nm (FIG. 1A).

【００２１】次に、ゲート電極をパターニングするため
のフォトレジスト７ａを形成する。前述したように多結
晶シリコン膜３ａは一端が形成すべきゲート電極の内部
に達しているため、フォトレジスト７ａ直下に多結晶シ
リコン膜の端部が位置する〔図１（ｂ）〕。このフォト
リソグラフィ工程において、下地の段差は多結晶シリコ
ン膜３ａの５０〜８０ｎｍ程度であるため、再現性よく
高精度にパターニングを行うことができる。Next, a photoresist 7a for patterning the gate electrode is formed. As described above, since one end of the polycrystalline silicon film 3a has reached the inside of the gate electrode to be formed, the end of the polycrystalline silicon film is located immediately below the photoresist 7a (FIG. 1B). In this photolithography step, since the step of the base is about 50 to 80 nm of the polycrystalline silicon film 3a, patterning can be performed with high reproducibility and high accuracy.

【００２２】フォトレジスト７ａをマスクにゲート電極
材３ｂをエッチングする。ゲート電極材として多結晶シ
リコンを選択した場合、ゲート電極材下に位置する多結
晶シリコン膜３ａとのエッチング選択比がとりにくくな
るが、不純物のドープ量に差を設けることにより、ある
いは多結晶シリコン膜３ａの領域を小さくしエンドポイ
ントディテクターの設定を適切に行うことにより選択的
エッチングが実現できる。The gate electrode material 3b is etched using the photoresist 7a as a mask. When polycrystalline silicon is selected as the gate electrode material, it is difficult to obtain an etching selectivity with respect to the polycrystalline silicon film 3a located under the gate electrode material. Selective etching can be realized by reducing the area of the film 3a and appropriately setting the end point detector.

【００２３】次に、例えばヒ素をエネルギー７０ｋｅＶ
で１×１０15cm-2程度のドーズ量でイオン注入する。こ
れによりフォトレジスト７ａで覆われずかつ多結晶シリ
コン膜３ａに覆われない領域には、ピーク濃度２〜３×
１０20cm-3のソース高濃度不純物領域５ｂが形成され、
またフォトレジスト７ａに覆われずかつ多結晶シリコン
膜３ａに覆われた領域には、ピーク濃度１０18cm-3台の
ドレイン低濃度不純物領域４ａが形成される〔図１
（ｃ）〕。Next, for example, arsenic is converted to an energy of 70 keV.
At a dose of about 1 × 10 15 cm −2 . As a result, a peak concentration of 2 to 3 × is applied to a region that is not covered with the photoresist 7a and is not covered with the polycrystalline silicon film 3a.
A source high concentration impurity region 5b of 10 20 cm -3 is formed,
In a region not covered with the photoresist 7a and covered with the polycrystalline silicon film 3a, a drain low concentration impurity region 4a having a peak concentration of about 10 18 cm -3 is formed.
(C)].

【００２４】次いで、多結晶シリコン膜３ａをフォトレ
ジスト７ａをマスクにエッチングして、多結晶シリコン
膜３ａおよびゲート電極材３ｂの２層膜からなるゲート
電極３を形成する。続いて、フォトレジスト７ａを除去
した後、全面にＣＶＤ法などによりシリコンで酸化膜な
どの絶縁膜を１００〜１５０ｎｍの膜厚に成長させ、Ｃ
Ｆ4 系ガスによる異方性エッチングを行い、ゲート電極
側面にゲート側壁絶縁膜６を形成する〔図１（ｄ）〕。Next, the polysilicon film 3a is etched using the photoresist 7a as a mask to form a gate electrode 3 composed of a two-layer film of the polysilicon film 3a and the gate electrode material 3b. Subsequently, after removing the photoresist 7a, an insulating film such as an oxide film is grown to a thickness of 100 to 150 nm with silicon on the entire surface by CVD or the like.
Anisotropic etching using an F 4 -based gas is performed to form a gate sidewall insulating film 6 on the side surface of the gate electrode [FIG. 1 (d)].

【００２５】次に、ヒ素をエネルギー７０ｋｅＶ、ドー
ズ量１×１０15cm-2程度でイオン注入して、ドレイン高
濃度不純物領域５ａを形成するとともにソース高濃度不
純物領域５ｂの不純物濃度を高めることにより、本実施
例の非対称ＬＤＤ構造を持つＭＯＳ型半導体装置の作製
が完了する〔図１（ｅ）〕。なお、本実施例の図１
（ｃ）、図１（ｄ）に示す工程において、ゲート電極材
３ｂのパターニング後フォトレジスト７ａを除去し、ゲ
ート電極材３ｂをイオン注入用マスクあるいは多結晶シ
リコン膜３ａのパターニング用マスクとして用いるよう
にしてもよい。Next, arsenic energy 70 keV, and ion-implanted at a dose of 1 × 10 15 cm approximately -2 by increasing the impurity concentration of the source high impurity concentration region 5b to form a drain high concentration impurity regions 5a Then, the fabrication of the MOS semiconductor device having the asymmetric LDD structure of the present embodiment is completed [FIG. 1 (e)]. It should be noted that FIG.
(C) In the step shown in FIG. 1D, the photoresist 7a is removed after patterning the gate electrode material 3b, and the gate electrode material 3b is used as a mask for ion implantation or a mask for patterning the polycrystalline silicon film 3a. It may be.

【００２６】図２は、本発明の第２の実施例を示す断面
図である。同図において、ＭＯＳＦＥＴ１０は前述した
非対称ＬＤＤ構造を持つＭＯＳ型トランジスタであり、
ＭＯＳＦＥＴ２０は対称ＬＤＤ構造を持つＭＯＳ型トラ
ンジスタである。このＭＯＳＦＥＴ２０は、多結晶シリ
コン膜３ａをソース、ドレインの両方に延在させておく
ことにより、ソース、ドレインの両方にＬＤＤ領域を形
成したものである。このＭＯＳＦＥＴ２０は例えばトラ
ンスファゲートなど極性を持たないことが要求される回
路において有用である。FIG. 2 is a sectional view showing a second embodiment of the present invention. In FIG. 1, a MOSFET 10 is a MOS transistor having the asymmetric LDD structure described above.
The MOSFET 20 is a MOS transistor having a symmetric LDD structure. In this MOSFET 20, the LDD regions are formed in both the source and the drain by extending the polycrystalline silicon film 3a in both the source and the drain. This MOSFET 20 is useful in a circuit that is required to have no polarity, such as a transfer gate.

【００２７】この例で示されるように、本発明によるＭ
ＯＳ型半導体装置では、多結晶シリコン膜３ａのパター
ンによってＬＤＤの有無、ソース、ドレインの極性を自
在に設定できるので、設計自由度は極めて高い。As shown in this example, M
In the OS type semiconductor device, the presence / absence of LDD and the polarities of the source and drain can be freely set by the pattern of the polycrystalline silicon film 3a, so that the degree of design freedom is extremely high.

【００２８】以上好ましい実施例について説明したが、
本発明はこれら実施例に限定されるものではなく特許請
求の範囲に記載された要旨内において各種の変更が可能
である。例えば実施例では、多結晶シリコン膜３ａをド
レイン形成予定領域の全体を覆うように形成していたが
必ずしもこのようにする必要はなく、ゲート電極寄りの
一部の領域上のみを覆うようにしてもよい。The preferred embodiment has been described above.
The present invention is not limited to these embodiments, and various changes can be made within the gist of the claims. For example, in the embodiment, the polycrystalline silicon film 3a is formed so as to cover the entire region where the drain is to be formed. However, it is not always necessary to do so, and only the part of the region near the gate electrode is covered. Is also good.

【００２９】[0029]

【発明の効果】以上説明したように、本発明によるＭＯ
Ｓ型半導体装置は、多結晶シリコン層などの第１のゲー
ト電極材の有無によってＬＤＤ領域の形成を選択できる
ようにしたものであるので、第１の電極材のパターン形
状でＬＤＤ領域の有無を自在に決定でき、設計の自由度
を損なうことなく電流駆動能力に優れかつホットキャリ
ア耐性の高いＭＯＳ型半導体装置を実現することができ
る。さらに、ゲート電極パターニングにおけるフォトリ
ソグラフィ工程では、下地段差は高々第１のゲート電極
材の５０〜８０ｎｍ程度であるため、フォトリソグラフ
ィ工程への負担が小さく、再現性および量産性に優れた
工程において上記の半導体装置を実現できる。As described above, the MO according to the present invention is
In the S-type semiconductor device, the formation of the LDD region can be selected depending on the presence or absence of the first gate electrode material such as a polycrystalline silicon layer. Therefore, the presence or absence of the LDD region is determined by the pattern shape of the first electrode material. It is possible to realize a MOS type semiconductor device which can be freely determined, has excellent current driving capability and high hot carrier resistance without impairing the degree of freedom of design. Furthermore, in the photolithography process in the gate electrode patterning, since the underlying step is at most about 50 to 80 nm of the first gate electrode material, the burden on the photolithography process is small, and the above-mentioned process is excellent in reproducibility and mass productivity. Semiconductor device can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施例の製造方法を説明するた
めの工程順断面図。FIG. 1 is a cross-sectional view in a process order for describing a manufacturing method according to a first embodiment of the present invention.

【図２】本発明の第２の実施例のＭＯＳ型半導体装置の
断面図。FIG. 2 is a sectional view of a MOS type semiconductor device according to a second embodiment of the present invention.

【図３】従来の対称ＬＤＤ構造のＭＯＳ型半導体装置の
断面図。FIG. 3 is a sectional view of a conventional MOS type semiconductor device having a symmetric LDD structure.

【図４】非対称ＬＤＤ構造のＭＯＳ型半導体装置の従来
の製造方法を説明するための工程順断面図。FIG. 4 is a cross-sectional view in a process order for describing a conventional method for manufacturing a MOS semiconductor device having an asymmetric LDD structure.

【符号の説明】 １ ｐ型シリコン基板 １ａ シリコン基板 ２ ゲート酸化膜 ３ ゲート電極 ３ａ 多結晶シリコン膜 ３ｂ ゲート電極材 ４ 低濃度不純物領域 ４ａ ドレイン低濃度不純物領域 ４ｂ ソース低濃度不純物領域 ５ 高濃度不純物領域 ５ａ ドレイン高濃度不純物領域 ５ｂ ソース高濃度不純物領域 ６ ゲート側壁絶縁膜 ７ａ、７ｂ フォトレジスト[Description of Signs] 1 p-type silicon substrate 1a silicon substrate 2 gate oxide film 3 gate electrode 3a polycrystalline silicon film 3b gate electrode material 4 low concentration impurity region 4a drain low concentration impurity region 4b source low concentration impurity region 5 high concentration impurity Region 5a Highly doped drain region 5b Highly doped source region 6 Gate sidewall insulating film 7a, 7b Photoresist

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 ゲート電極が２層以上の導体または半導
体で形成され、少なくとも２層はドレイン拡散領域端に
整合し、その２層の内の上層膜はソース拡散領域端に整
合しており、その２層の内の下層膜はソース拡散領域端
には達しておらず、かつ、ソースはゲート端部まで高濃
度不純物領域が形成され、ドレインはゲート近傍は低濃
度不純物領域となりこれに接して高濃度不純物領域が形
成されていることを特徴とするＭＯＳ型半導体装置。A gate electrode is formed of two or more layers of a conductor or a semiconductor, and at least two layers are formed at an end of a drain diffusion region.
The upper layer of the two layers is aligned at the end of the source diffusion region.
The lower layer of the two layers is located at the end of the source diffusion region.
And the source has a high-concentration impurity region formed up to the end of the gate , and the drain has a low-concentration impurity region near the gate , and a high-concentration impurity region is formed in contact with the low-concentration impurity region. MOS type semiconductor device. 【請求項２】 ゲート電極が下層の多結晶シリコン膜と
上層のシリサイド膜を含む導電層とによって形成されて
いることを特徴とする請求項１記載のＭＯＳ型半導体装
置。2. A gate electrode is formed by a conductive layer comprising a lower layer of polycrystalline silicon film and an upper silicide film
2. The MOS type semiconductor device according to claim 1, wherein: 【請求項３】 ドレインを共通として形成された１対の
同種のトランジスタを含むことを特徴とする請求項１記
載のＭＯＳ型半導体装置。3. The MOS type semiconductor device according to claim 1, further comprising a pair of transistors of the same type formed with a common drain. 【請求項４】 請求項１に記載された非対称ＬＤＤ構造
のトランジスタと、ゲート電極が全長に渡って２層以上
の導体または半導体で形成され、ソース拡散領域および
ドレイン拡散領域がともに低濃度不純物領域と高濃度不
純物領域とを有する対称ＬＤＤ構造のトランジスタと、
を含むことを特徴とするＭＯＳ型半導体装置。4. The asymmetric LDD structure according to claim 1.
Transistor and a gate electrode are formed of two or more layers of conductors or semiconductors over the entire length, and a source diffusion region and
Both the low concentration impurity region and the high concentration
A transistor having a symmetric LDD structure having a pure region ;
A MOS type semiconductor device comprising: 【請求項５】 （１）シリコン基板上にゲート酸化膜を
形成する工程と、 （２）ゲート酸化膜上の、ドレイン形成予定部およびゲ
ート電極形成予定部の一部を含みソース形成予定部には
達しない領域上に第１のゲート電極材膜を形成する工程
と、 （３）全面に第２のゲート電極材膜を形成する工程と、 （４）形成すべきゲート電極形状のフォトレジスト膜を
形成しこれをマスクとして第２のゲート電極材膜をエッ
チングして該膜をゲート電極の形状に加工する工程と、 （５）前記フォトレジスト膜または前記第２のゲート電
極材膜をマスクとして不純物のイオン注入を行い、ドレ
イン形成領域に低濃度不純物領域を、ソース形成領域に
高濃度不純物領域を形成する工程と、 （６）前記フォトレジスト膜または前記第２のゲート電
極材膜をマスクとして前記第１のゲート電極材膜をパタ
ーニングして、第１および第２のゲート電極材膜からな
るゲート電極を形成する工程と、 （７）絶縁膜の堆積とそのエッチバックにより前記ゲー
ト電極の側面に側壁絶縁膜を形成する工程と、 （８）前記ゲート電極および前記側壁絶縁膜をマスクと
して不純物のイオン注入を行い、ドレイン形成領域内お
よびソース形成領域内に高濃度不純物領域を形成する工
程と、を含むことを特徴とするＭＯＳ型半導体装置の製
造方法。5. A step of (1) forming a gate oxide film on a silicon substrate; and (2) a step of forming a drain formation portion and a part of a gate electrode formation portion on the gate oxide film to form a source formation portion. Forming a first gate electrode material film on a region which does not reach, (3) forming a second gate electrode material film on the entire surface, and (4) forming a gate electrode-shaped photoresist film to be formed. Forming a second gate electrode material film using the mask as a mask to process the second gate electrode material film into a shape of a gate electrode; and (5) using the photoresist film or the second gate electrode material film as a mask. Performing ion implantation of impurities to form a low-concentration impurity region in a drain formation region and a high-concentration impurity region in a source formation region; and (6) masking the photoresist film or the second gate electrode material film. Patterning the first gate electrode material film to form a gate electrode composed of the first and second gate electrode material films; (7) depositing an insulating film and etching back the gate electrode to form the gate electrode; Forming a sidewall insulating film on the side surface of the semiconductor device; and (8) ion-implanting impurities using the gate electrode and the sidewall insulating film as masks to form high-concentration impurity regions in the drain formation region and the source formation region. And a method for manufacturing a MOS type semiconductor device. 【請求項６】 前記第（２）の工程において形成される
第１のゲート電極材膜の膜厚が、前記第（３）の工程に
おいて形成される第２のゲート電極材膜の膜厚より薄い
ことを特徴とする請求項５記載のＭＯＳ型半導体装置の
製造方法。6. The film thickness of the first gate electrode material film formed in the step (2) is larger than the film thickness of the second gate electrode material film formed in the step (3). 6. The method according to claim 5, wherein the device is thin.
JP6232283A 1994-09-01 1994-09-01 MOS type semiconductor device and method of manufacturing the same Expired - Lifetime JP2707977B2 (en)

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JP6232283A JP2707977B2 (en) 1994-09-01 1994-09-01 MOS type semiconductor device and method of manufacturing the same
US08/962,807 US5828104A (en) 1994-09-01 1997-11-03 MOS structure device having asymmetric LDD structure and fabrication method thereof

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JP6232283A JP2707977B2 (en) 1994-09-01 1994-09-01 MOS type semiconductor device and method of manufacturing the same

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JP2707977B2 true JP2707977B2 (en) 1998-02-04

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