JPH09181308A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device formed with LDD (lightly doped drain) structures via sidewall spacers of different widths. SOLUTION: First and second sidewall spacers 15 and 17 are formed on each sidewall part of a gate electrode 9 on a first element formation region (A), which is formed on a P-type semiconductor substrate 1, first sidewall spacers 15 are respectively formed on the sidewall parts of a gate electrode 9 on a second element formation region (B), which is formed on the substrate 1, and LDD structures, in which the spreading way of diffused layers in the LDD structure on one side is different from that of diffused layers in the other LDD structure, are respectively formed in the regions (A) and (B).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an LDD (Lightly Light) via a sidewall spacer having a different width according to various characteristics.
Doped Drain) A technique for providing a semiconductor device having a structure.

[0002]

2. Description of the Related Art A method of manufacturing a semiconductor device of this type will be described with reference to FIGS. First, as shown in FIG. 8, in order to separate each element formation region of the first element formation region (A) and the second element formation region (B) on the semiconductor substrate 51 of one conductivity type, for example, P type, LOCO as a separation membrane
The S oxide film 53 is formed.

Subsequently, as shown in FIG. 9, a gate oxide film 54 is formed on each element forming region of the first element forming region (A) and the second element forming region (B), and then the entire surface of the substrate is formed. 8E11 / cm @ 2 is implanted at a accelerating voltage of about 80 KeV with P-type impurities for adjusting the threshold of the N-channel MOS transistor, for example, boron ions (11B @ +),
The channel ion implantation layer 56 is formed.

Next, after forming a polysilicon film on the substrate, patterning is carried out by a well-known technique, as shown in FIG.
A gate electrode 59 is formed on each element forming region as shown in FIG. Then, using the gate electrode 59 as a mask, about 4 N-type impurities such as phosphorus ions (31 P +) are added.
By implanting 3E13 / cm @ 2 at an accelerating voltage of 0 KeV, the N @-type source diffusion layer 62 and the drain diffusion layer 63 are formed.
To form

Next, a SiO2 film is formed on the substrate and then etched back to form sidewall spacers 65 on the sidewalls of the gate electrode 59 as shown in FIG. Then, by using the gate electrode 59 and the sidewall spacer 65 as a mask, N-type impurities such as arsenic ions (75 As +) are implanted at 3E15 / cm @ 2 at an accelerating voltage of about 25 KeV to form an N + -type source diffusion layer 79. And the drain diffusion layer 80 was formed.

As described above, in the semiconductor device having the LDD structure, the widths of the sidewall spacers are all the same in the chip. Therefore, even if there is a desire to partially increase the current driving force, it is difficult because the spacer has a uniform width.

[0007]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device having an LDD structure formed through sidewall spacers having different widths.

[0008]

Therefore, in the semiconductor device of the present invention, the first and second semiconductor devices are formed on a semiconductor substrate of one conductivity type.
Sidewall spacers having different widths are formed on the side wall portions of the respective gate electrodes on the element forming region.
Further, in the semiconductor device of the present invention, sidewall spacers having different widths are formed on the sidewalls of the gate electrodes of the memory cell portion and the peripheral circuit portion formed on the semiconductor substrate of one conductivity type.

Further, according to the method of manufacturing a semiconductor device of the present invention, after forming an element isolation film for isolating the first and second element formation regions on a semiconductor substrate of one conductivity type, the element isolation film is formed on each element formation region. A gate oxide film is formed, and one conductivity type impurity for threshold adjustment is implanted into the entire surface of the substrate. Next, after forming a gate electrode on each of the element forming regions, using the gate electrode as a mask, an impurity of opposite conductivity type is implanted to diffuse a low concentration of opposite conductivity type so as to be adjacent to the lower end portion of the gate electrode. Form the layers. Subsequently, an oxide film is formed on the entire surface of the substrate and then etched back to form a first sidewall spacer on the side wall of the gate electrode. Further, a silicon nitride film is formed on the entire surface of the substrate and then etched back to form the first sidewall spacer. First
Forming a second side wall spacer so as to cover the side wall spacer. Next, after forming a resist film on the first element formation region, the second sidewall spacers on the second element formation region are removed by etching using the resist film as a mask. Then, after removing the resist film, a reverse conductivity type impurity is injected into the entire surface to form a high concentration reverse conductivity type on the first element formation region so as to be adjacent to the lower end of the second sidewall spacer. A diffusion layer is formed, and a high-concentration reverse conductivity type diffusion layer is formed on the second element formation region so as to be adjacent to the lower end of the first sidewall spacer.

According to the method of manufacturing a semiconductor device of the present invention, an element isolation film for separating a memory cell portion formation region and a peripheral circuit portion formation region from each other is formed on a semiconductor substrate of one conductivity type. A gate oxide film is formed on each element formation region of the peripheral circuit portion, and one conductivity type impurity for threshold adjustment is implanted into the entire surface of the substrate. Next, after forming a gate electrode on the memory cell portion formation region and the peripheral circuit portion formation region, an impurity of opposite conductivity type is implanted using the gate electrode as a mask so that the gate electrode is adjacent to the lower end portion of the gate electrode. A low-concentration reverse conductivity type diffusion layer is formed. Subsequently, an oxide film is formed on the entire surface of the substrate and then etched back to form a first sidewall spacer on the side wall of the gate electrode. Further, a silicon nitride film is formed on the entire surface of the substrate and then etched back to form the first sidewall spacer. A second sidewall spacer is formed so as to cover the first sidewall spacer. Next, after forming a resist film on the element forming region of the memory cell portion, the second sidewall spacer of the peripheral circuit portion is removed by etching using the resist film as a mask. Then, after removing the resist film,
A reverse conductivity type impurity is implanted into the entire surface to form a high concentration reverse conductivity type diffusion layer in the memory cell portion so as to be adjacent to the lower end portion of the second sidewall spacer, and the peripheral circuit portion is provided with the reverse conductivity type diffusion layer. A high-concentration reverse conductivity type diffusion layer is formed adjacent to the lower end of the first sidewall spacer.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings of FIGS. First, as shown in FIG. 1, one conductivity type,
For example, on the P-type semiconductor substrate 1, the first element formation region (A) is formed.
And LO as an element isolation film having a thickness of about 300 nm for separating each element formation region of the second element formation region (B).
The COS oxide film 3 is formed.

Subsequently, as shown in FIG. 2, a gate oxide film 4 having a film thickness of about 16 nm is formed on each element forming region of the first element forming region (A) and the second element forming region (B). After the formation, a P-type impurity for adjusting the threshold value of the N-channel MOS transistor, for example, boron ion (11B +) is formed on the entire surface of the substrate at an acceleration voltage of about 80 KeV and 8E1
A channel ion implantation layer 6 is formed by implanting 1 / cm @ 2.

Next, a polysilicon film having a thickness of about 210 nm is formed on the substrate and then patterned by a well-known technique to form each element of the memory cell portion and the peripheral circuit portion as shown in FIG. A gate electrode 9 is formed on the region. Then, using the gate electrode 9 as a mask, N-type impurities, for example, phosphorus ions (31 P +) are added to about 40K.
An N @-type source diffusion layer 12 and a drain diffusion layer 13 are formed by implanting 3E13 / cm @ 2 at an accelerating voltage of eV.

Next, an oxide film (SiO2 film) is formed on the substrate.
By etching back after forming the gate electrode, a width of about 0.1 μm is formed on the side wall of the gate electrode 9 as shown in FIG.
m first sidewall spacers 15 are formed. Further, a silicon nitride film (SiN film) is formed on the substrate and then etched back to cover the first sidewall spacers 15 formed on the sidewalls of the gate electrode 9 as shown in FIG. Width of about 0.05μ
m second sidewall spacers 17 are formed.

Subsequently, a resist film 18 is formed on the first element formation region (A), and then a silicon nitride film (SiN film) is formed on the second element formation region (B). For example, the second sidewall spacer 17 is etched under the conditions of RF power of 200 W under the conditions that the flow rates of etching gases CF4, CHF3 and Ar are 50 sccm, 30 sccm and 900 sccm, respectively, and the pressure is 1600 mTorr. This step is a step which characterizes the present invention, and as described above, the second sidewall spacers 17 formed on the second element formation region (B) are removed,
The second sidewall spacer 17 formed on the first element formation region (A) masked with the resist film 18.
Is not removed, a sidewall spacer having a width of about 0.15 μm is formed on the first element formation region (A) and a width of about 0.15 μm is formed on the second element formation region (B).
A sidewall spacer of μm is formed.

Then, using the gate electrode 9 and each sidewall spacer as a mask, an N-type impurity, for example,
By implanting arsenic ions (75 As +) at an accelerating voltage of about 25 KeV and 3E15 / cm @ 2, the first element formation region (A) is adjacent to the lower end of the second sidewall spacer 17 as shown in FIG. The N + type source diffusion layer 20 and the drain diffusion layer 21 are formed so that the first sidewall spacer 1 is formed in the second element formation region (B).
An N + type source diffusion layer 22 and a drain diffusion layer 23 are formed so as to be adjacent to the lower end portion of No. 5. In this way, it is possible to form an LDD structure in which the diffusion layers spread differently in the first element formation region (A) and the second element formation region (B). The present invention can be applied to, for example, a single 3V power source, a single 5V power source, or a shared 3V and 5V power source.

Although not shown, an interlayer insulating film is formed on the entire surface of the substrate, and then a contact hole is formed on each diffusion layer.
Metal wiring is formed through the contact hole. As an embodiment corresponding to the first element formation region (A) and the second element formation region (B) of the present invention, for example, a memory cell portion and a peripheral circuit portion may be applied. The memory cell section may be operated with a 3V system, and the peripheral circuit section may be operated with a 5V system, and further, a 3V single power source or a 5V single power source is also applicable.

As described above, in the semiconductor device according to the embodiment of the present invention, it is possible to form the sidewall spacer having two kinds of widths. For example, in the portion where reliability is desired to be increased, the sidewall spacer is widened to achieve high driving. This can be achieved by narrowing the sidewall spacers at the portion where the force is desired.

[0019]

As described above, according to the present invention, it is possible to form a sidewall spacer having a plurality of types of widths. For example, in a portion where reliability is desired to be increased, the sidewall spacer is widened and a portion where high driving force is desired to be obtained. Can be realized by narrowing the side wall spacers, and the high performance of the LSI can be achieved.

Further, according to the present invention, the sidewall spacers having plural kinds of widths can be formed by a simple method.

[Brief description of the drawings]

FIG. 1 is a first cross-sectional view showing a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a second cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 3 is a third cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 4 is a fourth cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 5 is a fifth cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 6 is a sixth cross-sectional view showing the method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a seventh cross-sectional view showing the method for manufacturing the semiconductor device of the present invention.

FIG. 8 is a first sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 9 is a second cross-sectional view illustrating the conventional method for manufacturing a semiconductor device.

FIG. 10 is a third cross-sectional view showing the method of manufacturing the conventional semiconductor device.

FIG. 11 is a fourth sectional view showing the conventional method for manufacturing a semiconductor device.

Claims (4)

[Claims] 1. A semiconductor device in which side wall spacers having different widths are formed on side wall portions of respective gate electrodes formed on a semiconductor substrate of one conductivity type. 2. A semiconductor device, wherein side wall spacers having different widths are formed on side wall portions of respective gate electrodes of a memory cell portion and a peripheral circuit portion formed on a semiconductor substrate of one conductivity type. . 3. The first and second layers are formed on a semiconductor substrate of one conductivity type.
Forming an element isolation film for separating each element formation region, forming a gate oxide film on each element formation region, and implanting one conductivity type impurity for threshold adjustment on the entire surface of the substrate A step of forming a polysilicon film on the entire surface of the substrate and then patterning it to form a gate electrode on each element forming region; and a step of implanting an impurity of opposite conductivity type by using the gate electrode as a mask to form a lower end of the gate electrode. A low-concentration reverse-conductivity-type diffusion layer adjacent to the substrate, and forming an oxide film on the entire surface of the substrate and then etching back to form a first sidewall spacer on the sidewall of the gate electrode. And forming a second sidewall spacer so as to cover the first sidewall spacer by etching back after forming a silicon nitride film on the entire surface of the substrate. And a step of forming a resist film on the first element formation region and then etching away the second sidewall spacers on the second element formation region using the resist film as a mask. After the film is removed, a reverse conductivity type impurity is implanted into the entire surface to form a high concentration reverse conductivity type diffusion layer on the first element formation region so as to be adjacent to the lower end of the second sidewall spacer. And a step of forming a high-concentration reverse-conductivity-type diffusion layer on the second element formation region so as to be adjacent to the lower end portion of the first sidewall spacer. Production method. 4. A step of forming an element isolation film for respectively separating a memory cell part formation region and a peripheral circuit part formation region on a semiconductor substrate of one conductivity type, and each element formation region of the memory cell part and the peripheral circuit part. Forming a gate oxide film on the substrate; implanting one conductivity type impurity for threshold adjustment on the entire surface of the substrate; forming a polysilicon film on the entire surface of the substrate; And a step of forming a gate electrode on the peripheral circuit part formation region, and a low-concentration reverse-conductivity-type diffusion layer having a low-concentration diffused layer so as to be adjacent to the lower end of the gate electrode by implanting a reverse-conductivity-type impurity using the gate electrode as a mask. A step of forming an oxide film on the entire surface of the substrate and then etching back to form a first sidewall spacer on the side wall of the gate electrode; Forming a second sidewall spacer so as to cover the first sidewall spacer by etching back after forming the recon nitride film; and forming a resist film on the element forming region of the memory cell portion. After that, a step of etching away the second sidewall spacers of the peripheral circuit section by using the resist film as a mask, and a step of removing the resist film and then implanting an impurity of opposite conductivity type into the entire surface of the memory cell section A high-concentration reverse-conductivity-type diffusion layer is formed adjacent to the lower end of the second sidewall spacer, and a high-concentration reverse diffusion layer is formed in the peripheral circuit portion so as to be adjacent to the lower end of the first sidewall spacer. And a step of forming a diffusion layer of opposite conductivity type.