JPH04305922A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce contact resistance and dispersion thereof even when an element is made fine by forming an impurity region exposed to an opening section and a second conductive layer electrically connected to a first conductive layer. CONSTITUTION:As ions are implanted to a P-type silicon substrate 1 while using a gate electrode 4a, a wiring layer 4b and sidewall films 5a as masks. Consequently, an N<+> diffusion layer 6 is formed. An inter-layer oxide film 7 is formed on the whole surface, and a contact-hole 8 is bored at a specified position. The sidewall film 5a in the contact-hole 8 and an oxide film 3b under the film 5a are removed. Lastly, a polysilicon film 9 is shaped into the contact- hole 8 so as to be connected to all of the N<+> diffusion layer 6, N<-> diffusion layers 6a and the wiring layer 4b composed of a polysilicon film. Accordingly, a semiconductor device is formed.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, it has a contact portion with a so-called shared contact structure in which a conductive layer is connected to both a wiring layer and a semiconductor substrate within one contact hole. The present invention relates to a semiconductor device and its manufacturing method.

0002

[Prior Art] Conventionally, one of the contact structures of semiconductor devices is
One known example is a shared contact structure in which a conductive layer is connected to both a wiring layer and a semiconductor substrate within one contact hole.

FIG. 10 is a sectional view showing a semiconductor device having a contact portion with a conventional shared contact structure. Referring to FIG. 10, the conventional semiconductor device includes a P-type silicon substrate 1, an n+ diffusion layer 6 formed on the P-type silicon substrate 1 at a predetermined interval, and an end portion of the n+ diffusion layer 6. The formed n- diffusion layer 6a and n+ diffusion layer 6
an isolation oxide film 2 for element isolation formed at a predetermined distance from the gate electrode 4a formed of a polysilicon film formed between adjacent n+ diffusion layers 6 with a gate oxide film 3a interposed therebetween; A wiring layer 4b made of a polysilicon film is formed between the n+ diffusion layer 6 and the isolation oxide film 2 via an oxide film 3b, and a sidewall film 15a is formed on the sidewall portions of the gate electrode 4a and the wiring layer 4b. , an interlayer insulating film 14 formed on the P-type silicon substrate 1, the gate electrode 4a and the wiring layer 4b, and having a contact hole 8 through which a part of the n+ diffusion layer 6 and a part of the wiring layer 4b are exposed; A polysilicon film 9 is formed in the hole 8 so as to be electrically connected to both the n+ diffusion layer 6 and the wiring layer 4b. LDD (Lightly Doped Dra) is formed by the n- diffusion layer 6a.
in) the structure is configured. An N-type MOS transistor is constituted by two adjacent n+ diffusion layers 6, two opposing n- diffusion layers 6a, a gate oxide film 3a, and a gate electrode 4a. Furthermore, as described above, the polysilicon film 9 is connected to both the n+ diffusion layer 6 and the wiring layer 4b, forming a shared contact structure.

11 to 15 are cross-sectional views for explaining the manufacturing process of the conventional semiconductor device shown in FIG. 10.

Next, a conventional semiconductor device manufacturing process will be described with reference to FIGS. 11 to 15.

First, as shown in FIG. 11, an isolation oxide film 2 for element isolation is formed on a P-type silicon substrate 1. After forming an oxide film 3 on the entire surface, a polysilicon film is formed. By patterning this polysilicon film, a gate electrode 4a and a wiring layer 4b are formed.

Next, as shown in FIG. 12, the gate electrode 4a
Then, phosphorus (P) 10 is ion-implanted using the wiring layer 4b as a mask.

Next, as shown in FIG. 13, an oxide film 15 is formed by CVD.

Next, as shown in FIG. 14, the entire surface of the oxide film 15 (see FIG. 13) is etched back using anisotropic etching to form a sidewall film 15a. Arsenic (As) 12 is ion-implanted into the P-type silicon substrate 1 using an ion implantation method.

Next, as shown in FIG. 15, after forming an interlayer insulating film 14 over the entire surface, contact holes 8 are opened at predetermined positions. Since this contact hole 8 requires fine processing, it is usually formed by anisotropic etching. Therefore, the sidewall film 15a remains also on the sidewall portion of the wiring layer 4b.

Finally, as shown in FIG. 10, a polysilicon film 9 is formed in the contact hole 8, electrically connected to both the wiring layer 4b and the n+ diffusion layer 6. In this manner, a semiconductor device having a contact portion with a conventional shared contact structure was formed.

0012

[Problems to be Solved by the Invention] As mentioned above, in a semiconductor device having a contact portion with a conventional shared contact structure, when forming a contact hole 8 in an interlayer insulating film 14, anisotropy is required due to the necessity of microfabrication. It was necessary to use etching. Therefore, the sidewall film 15a remained on the sidewall portion of the wiring layer 4b as well.

However, in the shape in which the sidewall film 15a remains, the contact area between the n+ diffusion layer 6 and the polysilicon film 9 and the polysilicon film 9
There was a problem in that the contact area between the wiring layer 4b and the wiring layer 4b was reduced. In particular, this tendency becomes remarkable as elements become finer as semiconductor devices become more integrated. When the contact area decreases in this way, the connection resistance at the contact portion increases and the sidewall film 1
There was a problem in that the variation in connection resistance increased due to variations in the film thickness of the film 5a. This invention was made to solve the above problems, and even when elements are miniaturized with the integration of semiconductor devices, contact resistance (connection resistance) and contact resistance (connection resistance) An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce variations in the semiconductor device.

[0014]

A semiconductor device according to claim 1 includes: a semiconductor substrate; an impurity region formed on the main surface of the semiconductor substrate and having a low concentration region and a high concentration region; and an impurity region on the semiconductor substrate. a first conductive layer formed adjacent to the low concentration region; an insulating layer formed on the semiconductor substrate and having an opening through which the impurity region and a portion of the first conductive layer are exposed; and a second conductive layer formed on the semiconductor substrate so as to be electrically connected to the exposed impurity region and the first conductive layer.

A method for manufacturing a semiconductor device according to a second aspect of the present invention includes the steps of forming a first conductive layer on a semiconductor substrate via a first insulating film and then patterning it into a predetermined shape; and masking the first conductive layer. The first step is to form a low-concentration impurity region by ion-implanting impurities into the semiconductor substrate, and to form a second insulating film on the entire surface and then perform anisotropic etching to form a sidewall portion of the first conductive layer. A step of forming a sidewall insulating film on the semiconductor substrate, a step of forming a highly concentrated impurity region by ion-implanting impurities into the semiconductor substrate using the sidewall insulating film as a mask, and etching after forming a third insulating film on the entire surface. a step of forming an opening such that a part of the impurity region, a part of the first conductive layer, and a sidewall insulating film are exposed; a second conductive layer electrically connected to the exposed impurity region and the first conductive layer;
and a step of forming a conductive layer.

[0016]

[Operation] In the semiconductor device according to claim 1, the first impurity region adjacent to the low concentration region of the impurity region formed on the semiconductor substrate.
A conductive layer is formed, an insulating layer having an opening that exposes a portion of the impurity region and the first conductive layer is formed, and the exposed impurity region and the first conductive layer are electrically connected. Since the second conductive layer is formed so as to connect, there is no reduction in contact area due to a sidewall film on the sidewall portion of the first conductive layer as in the conventional case, and the impurity region and the sidewall portion of the first conductive layer are not reduced. The effective contact area at is increased.

In the method for manufacturing a semiconductor device according to claim 2, after forming an opening in the third insulating film, the sidewall insulating film formed on the sidewall portion of the first conductive layer in the opening and the sidewall thereof are removed. Since the first insulating film under the insulating film is removed, the effective contact area at the impurity region and the sidewall portion of the first conductive layer is increased. Moreover, the step coverage of the interlayer insulating film formed on the adjacent gate electrode and the upper layer wiring formed thereon is not impaired.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a semiconductor device having a contact portion with a shared contact structure according to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor device of this embodiment includes a P-type silicon substrate 1, an isolation oxide film 2 formed in a predetermined region on the P-type silicon substrate 1 for element isolation, and
Between the n+ diffusion layer 6 formed at a predetermined interval in a predetermined region on the P-type silicon substrate 1, the n− diffusion layer 6a formed at the end of the n+ diffusion layer 6, and the adjacent n+ diffusion layer 6 A gate electrode 4a formed through a gate oxide film 3a, and a wiring layer 4b formed in a region between the n+ diffusion layer 6 and the isolation oxide film 2 and on the isolation oxide film 2 through an oxide film 3b. , a sidewall film 5a formed on both side wall portions of the gate electrode 4a, an interlayer oxide film ( n+ in the contact hole 8 of the interlayer insulating film) 7 and the interlayer oxide film 7.
The diffusion layer 6 includes a polysilicon film 9 formed to be electrically connected to the n- diffusion layer 6a and the wiring layer 4b. In this embodiment, as in the conventional semiconductor device shown in FIG. 10, a so-called shared contact is formed in which a polysilicon film 9 is connected to both the n+ diffusion layer 6, the n- diffusion layer 6a, and the wiring layer 4b within the contact hole 8. It has a structure. In addition, two adjacent n+ diffusion layers 6,
Two opposing n- diffusion layers 6a and gate oxide film 3a
and gate electrode 4a constitute an N-type MOS transistor. Note that the n- diffusion layer 6a constitutes an LDD structure.

As described above, in this embodiment, unlike the conventional case, no sidewall film is formed on the sidewall portion of the wiring layer 4b. As a result, the contact area between polysilicon film 9 and n+ diffusion layer 6 and the contact area between polysilicon film 9 and interconnection layer 4b are effectively increased compared to the prior art. As a result, it is possible to effectively reduce contact resistance and variations in contact resistance when elements are miniaturized as a result of integration of semiconductor devices, which has been a problem in the past.

FIGS. 2 to 7 are cross-sectional views for explaining the manufacturing process of the semiconductor device shown in FIG. 1. Next, the manufacturing process will be described with reference to FIGS. 2 to 7.

First, as shown in FIG. 2, an isolation oxide film 2 for element isolation is formed on a P-type silicon substrate 1. After forming an oxide film 3 on the entire surface, a polysilicon film is formed on the oxide film 3. By patterning this polysilicon film, a gate electrode 4a and a wiring layer 4b are formed.

Next, as shown in FIG. 3, the gate electrode 4a
and the wiring layer 4b as a mask, the P-type silicon substrate 1
Phosphorus (P) 10 is ion-implanted. As a result, n-
A diffusion layer 6a is formed.

Next, as shown in FIG. 4, a nitride film 5 is formed over the entire surface using the CVD method.

Next, as shown in FIG. 5, the nitride film 5 is anisotropically etched to form a sidewall film 5 on both sidewalls of the gate electrode 4a and the sidewalls of the wiring layer 4b.
form a. Arsenic (As) 12 is ion-implanted into P-type silicon substrate 1 using gate electrode 4a, wiring layer 4b, and sidewall film 5a as masks. As a result, an n+ diffusion layer 6 as shown in FIG. 6 is formed. Thereafter, an interlayer oxide film 7 is formed over the entire surface, and then a contact hole 8 is opened at a predetermined position. That is, contact hole 8 penetrates interlayer oxide film 7, a part of which reaches n+ diffusion layer 6, and the remaining part reaches wiring layer 4b. Sidewall film 5a remains within contact hole 8.

As shown in FIG. 7, sidewall film 5a (see FIG. 6) in contact hole 8 and oxide film 3b thereunder are removed. That is, the sidewall film 5a made of a nitride film is selectively removed using hot phosphoric acid at about 170° C., for example. Thereafter, oxide film 3b is removed using anisotropic etching. When removing this oxide film 3b,
Since the interlayer oxide film 7 is shaved and its thickness is reduced, it is preferable to form it thickly in advance in consideration of the thickness reduction.

Finally, as shown in FIG. 1, a polysilicon film 9 is formed in the contact hole 8 so as to be connected to both the n+ diffusion layer 6, the n- diffusion layer 6a, and the wiring layer 4b made of a polysilicon film. form. In this way,
The semiconductor device of this example is formed.

As described above, in the semiconductor device manufacturing method of this embodiment, after opening the contact hole 8, the sidewall film 5a in the contact hole 8 and the oxide film 3b below it are removed. n- diffusion layer 6
The effective contact area at the surface a and the side wall portion of the wiring layer 4b increases. Also, since only the sidewall film 5a inside the contact hole 8 is removed, the gate electrode 4
This does not impair the step coverage of the interlayer insulating film formed on a or the upper layer wiring formed thereon.

Note that in this embodiment, the sidewall film 5
Although a nitride film is used as a, the present invention is not limited to this, and an oxide film may also be used. When using an oxide film as the sidewall film, changing the oxide film 3b and the interlayer oxide film 7 to nitride films allows the sidewall film made of the oxide film to be removed with better control. Further, although this embodiment shows an example in which the present invention is applied to an N-type MOS region, the present invention is not limited to this, and similar effects can be obtained even when applied to a P-type MOS region. Furthermore, in the manufacturing process shown in Fig. 5, arsenic (
A similar effect can be obtained by removing the sidewall film 5a over the entire surface after introducing As).

[0031] Furthermore, as the sidewall film, a sidewall film made of a multilayer film consisting of a combination of an oxide film and a polysilicon film may be used. FIGS. 8 and 9 are cross-sectional views for explaining a method of forming a sidewall film according to another embodiment of the present invention. Referring to FIGS. 8 and 9, after forming the oxide film 15 in advance also on the side wall portions of the gate electrode 4a and the wiring layer 4b, the polysilicon film 15 is
form 6. As a result, a sidewall film consisting of the oxide film 15 and the polysilicon film 16 can be formed. With a sidewall film made of a multilayer film as described above, it is possible to form and remove the sidewall film more stably.

[0032]

According to the semiconductor device according to claim 1,
A first conductive layer is formed adjacent to a low concentration region of an impurity region formed on a semiconductor substrate, and an insulating layer having an opening through which a portion of the impurity region and the first conductive layer is exposed is formed. However, by forming the second conductive layer so as to be electrically connected to the exposed impurity region in the opening and the first conductive layer, unlike the conventional method, the sidewall of the sidewall portion of the first conductive layer is Without the film, the effective contact area at the impurity region and the sidewall portion of the first conductive layer is increased. This makes it possible to effectively reduce contact resistance and variations in contact resistance even when elements are miniaturized as semiconductor devices become more integrated.

In the method for manufacturing a semiconductor device according to the second aspect, an opening is formed in the third insulating film so that a part of the impurity region, a part of the first conductive layer, and the sidewall insulating film are exposed. After that, by removing the side wall insulating film in the opening and the first insulating film under the side wall insulating film, the first insulating film is removed as in the conventional method.
There is no problem that the contact area is reduced due to the sidewall insulating film on the sidewall portion of the conductive layer, and the impurity region and the first
The effective contact area at the sidewall portion of the conductive layer is increased. As a result, even when elements are miniaturized as semiconductor devices become more integrated, contact resistance and variations in contact resistance can be reduced. Furthermore, by removing only the sidewall insulating film within the opening, there is an effect that step coverage of the interlayer insulating film formed on the adjacent gate electrode and the upper layer wiring formed thereon is not impaired.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a semiconductor device having a contact portion with a shared contact structure according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 1;

3 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 1. FIG.

4 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 1. FIG.

5 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 1. FIG.

6 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 1. FIG.

7 is a cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 1. FIG.

FIG. 8 is a cross-sectional view for explaining a method of forming a sidewall film according to another embodiment of the present invention.

FIG. 9 is a cross-sectional view for explaining a method of forming a sidewall film according to another embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a semiconductor device having a contact portion with a conventional shared contact structure.

11 is a cross-sectional view for explaining the manufacturing process of the conventional semiconductor device shown in FIG. 1. FIG.

12 is a cross-sectional view for explaining the manufacturing process of the conventional semiconductor device shown in FIG. 1. FIG.

13 is a cross-sectional view for explaining a manufacturing process of the conventional semiconductor device shown in FIG. 1. FIG.

14 is a cross-sectional view for explaining the manufacturing process of the conventional semiconductor device shown in FIG. 1. FIG.

15 is a cross-sectional view for explaining a manufacturing process of the conventional semiconductor device shown in FIG. 1. FIG.

[Explanation of symbols]

1 P-type silicon substrate 2 Isolation oxide film 3 Oxide film 3a Gate oxide film 3b Oxide film 4a Gate electrode 4b Wiring layer 5 Nitride film 5a Sidewall membrane 6 n+ diffusion layer 6a n- diffusion layer 7 Interlayer insulation film (interlayer oxide film) 8 Contact hole 9 Polysilicon film

Claims (2)

[Claims] 1. A semiconductor substrate, an impurity region formed on the main surface of the semiconductor substrate and having a low concentration region and a high concentration region, and an impurity region on the semiconductor substrate adjacent to the low concentration region of the impurity region. a first conductive layer formed on the semiconductor substrate; an insulating layer formed on the semiconductor substrate and having an opening through which the impurity region and a part of the first conductive layer are exposed;
A semiconductor device comprising: an exposed impurity region within the opening; and a second conductive layer formed on the semiconductor substrate so as to be electrically connected to the first conductive layer. 2. A step of forming a first conductive layer on a semiconductor substrate via a first insulating film, and then patterning it into a predetermined shape, and using the first conductive layer as a mask, doping impurities on the semiconductor substrate. ion implantation to form a low concentration impurity region, and after forming a second insulating film on the entire surface, anisotropic etching is performed to
forming a sidewall insulating film on the sidewall portion of the conductive layer; forming a highly concentrated impurity region by ion-implanting impurities into the semiconductor substrate using the sidewall insulating film as a mask; After forming the insulating film No. 3, etching is performed to form an opening in which a part of the impurity region, a part of the first conductive layer, and the sidewall insulating film are exposed; removing a sidewall insulating film and a first insulating film under the sidewall insulating film, and forming a second conductive layer so as to be electrically connected to the exposed impurity region and the first conductive layer. A method for manufacturing a semiconductor device, comprising a process.